Types of Instructions

Based on the number of addresses, instructions are classified as:

NOTE: We will use the X = (A+B)*(C+D) expression to showcase
the procedure.
• Zero Address Instructions
These instructions do not specify any operands or addresses.
Instead, they operate on data stored in registers or memory
locations implicitly defined by the instruction. For example, a
zero-address instruction might simply add the contents of two
registers together without specifying the register names.

A stack-based computer does not use the address field in the

instruction. To evaluate an expression, it is first converted to
reverse Polish Notation i.e. Postfix Notation.

Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location
 Types of Instructions
• One Address Instructions
These instructions specify one operand or address, which typically
refers to a memory location or register. The instruction operates on
the contents of that operand, and the result may be stored in the
same or a different location. For example, a one-address instruction
might load the contents of a memory location into a register.

This uses an implied ACCUMULATOR register for data manipulation. Expression: X = (A+B)*(C+D)
One operand is in the accumulator and the other is in the register or
memory location. Implied means that the CPU already knows that AC is accumulator
one operand is in the accumulator so there is no need to specify it. M[] is any memory location
M[T] is temporary location
Types of Instructions
• Two Address Instructions
These instructions specify two operands or
addresses, which may be memory locations or
registers. The instruction operates on the contents of
both operands, and the result may be stored in the
same or a different location. For example, a two-
address instruction might add the contents of two
registers together and store the result in one of the
registers. Here destination address can
also contain an operand.
This is common in commercial computers. Here two
addresses can be specified in the instruction. Unlike Expression: X = (A+B)*(C+D)
earlier in one address instruction, the result was R1, R2 are registers
stored in the accumulator, here the result can be M[] is any memory location
stored at different locations rather than just
accumulators, but require more number of bit to
represent the address.
 Types of Instructions
• Three Address Instructions
These instructions specify three operands or addresses,
which may be memory locations or registers. The
instruction operates on the contents of all three operands,
and the result may be stored in the same or a different
location. For example, a three-address instruction might
multiply the contents of two registers together and add the
contents of a third register, storing the result in a fourth
register.

This has three address fields to specify a register or a

memory location. Programs created are much short in size Expression: X = (A+B)*(C+D)
but number of bits per instruction increases. These R1, R2 are registers
instructions make the creation of the program much easier M[] is any memory location
but it does not mean that program will run much faster
because now instructions only contain more information
but each micro-operation (changing the content of the
register, loading address in the address bus etc.) will be
performed in one cycle only.
Lecture 21
Control Unit: instruction cycles and sub cycles
Instruction cycles
• A program consisting of the memory unit of the
computer includes a series of instructions. The
program is implemented on the computer by going
through a cycle for each instruction.

• In the basic computer, each instruction cycle includes

the following procedures −

• It can fetch instruction from memory.

• It is used to decode the instruction.
• It can read the effective address from memory if the
instruction has an indirect address.
• It can execute the instruction.
Instruction cycles
• After the following four procedures are done, the
control switches back to the first step and repeats
the similar process for the next instruction.
Therefore, the cycle continues until a Halt condition
is met. The figure shows the phases contained in the
instruction cycle.
• As display in the figure, the halt condition appears
when the device receive turned off, on the
circumstance of unrecoverable errors, etc.
• Fetch Cycle
• The address instruction to be implemented is held at
the program counter. The processor fetches the
instruction from the memory that is pointed by the
PC.
• Next, the PC is incremented to display the address of
the next instruction. This instruction is loaded onto
the instruction register. The processor reads the
instruction and executes the important procedures.
 Instruction cycles
• Execute Cycle
• The data transfer for implementation takes place in
two methods are as follows −
• Processor-memory − The data sent from the
processor to memory or from memory to processor.
• Processor-Input/Output − The data can be transferred
to or from a peripheral device by the transfer
between a processor and an I/O device.
• In the execute cycle, the processor implements the
important operations on the information, and
consistently the control calls for the modification in
the sequence of data implementation. These two
methods associate and complete the execute cycle.
 State Diagram for Instruction Cycle
• The figure provides a large aspect of the
instruction cycle of a basic computer, which is in
the design of a state diagram. For an instruction
cycle, various states can be null, while others can
be visited more than once.
• Instruction Address Calculation − The address of
the next instruction is computed. A permanent
number is inserted to the address of the earlier
instruction.
• Instruction Fetch − The instruction is read from its
specific memory location to the processor.
 State Diagram for Instruction Cycle
• Instruction Operation Decoding − The instruction
is interpreted and the type of operation to be
implemented and the operand(s) to be used are
decided.
• Operand Address Calculation − The address of the
operand is evaluated if it has a reference to an
operand in memory or is applicable through the
Input/Output.
• Operand Fetch − The operand is read from the
memory or the I/O.
• Data Operation − The actual operation that the
instruction contains is executed.
• Store Operands − It can store the result acquired
in the memory or transfer it to the I/O.
Lecture 22
Control Unit:micro operations, execution of a
complete instruction
 micro operations, execution of a complete
instruction
• Micro-operations are the basic elementary operations carried out on data stored in registers.
• Controlled by the Control Unit (CU).
• A complete machine instruction is executed by performing a sequence of micro-operations.

• Types of Micro-Operations
Register Transfer Micro-operations
• Transfer data between registers.
• Example: R1 ← R2

Arithmetic Micro-operations
• Perform arithmetic on data.
• Example: R1 ← R1 + R2
micro operations, execution of a complete
instruction
Logic Micro-operations
Perform bitwise operations.
Example: R1 ← R1 AND R2

Control Micro-operations
Change the sequence of execution.
Example: Branch, Jump

Memory Transfer Micro-operations

Data transfer between memory and registers.
Example: R1 ← M[1000]
micro operations, execution of a complete
instruction
A complete instruction goes through the Instruction Cycle:
• Fetch Phase (Micro-operations)
MAR ← PC (Load memory address register with PC)
MDR ← M[MAR] (Fetch instruction from memory)
IR ← MDR (Load instruction into IR)
PC ← PC + 1 (Increment PC)

• Decode Phase (Micro-operations)

CU decodes Opcode from IR.
Determine operand address & addressing mode.

• Execute Phase (Micro-operations Example: ADD instruction)

Suppose instruction is: ADD R1, R2
R1 ← R1 + R2 (ALU operation)
Result stored back in destination register.
micro operations, execution of a complete
instruction
Memory Reference Instruction Example
Instruction: LOAD R1, X
MAR ← X
MDR ← M[MAR]
R1 ← MDR

Branch/Control Instruction Example

Instruction: JUMP LABEL
PC ← LABEL

Control Signals for Micro-Operations

CU generates control signals to trigger these micro-operations.
Example signals:
Read / Write (Memory operations)
Load (Register load)
Increment (PC update)
ALU operation signals (ADD, SUB, etc.)
Lecture 23
Control Unit:Program Control, Reduced Instruction
Set Computer
 Program Control
• Program Control instructions manage the sequence of instruction execution in a computer system.
• They control the flow of the program, not the data directly.

Types of Program Control Instructions

1. Compare Instruction
• Compare instruction is specifically provided, which is similar to a subtract instruction except the result is not stored anywhere, but flags are set according to the result.
• Example: CMP R1, R2 ;

2. Unconditional Branch Instruction

• It causes an unconditional change of execution sequence to a new location.
• Example:
JUMP L2
Mov R3, R1 goto L2

3. Conditional Branch Instruction

A conditional branch instruction is used to examine the values stored in the condition code register to determine whether the specific condition exists and to branch if it does.
Example:
Assembly Code : BE R1, R2, L1
Compiler allocates R1 for x and R2 for y
High Level Code: if (x==y) goto L1;
 Program Control
4. Subroutines
• A subroutine is a program fragment that lives in user space, performs a well-defined task. It is invoked by another user program and
returns control to the calling program when finished.
• Example: CALL and RET

5. Halting Instructions
• NOP Instruction - NOP is no operation. It cause no change in the processor state other than an advancement of the program counter. It
can be used to synchronize timing.
• HALT - It brings the processor to an orderly halt, remaining in an idle state until restarted by interrupt, trace, reset or external action.

6. Interrupt Instructions
• Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of processor and get itself serviced.
• RESET - It reset the processor. This may include any or all setting registers to an initial value or setting program counter to standard
starting location.
• TRAP - It is non-maskable edge and level triggered interrupt. TRAP has the highest priority and vectored interrupt.
• INTR - It is level triggered and maskable interrupt. It has the lowest priority. It can be disabled by resetting the processor.
•
Reduced Instruction Set Computer
RISC stands for Reduced Instruction Set Computer and refers to
a design philosophy that uses a small, highly optimized set of
simple, single-cycle instructions to improve performance,
efficiency, and reduce costs

Key Characteristics of RISC in COA

• Reduced Instruction Set: A small, fixed number of basic
instructions.
• Simple Instructions: Each instruction is simple and can be
executed in one clock cycle.
• Register-Based Operations: Data transfer between memory and
registers primarily uses load and store instructions.
• Fixed Instruction Length: A consistent instruction format
simplifies decoding and pipelining.
• Pipelining: The simple, fixed-length instructions are well-suited
for pipelining, allowing multiple instructions to be processed
concurrently.
• Compiler Dependency: The performance of a RISC processor
relies heavily on the compiler to optimize instruction
sequences.
Reduced Instruction Set Computer

Benefits of RISC Architecture

• High Performance: Fast execution times due to simple,
single-cycle instructions.
• Energy Efficiency: Often used in battery-operated devices
because of its high performance per watt.
• Simplified Design: Fewer transistors are needed, leading
to lower per-chip costs and simplified development.
Examples of RISC Processors
• ARM: Widely used in smartphones, tablets, and
embedded systems.
• RISC-V: An open-source instruction set architecture based
on RISC design.
• PowerPC: Used in various computing devices.
Lecture 24
Pipelining
Pipelining
• Pipelining is a technique used in CPUs to increase
instruction throughput (the number of instructions
executed per unit time).
• Works like an assembly line in a factory → different stages
of execution work simultaneously.

Basic Concept
• Instead of executing one instruction at a time (sequential
execution), pipelining overlaps multiple instructions.
• Example analogy:
• Washing → Drying → Folding clothes.
• Sequential: Finish washing all, then drying, then folding.
• Pipeline: Start drying the first batch while washing the
second, folding the first while drying the second, etc.
 Pipelining
A typical 5-stage instruction pipeline:
• Instruction Fetch (IF): Fetch instruction from memory (PC →
MAR → MDR → IR).

• Instruction Decode (ID): Decode opcode, find operands &

addressing mode.

• Operand Fetch (OF): Get required operands from

registers/memory.

• Execution (EX): ALU performs arithmetic/logic operations.

• Write Back (WB): Store result into register/memory.

 Pipelining
Pipeline Performance
Time per instruction (Tp) reduces due to parallelism.
Speedup (S) = Non-pipelined execution time ÷ Pipelined execution time.
Ideally: Speedup ≈ Number of pipeline stages (n)
But practically less due to hazards.

Hazards in Pipelining
Pipelines face problems called hazards:
Structural Hazards
Conflict for hardware resources.
Example: Single memory for instructions and data.

Data Hazards
Instruction depends on the result of a previous instruction.
Example:
I1: ADD R1, R2, R3
I2: SUB R4, R1, R5 ← depends on I1

Control Hazards
Due to branch/jump instructions (program counter update).
Example: Branch prediction needed.
Solutions to Hazards
• Structural Hazard → Use separate instruction & data memories (Harvard Architecture).
• Data Hazard → Use forwarding (data bypassing) or pipeline stalls (NOPs).
• Control Hazard → Use branch prediction & delayed branching.

Advantages of Pipelining
• Increased instruction throughput.
• Better CPU utilization.
• Supports parallelism.

Disadvantages of Pipelining
• Complex hardware design.
• Performance loss due to hazards.
• Difficult handling of interrupts.
Lecture 25
Hardwire and micro programmed control: micro
programme sequencing
Hardwire and micro programmed control
• Hardwired Control Unit: The control hardware can be
viewed as a state machine that changes from one state to
another in every clock cycle, depending on the contents
of the instruction register, the condition codes, and the
external inputs. The outputs of the state machine are the
control signals. The sequence of the operation carried out
by this machine is determined by the wiring of the logic
elements and hence named “hardwired”.

• Fixed logic circuits that correspond directly to the

Boolean expressions are used to generate the control
signals.
• Hardwired control is faster than micro-programmed
control.
• A controller that uses this approach can operate at high
speed.
• RISC architecture is based on the hardwired control unit
 Hardwire and micro programmed control
Micro-programmed Control Unit -
• The control signals associated with operations are stored in special
memory units inaccessible by the programmer as Control Words.
• Control signals are generated by a program that is similar to machine
language programs.
• The micro-programmed control unit is slower in speed because of the
time it takes to fetch microinstructions from the control memory.
Some Important Terms
• Control Word: A control word is a word whose individual bits represent
various control signals.
• Micro-routine: A sequence of control words corresponding to the control
sequence of a machine instruction constitutes the micro-routine for that
instruction.
• Micro-instruction: Individual control words in this micro-routine are
referred to as microinstructions.
• Micro-program: A sequence of micro-instructions is called a micro-
program, which is stored in a ROM or RAM called a Control Memory
(CM).
• Control Store: the micro-routines for all instructions in the instruction set
of a computer are stored in a special memory called the Control Store.
 The differences between hardwired and micro-programmed control units:

Micro-programmed Control Unit

Hardwired Control Unit

Microcode stored in memory

Implementation Fixed set of logic gates and circuits

More flexible, easier to modify

Flexibility Less flexible, difficult to modify

Supports complex instruction sets

Instruction Set Supports limited instruction sets

Complex design, more difficult to implement

Complexity of Design Simple design, easy to implement

Slower operation due to microcode decoding

Speed Fast operation

Easier to debug and test

Debugging and Testing Difficult to debug and test

Larger size, higher cost

Size and Cost Smaller size, lower cost

Maintenance and Upgradability Difficult to upgrade and maintain Easier to upgrade and maintain
Lecture 26 & 27
concept of horizontal and vertical
microprogramming
concept of horizontal and vertical microprogramming
Types of Micro-programmed Control Unit - Based on the type of Control Word stored in the Control
Memory (CM), it is classified into two types :
1. Horizontal Micro-programmed Control Unit :
• The control signals are represented in the decoded binary format that is 1 bit/CS. Example: If 53
Control signals are present in the processor then 53 bits are required. More than 1 control signal
can be enabled at a time.
• It supports longer control words.
• It is used in parallel processing applications.
• It allows a higher degree of parallelism. If degree is n, n CS is enabled at a time.
• It requires no additional hardware(decoders). It means it is faster than Vertical Microprogrammed.
• It is more flexible than vertical microprogrammed
concept of horizontal and vertical microprogramming
2. Vertical Micro-programmed Control Unit :
• The control signals are represented in the encoded binary format. For N control signals- Log2(N)
bits are required.
• It supports shorter control words.
• It supports easy implementation of new control signals therefore it is more flexible.
• It allows a low degree of parallelism i.e., the degree of parallelism is either 0 or 1.
• Requires additional hardware (decoders) to generate control signals, it implies it is slower than
horizontal microprogrammed.
• It is less flexible than horizontal but more flexible than that of a hardwired control unit.
S. No Horizontal µ-Programmed CU Vertical µ-Programmed CU

1. It supports longer control word. It supports shorter control word.

2. It allows a higher degree of parallelism. If degree is n, then It allows a low degree of parallelism i.e., the degree
n Control Signals are enabled at a time. of parallelism is either 0 or 1.

3. Additional hardware in the form of decoders is

No additional hardware is required.
required to generate control signals.

4. it is slower than a Horizontal micro-programmed

It is faster than a Vertical micro-programmed control unit.
control unit.

5. It is more flexible than a vertical micro-programmed It is less flexible than horizontal but more flexible
control unit. than that of a hardwired control unit.

6. A vertical micro-programmed control unit uses

A horizontal micro-programmed control unit uses
vertical micro-instruction, where a code is used for
horizontal micro-instruction, where every bit in the control
each action to be performed and the decoder
field attaches to a control line.
translates this code into individual control signals.

7. The horizontal micro-programmed control unit makes less The vertical micro-programmed control unit makes
use of ROM encoding than the vertical micro-programmed more use of ROM encoding to reduce the length of
control unit. the control word