UNIT -5

RISC CISC

RISC is a reduced instruction set. CISC is a complex instruction set.

The number of instructions is less as The number of instructions is more as

compared to CISC. compared to RISC.

The addressing modes are less. The addressing modes are more.

It works in a fixed instruction format. It works in a variable instruction

format.

The RISC consumes low power. The CISC consumes high power.

The RISC processors are highly pipelined. The CISC processors are less pipelined.

It optimizes the performance by focusing It optimizes the performance by

on software. focusing on hardware.

Requires more RAM. Requires less RAM.

Von Neumann architecture

The Von Neumann architecture, also known as the Princeton architecture, is a
computer design model where both data and instructions are stored in a single,
shared memory space and accessed via a common bus. It uses Complex
Instruction Set Computer (CISC)
Harvard architecture
Harvard architecture is a computer architecture where data and instructions are
stored in separate memory spaces, allowing for simultaneous access and
potentially faster execution, unlike the Von Neumann architecture where they
share the same [Link] uses RISC (Reduced Instruction Set Computer)
ARM Architecture
ARM (Advanced RISC Machine) processors are a family of central
processing units (CPUs) based on a reduced instruction set computer (RISC)
architecture, known for their energy efficiency and performance, widely used in
smartphones, tablets, and other embedded devices.
ARM Processors follow Load and Store type architecture where the
data processing is performed only on the contents of the registers rather than
directly on the memory. The instructions for data processing on registers are
different from that access the memory.
The instruction set of ARM is uniform and fixed in length. 32-bit ARM
Processors have two instruction sets: general 32-bit ARM Instruction Set and
16-bit Thumb Instruction Set.
ARM supports multiple stages of pipeline to speed up the flow of
instructions. In a simple three stage pipeline, the instructions follow three
stages: fetch, decode and execute.
Features of ARM Microprocessors
 RISC-Based Architecture – Simplified instruction set for fast execution.
 Low Power Consumption – Optimized for mobile and embedded
systems.
 High Performance with Pipelining – Multi-stage pipelines for faster
processing.
 Thumb & Thumb-2 Instruction Set – Reduces code size while
maintaining efficiency.
 Multiple Processor Modes – Supports User, Supervisor, and Interrupt
modes.
 Small built-smaller in size
 Lower cost
Block diagram

Address Register & Incrementer

 The address register stores the memory address for fetching instructions
or data.
 The incrementer automatically updates the Program Counter (PC) so
that the next instruction is fetched sequentially.
 The PC (Program Counter) is responsible for tracking the next
instruction’s memory location.
 This ensures smooth instruction execution by handling memory addresses
efficiently.

Register Bank

 The register bank consists of multiple general-purpose registers.

 These registers temporarily store data for fast access by the ALU
(Arithmetic Logic Unit).
  Registers reduce the need for accessing slow memory, improving speed.
 Some special-purpose registers are also included, such as:
o Program Counter (PC) - Stores the address of the next
instruction.
o Status Registers - Store condition flags that indicate the result of
operations (e.g., zero, negative, carry, overflow).

Multiply Register & Barrel Shifter

 The multiply register is a dedicated unit for handling multiplication

operations efficiently.
 The barrel shifter is a specialized unit that can shift or rotate bits in a
single cycle, reducing computation time for arithmetic and logical
operations.

ALU (Arithmetic Logic Unit)

 The ALU is responsible for performing arithmetic operations (addition,

subtraction, multiplication) and logical operations (AND, OR, XOR,
NOT).
 It interacts with different buses:
o A bus & B bus – Used to fetch operands from the register bank.
o ALU bus – Transfers the result of operations back to registers or
memory.
 The ALU is the core computational unit, executing operations defined by
the instruction set.

Instruction Decode & Control Unit

 The Instruction Decode & Control Unit is responsible for:

o Fetching instructions from memory.
o Decoding the instructions to determine what operation needs to be
performed.
o Generating necessary control signals to direct other components.

Data Input/Output Registers

 Data in register: Holds input data that is to be processed.

 Data out register: Stores the processed results before transferring them
to memory or external devices.

Control Unit

 The control unit is a critical component that sends control signals to

various parts of the CPU.
 It coordinates the execution of instructions by:
 o Managing data flow between components.
o Controlling the read/write operations of registers and memory.
o Ensuring synchronization of instruction execution.

Advantages of the ARM Architecture

 RISC (Reduced Instruction Set Computing) Design: Uses a simple and

efficient set of instructions that execute quickly.
 Low Power Consumption: Ideal for battery-powered devices like
smartphones and IoT devices.
 Efficient Data Handling: With registers, barrel shifter, and multiply
register, data manipulation is faster than traditional architectures.
 High Performance: Due to pipeline execution and specialized units,
ARM processors achieve high speed with minimal power usage.

Applications of ARM Processors

 Mobile Devices: Used in smartphones and tablets due to low power

consumption.
 Embedded Systems: Found in microcontrollers, IoT devices, and
industrial applications.
 Gaming Consoles: Used in graphics and computing cores.
 Automotive Systems: Deployed in control units for cars.

ARM Microcontroller Register Modes

An ARM micrcontroller is a load store reducing instruction set computer

architecture means the core cannot directly operate with the memory. The data
operations must be done by the registers and the information is stored in the
memory by an address. The ARM cortex-M3 consists of 37 register sets
wherein 31 are general purpose registers and 6 are status registers. The ARM
uses seven processing modes to run the user task.

In all ARM processors, the following registers are available and accessible in any
processor mode:

 13 general-purpose registers R0-R12.

 One Stack Pointer (SP).

 One Link Register (LR).

 One Program Counter (PC).

 One Application Program Status Register (APSR).

SP ( Stack Pointer )
The stack pointer, often known as the SP register, is located in register [Link]
exception mode has its own version of r13, pointing to a stack specialised to that
mode.
 Temporary values are stored in the stack.
 This was the purpose of SP ARM registers

LR ( The link register )

The Link register, also known as register r14, is used to store the subroutine’s
return address.
 When an exception occurs, the version of r14 in the exception mode is set to the
address after the instruction is executed.
 SPSR is a copy of the CPSR just before an exception has occurred.

PC ( Program Counter )
The Program Counter, sometimes known as the PC, is located in register r15.
 It’s used to determine which instruction will be executed next.
 The PC is referred to as an instruction pointer because it stores the address of
the next instruction.

CPSR ( Current Processor Status Register ) – Important ARM Registers

Current processor status register (CPSR) contains the current status of the processor.
•This includes various conditional code flags, Interrupt Status Processor mode and
other status and control information.
•The exception modes also have a saved processor status register (SPSR), that is used
to preserve the value of CPSR when the associated exception occurs.
•Because the User and System modes are not exception modes, there is no SPSR
available.
SPSR ( Saved Processor Status Register )
In the exception modes there is an additional Saved Processor Status register (SPSR)
which holds information on the processor’s state before the system changed into this
mode i.e. the processor status just before an exception.

 The reserved registers are used for specific functions. The SPSR and
CPSR contain the status control bits which are used to store the
temporary data. The SPSR and CPSR register have some properties that
are defined operating modes, Interrupt enable or disable flags and ALU
status flag. The ARM core operates in two states 32-bit state or
THUMBS state.
  USER Mode
 FIQ Mode
 IRQ Mode
 SVC Mode
 UNDEFINED Mode
 ABORT Mode
 Monitor Mode

USER Mode: The user mode is a normal mode, which has the least number of
registers. It doesn’t have SPSR and has limited access to the CPSR.

FIQ and IRQ: The FIQ and IRQ are the two interrupt caused modes of the
CPU. The FIQ is fast processing interrupt and IRQ is standard interrupt. The
FIQ mode has additional five banked registers to provide more flexibility and
high performance when critical interrupts are handled.

SVC Mode: The Supervisor mode is the software interrupt mode of the
processor to start up or reset.

Undefined Mode: The Undefined mode traps when illegal instructions are
executed. The ARM core consists of 32-bit data bus and faster data flow.

THUMB Mode: In THUMB mode 32-bit data is divided into 16-bits and
increases the processing speed.

THUMB-2 Mode: In THUMB-2 mode the instructions can be either 16-bit or

32-bit and it increases the performance of the ARM cortex –M3
microcontroller. The ARM cortex-m3 microcontroller uses only THUMB-2
instructions.

Pipelining in ARM
Pipelining in ARM processors can be described as a situation in which many
stages of instructions such as the fetch, the decode, the execution, among
others, are enhanced or overlapped in order to improve the performance of the
CPU. Each stage of the pipeline at work on a different instruction at the same
time thereby enhancing throughput.
 A Pipelining is the mechanism used by RISC(Reduced instruction set
computer) processors to execute instructions
 by speeding up the execution by fetching the instruction, while other
instructions are being decoded and executed simultaneously.

Pipelining is a design technique or a process which plays an important

role in increasing the efficiency of data processing in the
processor of a computer and microcontroller. By keeping the processor in a
continuous process of fetching, decoding and executing called (F&E cycle).

 Fetch loads an instruction from memory.

 Decode identifies the instruction to be executed.
 Execute processes the instruction and writes the result back to the
register.
 By over lapping the above stages of execution of different instructions, the
speed of execution is increased.
 The pipelining allows the core to execute an instruction every cycle,
which results in increased throughput.

ARM Pipeline Characteristics

 The ARM pipeline doesn’t process an instruction until it passes
completely through the execution stage.
 In the execution stage, the PC always points to the instruction address
+ 8 bytes.
 When the processor is in thumb state, PC always points to the
instruction address + 4 bytes.
 While executing branch instructions or branching by direct modification of
PC causes the ARM core to flush it’s pipeline.
 As instruction in the execution stage will complete its execution even
though an interrupt has been raised.

ARM-based microcontrollers

ARM-based microcontrollers, categorized by their core architecture, along with

some notable manufacturers and examples:

Cortex-M Series (Microcontroller Focus):

 Cortex-M0/M0+
Smallest footprint, lowest power.
Examples: NXP LPC1100, STMicroelectronics STM32F0 series, TI MSP430
series.
 Cortex-M3:
Good balance of performance and power efficiency.
Examples: NXP LPC1700, STMicroelectronics STM32F1 series, Cypress
CY8C29400.
 Cortex-M4:
Higher performance for demanding applications, often used in industrial and
automotive.
Examples: NXP LPC4000, STMicroelectronics STM32F4 series, TI TMS570
series.
 Cortex-M7:
Highest performance within the Cortex-M family.
Examples: STMicroelectronics STM32H7 series, NXP S32K series.
 Cortex-M33:
Focus on security and real-time performance.
Examples: NXP LPC5500, STMicroelectronics STM32L5 series.

ARM processors are designed to work in a variety of environments, including:

1. Mobile Devices: They are widely used in smartphones and tablets due to their
power efficiency and performance.
2. Embedded Systems: Common in IoT devices, automotive applications, and home
automation products.
3. Consumer Electronics: Found in smart TVs, gaming consoles, and set-top boxes.
4. Networking Equipment: Used in routers and switches for efficient data
processing.
5. Industrial Applications: Employed in machinery and automation systems for
control and monitoring.
6. Computing: Increasingly used in laptops and servers, particularly for energy-
efficient computing solutions.
Their versatility and low power consumption make ARM processors suitable for
many environments across various industries.