THC63LVD824 _Rev2.

THC63LVD824
Single(135MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA

General Description Features

The THC63LVD824 receiver is designed to support • Wide dot clock range: 25-170MHz suited for VGA,
Single Link transmission between Host and Flat Panel SVGA, XGA, SXGA, SXGA+ and UXGA
Display up to SXGA+ resolutions and Dual Link trans-
• PLL requires No external components
mission between Host and Flat Panel Display up to
UXGA resolutions. The THC63LVD824 converts the • Supports Single Link up to 135MHz dot clock for
LVDS data streams back into 48bits of CMOS/TTL data SXGA+
with falling edge or rising edge clock for convenient • Supports Dual Link up to 170MHz dot clock for
with a variety of LCD panel controllers. UXGA
In Single Link, data transmit clock frequency of • 50% output clock duty cycle
135MHz, 48bits of RGB data are transmitted at an
• TTL clock edge programmable
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 472Mbytes per • TTL output driverbility selectable for lower EMI
second. • Power down mode
In Dual Link, data transmit clock frequency of 85MHz, • Low power single 3.3V CMOS design
48bits of RGB data are transmitted at an effective rate
• 100pin TQFP
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second. • THC63LVDF84B compatible

Block Diagram
LVDS INPUT CMOS/TTL OUTPUT
RA1 +/-
SERIAL TO PARALLEL

8 RED1
8
RB1 +/- GREEN1 1st DATA
28 8
BLUE1
1st Link RC1 +/-

RD1 +/- HSYNC

VSYNC
RCLK1 +/-
(25 to 135MHz) PLL DE
DEMUX

RECEIVER CLOCK OUT

RA2 +/-
SERIAL TO PARALLEL

(25 to 85MHz)

RB2 +/- 8
RED2
28 8
GREEN2 2nd DATA
2nd Link RC2 +/-
8
BLUE2
RD2 +/-

RCLK2 +/-
(25 to 85MHz) PLL

R/F
/PDWN

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 1 THine Electronics, Inc.
THC63LVD824 _Rev2.0

Pin Out

VSYNC
HSYNC

GND

GND
VCC

VCC
G17
G16
G15
G14
G13

G12

G10
G11
B17
B16

B15
B14
B13
B12

B10

R17
R16
B11
DE
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LVDS GND 76 50 R15
RA1- 77 49 GND
RA1+ 78 48 VCC
RB1- 79 47 R14
RB1+ 80 46 R13
LVDS VCC 81 45 R12
RC1- 82 44 R11
RC1+ 83 43 R10
RCLK1- 84 42 GND
RCLK1+ 85 41 VCC
RD1- 86 40 CLKOUT
RD1+ 87 39 B27
LVDS GND 88 38 B26
RA2- 89 37 B25
RA2+ 90 36 B24
RB2- 91 35 B23
RB2+ 92 34 GND
LVDS VCC 93 33 VCC
RC2- 94 32 B22
RC2+ 95 31 B21
RCLK2- 96 30 B20
RCLK2+ 97 29 G27
RD2- 98 28 GND
RD2+ 99 27 VCC
LVDS GND 100 26 G26
10

12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
1
2
3
4
5
6
7
8
9DRVSEL
PLL VCC

VCC
PLL GND

MODE0
MODE1
GND
/PDWN

GND

R20
R21
R22
R23
R24

GND
R25
R26
R27
G20
G21
G22
G23
G24
G25
R/F

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 2 THine Electronics, Inc.
THC63LVD824 _Rev2.0

Pin Description
Pin Name Pin # Type Description
RA1+, RA1- 78, 77 LVDS IN
RB1+, RB1- 80, 79 LVDS IN
The 1st Link. The 1st pixel input data when Dual Link.
RC1+, RC1- 83, 82 LVDS IN
RD1+, RD1- 87, 86 LVDS IN
RCLK1+, RCLK1- 85, 84 LVDS IN LVDS Clock Input for 1st Link.
RA2+, RA2- 90, 89 LVDS IN
RB2+, RB2- 92, 91 LVDS IN
The 2nd Link. These pins are disabled when Single Link.
RC2+, RC2- 95, 94 LVDS IN
RD2+, RD2- 99, 98 LVDS IN
RCLK2+, RCLK2- 97, 96 LVDS IN LVDS Clock Input for 2nd Link.
52, 51, 50, 47,
R17 ~ R10 OUT
46, 45, 44, 43
62, 61, 60, 59,
G17 ~ G10 OUT The 1st Pixel Data Outputs.
58, 55, 54, 53
72, 71, 68, 67,
B17 ~ B10 OUT
66, 65, 64, 63
19, 18, 17, 14,
R27 ~ R20 OUT
13, 12, 11, 10
29, 26, 25, 24,
G27 ~ G20 OUT The 2nd Pixel Data Outputs.
23, 22, 21, 20
39, 38, 37, 36,
B27 ~ B20 OUT
35, 32, 31, 30
DE 75 OUT Data Enable Output.
VSYNC 74 OUT Vsync Output.
HSYNC 73 OUT Hsync Output.
CLKOUT 40 OUT Clock Output.
Output Driverbility Select.
DRVSEL 9 IN
H: High power, L: Low power.
Output Clock Triggering Edge Select.
R/F 8 IN
H: Rising edge, L: Falling edge.
Pixel Data Mode.
MODE1 MODE0 Mode
MODE1, MODE0 6, 5 IN L L Dual Link
L H Single Link

H: Normal operation,
/PDWN 4 IN
L: Power down (all outputs are pulled to ground)
15, 27, 33, 41,
VCC Power Power Supply Pins for TTL outputs and digital circuitry.
48, 56, 69
3, 7, 16, 28, 34,
GND Ground Ground Pins for TTL outputs and digital circuitry.
42, 49, 57, 70
LVDS VCC 81,93 Power Power Supply Pins for LVDS inputs.
LVDS GND 76, 88, 100 Ground Ground Pins for LVDS inputs.

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 3 THine Electronics, Inc.
THC63LVD824 _Rev2.0

Pin Name Pin # Type Description

PLL VCC 2 Power Power Supply Pin for PLL circuitry.
PLL GND 1 Ground Ground Pin for PLL circuitry.

Absolute Maximum Ratings 1

Supply Voltage (VCC) -0.3V ~ +4.0V
CMOS/TTL Input Voltage -0.3V ~ (VCC + 0.3V)
CMOS/TTL Output Voltage -0.3V ~ (VCC + 0.3V)
LVDS Receiver Input Voltage -0.3V ~ (VCC + 0.3V)
Output Current -30mA ~ 30mA
Junction Temperature +125 °C
Storage Temperature Range -55 °C ~ +125 °C
Lead Temperature (Soldering, 10sec) +230 °C
Maximum Power Dissipation @+25 °C 1.0W

Electrical Characteristics

CMOS/TTL DC Specifications
VCC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70 °C
Symbol Parameter Conditions Min. Typ. Max. Units
VIH High Level Input Voltage 2.0 VCC V
VIL Low Level Input Voltage GND 0.8 V
IOH= -2mA, -4mA (data)
VOH High Level Output Voltage 2.4 V
IOH= -4mA, -8mA (clock)
IOL= 2mA, 4mA (data)
VOL Low Level Output Voltage 0.4 V
IOL= 4mA, 8mA (clock)
IINC Input Current 0V ≤ VIN ≤ V CC ± 10 µA

LVDS Receiver DC Specifications

VCC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70 °C
Symbol Parameter Conditions Min. Typ. Max. Units
VTH Differential Input High Threshold VOC= 1.2V 100 mV
VTL Differential Input Low Threshold VOC= 1.2V -100 mV
VIN= 2.4V / 0V
IINL Input Current ± 20 µA
VCC= 3.6V

1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They
are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics”
specify conditions for device operation.

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 4 THine Electronics, Inc.
THC63LVD824 _Rev2.0

Supply Current
VCC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70 °C
Symbol Parameter Condition(*) Typ. Max. Units
MODE<1:0>=LH
VESA SXGA (60Hz),
CL=8pF, 57 66 mA
Receiver Supply fCLKOUT = 54MHz
Vcc=3.3V
IRCCG Current
MODE<1:0>=LL
(256 Gray Scale Pattern) VESA UXGA (60Hz),
CL=8pF, 85 97 mA
fCLKOUT = 81MHz
Vcc=3.3V
MODE<1:0>=LH
VESA SXGA (60Hz),
CL=8pF, 87 99 mA
Receiver Supply fCLKOUT = 54MHz
Vcc=3.3V
IRCCW Current
MODE<1:0>=LL
(Double Checker Pattern) VESA UXGA (60Hz),
CL=8pF, 148 173 mA
fCLKOUT = 81MHz
Vcc=3.3V
Receiver Power Down
IRCCS /PDWN = L 10 µA
Supply Current
(*) VESA is a trademark of the Video Electronics Standards Association.

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 5 THine Electronics, Inc.
THC63LVD824 _Rev2.0

256 Gray Scale Pattern

CLKOUT

Rx0/Gx0/Bx0

Rx1/Gx1/Bx1

Rx2/Gx2/Bx2

Rx3/Gx3/Bx3

Rx4/Gx4/Bx4

Rx5/Gx5/Bx5

Rx6/Gx6/Bx6

Rx7/Gx7/Bx7
x=1,2

DE

Double Checker Pattern

CLKOUT

R1n/G1n/B1n

R2n/G2n/B2n
n=0~7
DE

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 6 THine Electronics, Inc.
THC63LVD824 _Rev2.0

Switching Characteristics
VCC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70 °C
Symbol Parameter Min. Typ. Max. Units
Dual-in / Dual-out 11.76 tRCIP 40.0 ns
tRCP CLKOUT Period
Single-in / Dual-out 14.8 2tRCIP 80.0 ns
t RCP
tRCH CLKOUT High Time ----------
- ns
2

t RCP
tRCL CKLOUT Low Time ----------- ns
2
tRS TTL Data Setup to CLKOUT 0.3tRCP ns
tRH TTL Data Hold from CKLOUT 0.3tRCP ns
tTLH TTL Low to High Transition Time 3.0 5.0 ns
tTHL TTL High to Low Transition Time 3.0 5.0 ns
tRIP1 Input Data Position0 (tRCIP = 7.4ns) -0.25 0.0 +0.25 ns
t RCIP tRCIP t RCIP
tRIP0 Input Data Position1 (tRCIP = 7.4ns) ------------
- – 0.25 ------------- ------------
- + 0.25 ns
7 7 7

t RCIP tRCIP t RCIP

tRIP6 Input Data Position2 (tRCIP = 7.4ns) 2 ------------
- – 0.25 2 ------------
- 2 ------------
- + 0.25 ns
7 7 7

t RCIP tRCIP t RCIP

tRIP5 Input Data Position3 (tRCIP = 7.4ns) 3 ------------
- – 0.25 3 ------------
- 3 ------------
- + 0.25 ns
7 7 7

t RCIP tRCIP t RCIP

tRIP4 Input Data Position4 (tRCIP = 7.4ns) 4 ------------
- – 0.25 4 ------------
- 4 ------------
- + 0.25 ns
7 7 7

t RCIP tRCIP t RCIP

tRIP3 Input Data Position5 (tRCIP = 7.4ns) 5 ------------
- – 0.25 5 ------------
- 5 ------------
- + 0.25 ns
7 7 7

t RCIP tRCIP t RCIP

tRIP2 Input Data Position6 (tRCIP = 7.4ns) 6 ------------
- – 0.25 6 ------------
- 6 ------------
- + 0.25 ns
7 7 7
tRPLL Phase Lock Loop Set 10.0 ms
tRCIP CLKIN Period 7.4 40.0 ns
Skew Time between RCLK1 and
tCK12 ± 0.3t RCIP ns
RCLK2

AC Timing Diagrams
TTL Outputs

TTL Output 80% 80%

8pF

20% 20%

TTL Output Load

tTLH tTHL

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 7 THine Electronics, Inc.
THC63LVD824 _Rev2.0

AC Timing Diagrams
TTL Outputs

tRCH tRCL

R/F = L
2.0V 2.0V 2.0V
CLKOUT
0.8V 0.8V
R/F = H

tRCP tRH
tRS

Rxn 2.0V 2.0V

Gxn
0.8V 0.8V
Bxn
x = 1,2
n = 0~7

Phase Lock Loop Set Time

3.0V
VCC

RCLKx+/-

2.0V
/PDWN

tRPLL

2.0V
CLKOUT

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 8 THine Electronics, Inc.
THC63LVD824 _Rev2.0

Pixel Map Table for Single/Dual Link

1st Pixel Data 2nd Pixel Data

TFT Panel Data TFT Panel Data
824 TTL Output Pin 824 TTL Output Pin
24Bit 18Bit 24Bit 18Bit
R10 LSB R10 - R20 LSB R20 -
R11 R11 - R21 R21 -
R12 R12 R10 R22 R22 R20
R13 R13 R11 R23 R23 R21
R14 R14 R12 R24 R24 R22
R15 R15 R13 R25 R25 R23
R16 R16 R14 R26 R26 R24
R17 MSB R17 R15 R27 MSB R27 R25
G10 LSB G10 - G20 LSB G20 -
G11 G11 - G21 G21 -
G12 G12 G10 G22 G22 G20
G13 G13 G11 G23 G23 G21
G14 G14 G12 G24 G24 G22
G15 G15 G13 G25 G25 G23
G16 G16 G14 G26 G26 G24
G17 MSB G17 G15 G27 MSB G27 G25
B10 LSB B10 - B20 LSB B20 -
B11 B11 - B21 B21 -
B12 B12 B10 B22 B22 B20
B13 B13 B11 B23 B23 B21
B14 B14 B12 B24 B24 B22
B15 B15 B13 B25 B25 B23
B16 B16 B14 B26 B26 B24
B17 MSB B17 B15 B27 MSB B27 B25

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 9 THine Electronics, Inc.
THC63LVD824 _Rev2.0

824 TTL Data Output Timing for Single/Dual Link

Example : SXGA+(1400 x 1050)

HSYNC

DE

CLKOUT

R1x/G1x/B1x #1 #3 #5 #7 1395 #1397 #1399

R2x/G2x/B2x #2 #4 #6 #8 1396 #1398 #1400

n = 0~7

#1 #2 #1399 #1400

TFT Panel
(1400 x 1050)

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 10 THine Electronics, Inc.
THC63LVD824 _Rev2.0

AC Timing Diagrams
LVDS Inputs
tRIP2

tRIP3

tRIP4

tRIP5

tRIP6

tRIP0

tRIP1

Ryx+/- Ryx6 Ryx5 Ryx4 Ryx3 Ryx2 Ryx1 Ryx0 Ryx6 Ryx5 Ryx4 Ryx3 Ryx2 Ryx1

RCLKx+ Vdiff = 0V Vdiff = 0V

x = 1,2 tRCIP
y = A,B,C,D

RCLK1+ Vdiff = 0V

tCK12

RCLK2+ Vdiff = 0V

Note:
Vdiff = (Ryx+) - (Ryx-), (RCLKx+) - (RCLKx-)

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 11 THine Electronics, Inc.
THC63LVD824 _Rev2.0

LVDS Data Inputs Timing Diagrams in Single Link

Previous Cycle Current Cycle

(2nd pixel data) (1st pixel data)

RCLK1+

RA1+/- R26’ R25’ R24’ R23’ R22’ G12 R17 R16 R15 R14 R13 R12 G22’’

RB1+/- G27’ G26’ G25’ G24’ G23’ B13 B12 G17 G16 G15 G14 G13 B23’’

RC1+/- HSYNC’ B27’ B26’ B25’ B24’ DE VSYNC HSYNC B17 B16 B15 B14 DE’’

RD1+/- B20’ G21’ G20’ R21’ R20’ x B11 B10 G11 G10 R11 R10 x’’

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 12 THine Electronics, Inc.
THC63LVD824 _Rev2.0

LVDS Data Inputs Timing Diagrams in Dual Link

Previous Cycle Current Cycle

RCLK1+

RA1+/- R16’ R15’ R14’ R13’ R12’ G12 R17 R16 R15 R14 R13 R12 G12’’

RB1+/- G17’ G16’ G15’ G14’ G13’ B13 B12 G17 G16 G15 G14 G13 B13’’

RC1+/- HSYNC’ B17’ B16’ B15’ B14’ DE VSYNC HSYNC B17 B16 B15 B14 DE’’

RD1+/- B10’ G11’ G10’ R11’ R10’ x B11 B10 G11 G10 R11 R10 x’’

RCLK2+

RA2+/- R26’ R25’ R24’ R23’ R22’ G22 R27 R26 R25 R24 R23 R22 G22’’

RB2+/- G27’ G26’ G25’ G24’ G23’ B23 B22 G27 G26 G25 G24 G23 B23’’

RC2+/- x’ B27’ B26’ B25’ B24’ x x x B27 B26 B25 B24 x’’

RD2+/- B20’ G21’ G20’ R21’ R20’ x B21 B20 G21 G20 R21 R20 x’’

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 13 THine Electronics, Inc.
THC63LVD824 _Rev2.0

Package

INDEX ∆ 100 76
PIN No.1

75

0.5TYP

14.0SQ TYP

16.0SQ TYP
0.22

25 51

26 50
1.00 TYP

1.2MAX

UNITS:mm

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 14 THine Electronics, Inc.
THC63LVD824 _Rev2.0

Notes to Users:
1. The contents of this data sheet are subject to change without prior notice.
2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay sufficient attention
when designing circuits. Even if there are incorrect descriptions, we are not responsible for any problem due to
them. Please note that incorrect descriptions sometimes cannot be corrected immediately if found.
3. Our copyright and know-how are included in this data sheet. Duplication of the data sheet and disclosure to other
persons are strictly prohibited without our permission.
4. We are not responsible for any problems of industrial proprietorship occurring during THC63LVD824 use, except
for those directly related to THC63LVD824’s structure, manufacture or functions. THC63LVD824 is designed on
the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that
require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects peo-
ple’s lives, etc.). In addition, when using THC63LVD824 for traffic signals, safety devices and control/safety units
in transportation equipment, etc., appropriate measures should be taken.
5. We are making the utmost effort to improve the quality and reliability of our products. However, there is a very
slight possibility of failure in semiconductor devices. To avoid damage to social or official organizations, much care
should be taken to provide sufficient redundancy and fail-safe design.
6. No radiation-hardened design is incorporated in THC63LVD824.
7. Judgment on whether THC63LVD824 comes under strategic products prescribed by the Foreign Exchange and For-
eign Trade Control Law is the user’s responsibility.
8. This technical document was provisionally created during development of THC63LVD824, so there is a possibility
of differences between it and the product’s final specifications. When designing circuits using THC63LVD824, be
sure to refer to the final technical documents.

THine Electronics, Inc.

Wakamatsu Bldg, 6F
3-3-6, Nihombashi-Honcho,
Chuo-ku, Tokyo, 103-0023 Japan
Tel: 81-3-3270-0666
Fax: 81-3-3270-0688

Copyright 2000-2003 THine Electronics, Inc. All rights reserved 15 THine Electronics, Inc.