HIGH-VOLTAGE MIXED-SIGNAL IC

65x192 STN Controller-Driver

MP Specifications August 3, 2012

ULTRACHIP
The Coolest LCD Driver, Ever!
ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

Table of Content

INTRODUCTION .......................................................................................... 3
MAIN APPLICATIONS .................................................................................. 3
FEATURE HIGHLIGHTS ............................................................................... 3
ORDERING INFORMATION ........................................................................... 4
BLOCK DIAGRAM ....................................................................................... 5
PIN DESCRIPTION ...................................................................................... 6
RECOMMENDED COG LAYOUT ................................................................... 8
CONTROL REGISTERS ................................................................................ 9
COMMAND TABLE .................................................................................... 11
COMMAND DESCRIPTION.......................................................................... 12
LCD VOLTAGE SETTING .......................................................................... 20
VLCD QUICK REFERENCE .......................................................................... 21
LCD DISPLAY CONTROLS ........................................................................ 23
ITO LAYOUT AND LC SELECTION ............................................................. 24
HOST INTERFACE .................................................................................... 26
DISPLAY DATA RAM (DDRAM) ............................................................... 34
RESET & POWER MANAGEMENT .............................................................. 36
MULTI-TIME PROGRAM (MTP) NV MEMORY .............................................. 41
MTP OPERATION FOR LCM MAKERS ....................................................... 44
ESD CONSIDERATION .............................................................................. 48
ABSOLUTE MAXIMUM RATINGS ................................................................ 49
SPECIFICATIONS ...................................................................................... 50
AC CHARACTERISTICS ............................................................................ 51
PHYSICAL DIMENSIONS ............................................................................ 57
ALIGNMENT MARK INFORMATION ............................................................. 58
PAD COORDINATES ................................................................................. 59
TRAY INFORMATION ................................................................................. 63
REVISION HISTORY .................................................................................. 64

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

UC1609
Single-Chip, Ultra-Low Power
65COM by 192SEG
Passive Matrix LCD Controller-Driver

• Support industry standard 8-bit parallel bus (8080 or

INTRODUCTION 6800 mode), 4-wire and 3-wire serial buses (S8 and S9),
2
and 2-wire I C serial interface.
UC1609c is an advanced high-voltage mixed-signal CMOS IC,
especially designed for the display needs of ultra-low power • Ultra-low power consumption under all display patterns.
hand-held devices. • Fully programmable Mux Rate, partial display, Bias
This chip employs UltraChip’s unique DCC (Direct Capacitor Ratio and Frame Rate allow many flexible power
Coupling) driver architecture to achieve near crosstalk free management options.
images. • Software programmable frame rates at 76, 95, 132 and
In addition to low power column and row drivers, the IC 168 Hz.
contains all necessary circuits for high-V LCD power supply, • Four software programmable temperature
bias voltage generation, timing generation and graphics data compensation coefficients.
memory.
• 7-x internal charge pump with on-chip pumping
Advanced circuit design techniques are employed to minimize
capacitor requires only 3 external capacitors to operate.
external component counts and reduce connector size while
achieving extremely low power consumption. • On-chip Power-ON Reset makes RST pin optional.
• Very low pin count (10-pin) allows exceptional image
MAIN APPLICATIONS quality in COG format on conventional ITO glass.

• Cellular Phones, Smart Phones, PDA, and other battery • Flexible data addressing/mapping schemes to support
operated palm top devices or portable Instruments wide ranges of software models and LCD layout
placements.
• VDD (digital) range (Typ.): 1.8V ~ 3.3V
FEATURE HIGHLIGHTS VDD (analog) range (Typ.): 2.7V ~ 3.3V
VLCD range: 4.8V ~ 11.5V
• Single chip controller-driver supports 65x192 graphics
STN LCD panels. • Available in gold bump dies
• Support both row ordered and column ordered display • COM/SEG bump information
buffer RAM access. Bump pitch: 27.6 µM
Bump gap: 12 µM
• A software-readable ID pin to support configurable 2
vender identification. Bump surface: 1560 µM

• Support both row-ordered and column-ordered display

buffer RAM access.

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

ORDERING INFORMATION
2
Part Number MTP IC Description
UC1609cGAA Yes Yes Gold Bumped Die

General Notes
APPLICATION INFORMATION
For improved readability, the specification contains many application data points. When application information is given, it is advisory and does
not form part of the specification for the device.

USE OF I2C
2
The implementation of I C is already included and tested in all silicon.

BARE DIE DISCLAIMER

All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing. There is no post waffle saw/pack testing
performed on individual die. Although the latest modern processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers,
UltraChip has no control of third party procedures in the handling, packing or assembly of the die. Accordingly, it is the responsibility of the
customer to test and qualify their application in which the die is to be used. UltraChip assumes no liability for device functionality or performance
of the die or systems after handling, packing or assembly of the die.

LIFE SUPPORT APPLICATIONS

These devices are not designed for use in life support appliances, or systems where malfunction of these products can reasonably be expected to
result in personal injuries. Customer using or selling these products for use in such applications do so at their own risk.

CONTENT DISCLAIMER
UltraChip believes the information contained in this document to be accurate and reliable. However, it is subject to change without notice. No
responsibility is assumed by UltraChip for its use, nor for infringement of patents or other rights of third parties. No part of this publication may be
reproduced, or transmitted in any form or by any means without the prior consent of UltraChip Inc. UltraChip’s terms and conditions of sale apply
at all times.

CONTACT DETAILS
UltraChip Inc. (Headquarter) Tel: +886 (2) 8797-8947
4F, No. 618, Recom Road, Fax: +886 (2) 8797-8910
Neihu District, Taipei 114, Sales e-mail: sales@[Link]
Taiwan, R. O. C. Web site: [Link]

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

BLOCK DIAGRAM

COLUMN ADDRESS
GENERATOR

PAGE ADDRESS GENERATOR

POWER ON &

ROW ADDRESS GENERATOR

RESET

DATA RAM I/O BUFFER

CONTROL

LEVEL SHIFTER

COM DRIVERS
CLOCK & DISPLAY DATA RAM
TIMING
GENERATOR

CONTROL &
STATUS
REGISTER

DISPLAY DATA LATCHES

COMMAND LEVEL SHIFTERS VLCD & BIAS CL

GENERATOR
HOST INTERFACE SEG DRIVERS

CB0 CB1

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

PIN DESCRIPTION
Pin Name
Type Pins Description
(Pad Name)
MAIN POWER SUPPLY
VDD supplies for Display Data RAM and digital logic, VDD2 supplies for VLCD and VD
generator, VDD3 supplies for VBIAS and other analog circuits.
VDD 6 VDD2/VDD3 should be connected to the same power source. But VDD can be connected to
VDD2 PWR 5 a source voltage no higher than VDD2/VDD3.
VDD3 5 Please maintain the following relationship:
VDD+1.3V ≥ VDD2/3 ≥ VDD
ITO trace resistance needs to be minimized for VDD2/VDD3.
VSS 6 Ground. Connect VSS and VSS2 to the shared GND pin. In COG applications, minimize
GND
VSS2 6 the ITO resistance for both VSS and VSS2.
LCD POWER SUPPLY & VOLTAGE CONTROL
VB0+ 4
(VBP_pad<0>)
LCD Bias Voltages. These are the voltage sources to provide SEG driving currents.
VB0– 4 These voltages are generated internally. Connect capacitors of CBX value between VBX+
(VBN_pad<0>) and VBX–. See the “LCD Voltage Setting” section for more details.
PWR
VB1+ 4 In COG application, the resistance of these ITO traces directly affects the SEG driving
(VBP_pad<1>) strength of the resulting LCD module. Minimize these trace resistance is critical in
achieving high quality image.
VB1– 4
(VBN_pad<1>)
VLCDIN Main LCD Power Supply. When internal VLCD is used, connect these pins together. When
external VLCD source is used, connect external VLCD source to VLCDIN pins and leave
(VLCDIN_pad) 4
PWR VLCDOUT open.
VLCDOUT 4
Capacitor CL should be connected between VLCD and VSS. In COG applications, keep the
(VLCDOUT_pad) ITO trace resistance around 70 Ω .
• Recommended capacitor values:
CB: 2.2µF/5V or 300x(LCD load capacitance), whichever is higher.
CL: 330nF/25V is appropriate for most applications.

HOST INTERFACE
Bus mode: The interface bus mode is determined by BM[1:0] and
D[7] by the following relationship:
BM[1:0] D[7] Mode Remark
BM0 1
BM1 1 11 Data 6800/8-bit
I
(BM_pad<0> 10 Data 8080/8-bit
~ <1>) 00 -- 4-wire SPI w/ 8-bit token (S8: conventional)
01 0 3-wire SPI w/ 9-bit token (S9: conventional)
2
01 1 2-wire serial (I C)
CS1/A3 1 Chip Select. Chip is selected when CS1=”H” and CS0 = “L”. When the chip is not
CS0/A2 I 1 selected, D[7:0] will be of high impedance.
2
(CS_pad<0>~<1>) In I C mode, these two pins specifies bits 3~2 of UC1609c’ device address (A[3:2]).
When RST=”L”, all control registers are re-initialized by their default states. Since
UC1609c has built-in Power-On Reset, the RST pin is not required for proper chip
RST
I 1 operation.
(RSTB_pad)
An RC Filter has been included on-chip. There is no need for external RC noise filter.
When RST is not used, connect the pin to VDD.

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

Pin Name
Type Pins Description
(Pad Name)
Select Control data or Display data for read/write operation. In S9, CD pin is not used.
CD
I 1 Connect CD to VSS when not used.
(CD_pad)
”L”: Control data ”H”: Display data
ID ID may be used for production identification.
I 1
(ID_pad) Connect ID to VDD for “H” or VSS for “L”.
WR [1:0] controls the read/write operation of the host interface. See Host Interface section
WR0
1 for details.
WR1 I
1 In parallel mode, the meaning of WR[1:0] depends on which interface it is in, 6800 or
(WR_pad<0>~<1>)
8080 mode. In serial interface modes, these two pins are not used, Connect them to VSS.
Bi-directional bus for both serial and parallel host interfaces.
In serial modes, connect D[0] to SCK, D[5:3] to SDA.
D7 D6 D5 D4 D3 D2 D1 D0
D7~D0 8-bit (BM=1x) D7 D6 D5 D4 D3 D2 D1 D0
(DATA_pad<7> I/O 8 s8 (BM=00) -- -- SDA SDA SDA -- -- SCK
~ <0>) S9 (BM=01) 0 -- SDA SDA SDA -- -- SCK
2
I C (BM=01) 1 -- SDA SDA SDA -- -- SCK
For better drive ability, connect D[5:3] together.
Always connect unused pins to either VSS or VDD.
HIGH VOLTAGE LCD DRIVER OUTPUT
SEG1~192
SEG (column) driver outputs. Support up to 192 pixels.
(SEG_pad<1> HV 192
Leave unused SEG drivers open-circuit.
~ <192>)
COM1~64 COM (row) driver outputs. Support up to 64 rows.
(COM_pad<1> HV 64 When designing LCM, always start from COM1. If the LCM has N pixel rows and N is
~ <64>) less than 64, set CEN to be N-1, and leave COM drivers [N+1 ~ 64] open-circuit.
CIC
HV 2 Icon driver outputs. Leave it open if not used.
(COMS_pad)
MISC. PINS
Auxiliary VDD. This pin is connected to the main VDD bus within the IC. It’s provided to
facilitate chip configurations in COG application.
VDDX 5
There’s no need to connect VDDX to main VDD externally and it should NOT be used to
provide VDD power to the chip.
TST4 TST4 is used as one of the high voltage power supply for MTP programming operation.
I 4
(TST4_pad) For COG designs, please wire out TST4 with trace resistance between 30~50 Ω.
TST2
I/O 2 Test I/O pins. Leave these pins open during normal use.
(TST2_pad)
Power-ON Reset control.
POR Connect the POR pin to VDD for “H”; to Vss for “L” to control the POR register.
1
(POR_dis_pad) “L”: Power-ON Reset Enable.
“H”: Power-ON Reset Disabled.
Dummy
22 Dummy pins are NOT connected inside the IC.
(Dummy1~22)
Note: Several control registers will specify “0 based index” for COM and SEG electrodes. In those situations, COMx or SEGx
will correspond to index x-1, and the value range for those index register will be 0~63 for COM and 0~191 for SEG.

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

RECOMMENDED COG LAYOUT

D7
D6
DUMMY2 DUMMY1
COM_pad<63>
D5 DUMMY5
COM_pad<61>
COM_pad<59>
COM_pad<57>
DUMMY6 COM_pad<55>

D4 COM_pad<53>
COM_pad<51>
COM_pad<49>
COM_pad<47>
COM_pad<45>
D3 COM_pad<43>
COM_pad<41>
COM_pad<39>
DATA_pad<7> COM_pad<37>
COM_pad<35>
D2 VDDX
COM_pad<33>
COM_pad<31>
COM_pad<29>
DATA_pad<6> COM__pad<27>
COM_pad<25>
D1 DATA_pad<5> COM_pad<23>

UC1609c Bump View

COM_pad<21>
COM_pad<19>
DATA_pad<4> COM_pad<17>

D0 DATA_pad<3>
COM_pad<15>
COM_pad<13>
COM_pad<11>
COM_pad<9>
COM_pad<7>
RST DATA_pad<2> COM_pad<5>
COM_pad<3>
COM_pad<1>
DATA_pad<1>
COMS_PAD

WR0 DATA_pad<0>

RSTB_pad SEG_pad<192>

WR1 WR_pad<0>
SEG_pad<191>
SEG_pad<190>
SEG_pad<189>
SEG_pad<188>
VDDX SEG_pad<187>

CD WR_pad<1>
SEG_pad<186>
SEG_pad<185>
SEG_pad<184>
SEG_pad<183>
CD_pad SEG_pad<182>
CS0 CS_pad<0>
SEG_pad<181>
SEG_pad<180>
SEG_pad<179>
VDDX SEG_pad<178>
SEG_pad<177>
BM0 CS_pad<1>
SEG_pad<176>
SEG_pad<175>
SEG_pad<174>
BM_pad<0> SEG_pad<173>

BM1 VDDX
SEG_pad<172>
SEG_pad<171>
SEG_pad<170>
SEG_pad<169>
BM_pad<1> SEG_pad<168>
ID ID_pad
SEG_pad<167>
SEG_pad<166>
SEG_pad<165>
SEG_pad<164>
VDDX SEG_pad<163>
POR POR_dis_pad
SEG_pad<162>
SEG_pad<161>
SEG_pad<160>
SEG_pad<159>
VSS SEG_pad<158>
SEG_pad<157>
VSS SEG_pad<156>
SEG_pad<155>
VSS SEG_pad<154>
SEG_pad<153>
SEG_pad<152>
VSS SEG_pad<151>
SEG_pad<150>
VSS SEG_pad<149>
SEG_pad<148>
VSS SEG_pad<147>
SEG_pad<146>
SEG_pad<145>
SEG_pad<144>
DUMMY7 SEG_pad<143>
SEG_pad<142>
DUMMY8 SEG_pad<141>
SEG_pad<140>
DUMMY9 SEG_pad<139>
SEG_pad<138>
SEG_pad<137>
SEG_pad<136>
VSS2 SEG_pad<135>
VSS VSS2
SEG_pad<134>
SEG_pad<133>
SEG_pad<132>
SEG_pad<131>
VSS2 SEG_pad<130>
SEG_pad<129>
VSS2 SEG_pad<128>
SEG_pad<127>
VSS2 SEG_pad<126>
SEG_pad<125>
SEG_pad<124>
VSS2 SEG_pad<123>
SEG_pad<122>
SEG_pad<121>
DUMMY10 SEG_pad<120>
SEG_pad<119>
DUMMY11 SEG_pad<118>
SEG_pad<117>
SEG_pad<116>
DUMMY12 SEG_pad<115>
SEG_pad<114>
DUMMY13 SEG_pad<113>
SEG_pad<112>
SEG_pad<111>
DUMMY14 SEG_pad<110>
SEG_pad<109>
VDD SEG_pad<108>
SEG_pad<107>
SEG_pad<106>
VDD SEG_pad<105>
SEG_pad<104>
VDD SEG_pad<103>
SEG_pad<102>
VDD SEG_pad<101>
SEG_pad<100>
SEG_pad<99>
VDD SEG_pad<98>
SEG_pad<97>
SEG_pad<96>
VDD SEG_pad<95>
SEG_pad<94>
SEG_pad<93>
VDD2 SEG_pad<92>
SEG_pad<91>
SEG_pad<90>
VDD2 SEG_pad<89>
SEG_pad<88>
VDD2 SEG_pad<87>
VDD VDD2
SEG_pad<86>
SEG_pad<85>
SEG_pad<84>
SEG_pad<83>
VDD2 SEG_pad<82>
SEG_pad<81>
VDD3 SEG_pad<80>
SEG_pad<79>
VDD3 SEG_pad<78>
SEG_pad<77>
SEG_pad<76>
VDD3 SEG_pad<75>
SEG_pad<74>
VDD3 SEG_pad<73>
SEG_pad<72>
SEG_pad<71>
VDD3 SEG_pad<70>
SEG_pad<69>
SEG_pad<68>
SEG_pad<67>
SEG_pad<66>
SEG_pad<65>
TST4_pad SEG_pad<64>
SEG_pad<63>
SEG_pad<62>
TST4_pad SEG_pad<61>
SEG_pad<60>
TST4_pad SEG_pad<59>
SEG_pad<58>
SEG_pad<57>
TST4_pad
TST4 TST2_pad
SEG_pad<56>
SEG_pad<55>
SEG_pad<54>
SEG_pad<53>
SEG_pad<52>
SEG_pad<51>
TST2_pad SEG_pad<50>
SEG_pad<49>
SEG_pad<48>
SEG_pad<47>
VBP_pad<0> SEG_pad<46>
SEG_pad<45>
SEG_pad<44>
VBP_pad<0> SEG_pad<43>
VB0+ VBP_pad<0>
SEG_pad<42>
SEG_pad<41>
SEG_pad<40>
SEG_pad<39>
VBP_pad<0> SEG_pad<38>
SEG_pad<37>
VBP_pad<1> SEG_pad<36>
SEG_pad<35>
VBP_pad<1> SEG_pad<34>
SEG_pad<33>
VB1+ VBP_pad<1>
SEG_pad<32>
SEG_pad<31>
SEG_pad<30>
VBP_pad<1> SEG_pad<29>
SEG_pad<28>
SEG_pad<27>
VBN_pad<1> SEG_pad<26>
SEG_pad<25>
SEG_pad<24>
VBN_pad<1> SEG_pad<23>
VB1- VBN_pad<1>
SEG_pad<22>
SEG_pad<21>
SEG_pad<20>
SEG_pad<19>
VBN_pad<1> SEG_pad<18>
SEG_pad<17>
VBN_pad<0> SEG_pad<16>
SEG_pad<15>
VBN_pad<0> SEG_pad<14>
SEG_pad<13>

VB0- VBN_pad<0>
SEG_pad<12>
SEG_pad<11>
SEG_pad<10>
SEG_pad<9>
VBN_pad<0> SEG_pad<8>
SEG_pad<7>
SEG_pad<6>
VLCDIN_pad SEG_pad<5>
SEG_pad<4>
VLCDIN_pad SEG_pad<3>
SEG_pad<2>
VLCDIN VLCDIN_pad
SEG_pad<1>

VLCDIN_pad

VLCDOUT_pad COM_pad<2>
COM_pad<4>
VLCDOUT_pad COM_pad<6>
COM_pad<8>
VLCDOUT VLCDOUT_pad
COM_pad<10>
COM_pad<12>
COM_pad<14>
VLCDOUT_pad COM_pad<16>
COM_pad<18>
DUMMY15 COM_pad<20>
COM_pad<22>
COM_pad<24>
DUMMY16 COM_pad<26>
COM__pad<28>
DUMMY17 COM_pad<30>
COM_pad<32>
COM_pad<34>
DUMMY18 COM_pad<36>
COM_pad<38>
DUMMY19 COM_pad<40>
COM_pad<42>
DUMMY20 COM_pad<44>
COM_pad<46>
COM_pad<48>
COM_pad<50>
COM_pad<52>
COM_pad<54>
DUMMY21 COM_pad<56>
COM_pad<58>
DUMMY22 COM_pad<60>
COM_pad<62>
DUMMY3 COM_pad<64>
COMS_PAD
DUMMY4

NOTES FOR VDD WITH COG:

The operation condition, VDD=1.8V (typical), should be satisfied under all operating conditions. UC1609c’ peak current (IDD) can
be up to ~15mA during high speed data-write to UC1609c’ on-chip SRAM. Such high pulsing current mandates very careful
design of VDD and VSS ITO trances in COG modules. When VDD and VSS trace resistance is not low enough, the pulsing IDD
current can cause the actual on-chip VDD to drop to below 1.7V and cause the IC to malfunction.

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

CONTROL REGISTERS
UC1609c contains registers, which control the chip operation. The following table is a summary of these control registers, a brief
description and the default values. These registers can be modified by commands, which will be described in the next two
sections, Command Table and Command Description.
Name: The Symbolic reference of the register. Note that, some symbol name refers to bits (flags) within another register.
Default: Numbers shown in Bold font are default values after Power-Up-Reset and System-Reset.

Name Bits Default Description

SL 6 00H Scroll Line. Scroll the displayed image up by SL rows. The valid SL value is between 0 (for no
scrolling) and (64). Setting SL outside of this range causes undefined effect on the displayed
image.
CA 8 00H Display Data RAM Column Address. Value range is 0 ~ 191.
(Used in Host to Display Data RAM access)
PA 4 0H Display Data Page Row Address. Value range is 0 ~ 8.
(Used in Host to Display Data RAM access)
BR 2 3H Bias Ratio. The ratio between VLCD and VD.
00b: 6 01b: 7 10b: 8 11b: 9
o
TC 2 0H Temperature Compensation (per C)
00b: -0.00% 01b: -0.05% 10b: -0.10% 11b: -0.15%
PM 8 49H Electronic Potentiometer to fine tune VD and VLCD
PMO 6 00H PM offset.
PC 3 6H Power Control.
PC[1:0]: low pump charge current select
00b: 0.6mA 01b: 1.0mA 10b: 1.4mA 11b: 2.3mA
PC[2]: to program the build-in charge pump stages
0b: External VLCD 1b: Internal VLCD (7x charge pump)
AC 3 1H Address Control:
AC[0]: WA: Automatic column/row Wrap Around (Default 1: ON)
AC[1]: Auto-Increment order
0: Column (CA) first 1: Page (PA) first
AC[2]: RID: RA (row address) auto increment direction (L:+1 H:-1)
DC 3 0H Display Control:
DC[0]: PXV: Pixels Inverse. Bit-wise data inversion. (Default 0: OFF)
DC[1]: APO: All Pixels ON (Default 0: OFF)
DC[2]: Display ON/OFF (Default 0: OFF)
LC 6 08H LCD Control:
LC[0]: Reserved (always set to 0)
LC[1]: MX, Mirror X. SEG/Column sequence inversion (Default: 0:OFF)
LC[2]: MY, Mirror Y. COM/Row sequence inversion (Default: 0:OFF)
LC[4:3]: Line Rate (Klps: Kilo-Line-per-second)
00b: 76 fps 01b: 95 fps 10b: 132 fps 11b: 168 fps
LC[5] : Partial Display.
0b: Disabled. Mux-Rate = CEN+1 (DST, DEN not used)
1b: Enabled. Mux-Rate = DEN-DST+1

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

Name Bits Default Description

CEN 6 3FH COM scanning end (last COM with full line cycle, 0-based index)
DST 6 00H Display start (first COM with active scan pulse, 0-based index)
DEN 6 3FH
Display end (last COM with active scan pulse, 0-based index)
Please maintain the following relationship:
CEN = “the actual number of pixel rows on the LCD” – 1
CEN
DEN
DST+ 9
MTPC 5 00H MTP Programming Control:
MTPC[2:0] : MTP command
000 : Idle 001 : Read
010 : Erase 011 : Program
1XX : For UltraChip debug use only
MTPC[3] : MTP Enable (automatically cleared after each MTP command)
MTPC[4] : Ignore/Use MTP.
0: Ignore 1: Use
MTPM 6 00H MTP Write Mask. For each bit, Bit =1: program, Bit=0: no action.
APC N/A Advanced Program Control. For UltraChip only. Please do not use.
Status Registers
OM 2 – Operating Modes (Read only)
00b: Reset 01b: (Not used)
10b: Sleep 11b: Normal
ID 1 PIN Access the connected status of ID pins.
POR 1 PIN Power-ON Reset control.
Controlled by the POR pin.
“L”: Power-ON Reset Enable.
“H”: Power-ON Reset Disabled.

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

COMMAND TABLE
The following is a list of host commands supported by UC1609c
C/D : 0 / 1 – Control / Data W/R : 0 / 1 – Write / Read Cycle D7~D0 : # Useful Data bits, – Don’t Care

No Command C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Action Default

1. Write Data Byte 1 0 # # # # # # # # Write 1 byte N/A
2. Read Data Byte 1 1 # # # # # # # # Read 1 byte N/A
ID MX MY WA DE WS MD MS Get Status
3. Get Status 0 1 N/A
VER POR # # # # # # PMO[5:0]
Set Column Address LSB 0 0 0 0 0 0 # # # # Set CA [3:0] 0
4.
Set Column Address MSB 0 0 0 0 0 1 # # # # Set CA [7:4] 0
5. Set Temp. Compensation 0 0 0 0 1 0 0 1 # # Set TC[1:0] 00b
6. Set Power Control 0 0 0 0 1 0 1 # # # Set PC[2:0] 110b
Set Adv. Program Control 0 0 1 1 0 0 R R Set APC[R][7:0],
7. 0 0 N/A
(double-byte command) # # # # # # # # R = 0~3
8. Set Scroll Line 0 0 0 1 # # # # # # Set SL[5:0] 0
9. Set Page Address 0 0 1 0 1 1 # # # # Set PA[3:0] 0
Set VBIAS Potentiometer 1 0 0 0 0 0 0 1
10. 0 0 Set PM[7:0] 49H
(double-byte command) # # # # # # # #
11. Set Partial Display Control 0 0 1 0 0 0 0 1 0 # Set LC[5] 0b
12. Set RAM Address Control 0 0 1 0 0 0 1 # # # Set AC[2:0] 001b
13. Set Frame Rate 0 0 1 0 1 0 0 0 # # Set LC[4:3] 01b
14. Set All-Pixel-ON 0 0 1 0 1 0 0 1 0 # Set DC[1] 0b
15. Set Inverse Display 0 0 1 0 1 0 0 1 1 # Set DC[0] 0b
16. Set Display Enable 0 0 1 0 1 0 1 1 1 # Set DC[2] 0b
17. Set LCD Mapping Control 0 0 1 1 0 0 0 # # 0 Set LC[2:1] 00b
18. System Reset 0 0 1 1 1 0 0 0 1 0 System Reset N/A
19. NOP 0 0 1 1 1 0 0 0 1 1 No operation N/A
Set Test Control 1 1 1 0 0 1 TT For testing only.
20. 0 0 N/A
(double-byte command) # # # # # # # # Do not use.
21. Set LCD Bias Ratio 0 0 1 1 1 0 1 0 # # Set BR[1:0] 11b: 9
1 1 1 1 0 0 0 1
22. Set COM End 0 0 Set CEN[5:0] 63D
-- -- # # # # # #
1 1 1 1 0 0 1 0
23. Set Partial Display Start 0 0 Set DST[5:0] 0
-- -- # # # # # #
1 1 1 1 0 0 1 1
24. Set Partial Display End 0 0 Set DEN[5:0] 63D
-- -- # # # # # #
1 1 1 1 1 0 0 0
25. Set MTP Operation Control 0 0 Set MTPC[4:0] 00H
-- -- -- # # # # #
1 1 1 1 1 0 0 1
26. Set MTP Write Mask 0 0 Set MTPM[5:0] 0
-- -- # # # # # #
1 1 1 1 0 1 0 0
27. Set VMTP1 Potentiometer 0 0 Set VMTP1[7:0] N/A
# # # # # # # #
1 1 1 1 0 1 0 1
28. Set VMTP2 Potentiometer 0 0 Set VMTP2[7:0] N/A
# # # # # # # #
1 1 1 1 0 1 1 0
29. Set MTP Write Timer 0 0 Set MTPWT[7:0] N/A
# # # # # # # #
1 1 1 1 0 1 1 1
30. Set MTP Read Timer 0 0 Set MTPRT[7:0] N/A
# # # # # # # #
Serial Read Command (Enabled only in S8/S9 mode )
0 0 1 1 1 1 1 1 1 0
31. Get Status ID MX MY WA DE WS MD MS Get Status N/A
0 1
VER POR # # # # # # PMO[5:0]
0 0 1 1 1 1 1 1 1 1 FFH
32. Read Data
1 1 # # # # # # # #
Any bit pattern other than those listed above may result in NOP (No Operation).

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COMMAND DESCRIPTION

1. Write Data Byte to Memory

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Write data 1 0 8-bit data write to SRAM

2. Read Data Byte from Memory

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Read data 1 1 8-bit data read from SRAM
Write/Read Data Byte (Command 1,2) access Display Data RAM based on Page Address (PA) register and Column Address (CA)
register. To minimize bus interface cycles, PA and CA will increase or decrease automatically after each bus cycle, depending on
the setting of Access Control (AC) registers. PA and CA can also be programmed directly by issuing Set Page Address and Set
Column Address commands.
If Wrap-Around (WA) is OFF (AC[0] = 0), CA will stop increasing after reaching the end of the page, and system programmers
need to set the values of PA and CA explicitly. If WA is ON (AC[0]=1), when CA reaches the end of the page, CA will be reset to
0 and PA will increase or decrease by 1, depending on the setting of Page Increment Direction (PID, AC[2]). When PA reaches
the boundary of RAM, PA will be wrapped around to the other end of RAM and continue.

3. Get Status

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0 1 ID MX MY WA DE WS MD MS
Get Status
0 1 VER POR PMO5 PMO4 PMO3 PMO2 PMO1 PMO0
Status1 definitions:
ID: Provide access to ID pins connection status.
MX: Status of register LC[1], mirror X.
MY: Status of register LC[2], mirror Y.
WA: Status of register AC[0]. Automatic column/row wrap around.
DE: Display Enable flag. DE=1 when display is enabled.
WS: MTP Operation succeeded
MD: MTP Option (1 for MTP version, 0 for non-MTP version)
MS: MTP action status
Status2 definitions:
Ver: IC Version, 0~ 1.
POR: Power-ON Reset control.
PMO[5:0]: PM offset value. Default: 00H

4. Set Column Address

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Column Address LSB CA[3:0] 0 0 0 0 0 0 CA3 CA2 CA1 CA0
Set Column Address MSB CA[7:4] 0 0 0 0 0 1 CA7 CA6 CA5 CA4
Set the SRAM column address before Write/Read memory from host interface.
CA value range: 0~191

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5. Set Temperature Compensation

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Temperature Comp. TC[1:0] 0 0 0 0 1 0 0 1 TC1 TC0
Set VBIAS temperature compensation coefficient (%-per-degree-C)
Temperature compensation curve definition:
o o o o
00b= -0.00%/ C 01b= -0.05%/ C 10b= -0.10%/ C 11b= -0.15%/ C

6. Set Power Control

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Power Control PC[2:0] 0 0 0 0 1 0 1 PC2 PC1 PC0
PC[1:0] : to select low-pump charge current
00b: 0.6mA 01b: 1.0mA 10b: 1.4mA 11b: 2.3mA
Set PC[2] : to program the build-in charge pump stages.
0b: External VLCD 1b: Internal VLCD (7x charge pump)

7. Set Advanced Program Control

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Adv. Program Control APC[R][7:0] 0 0 0 0 1 1 0 0 R R
(Double-byte command) 0 0 APC7 APC6 APC5 APC4 APC3 APC2 APC1 APC0
For UltraChip only. Please Do NOT use.

8. Set Scroll Line

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Scroll Line SL[5:0] 0 0 0 1 SL5 SL4 SL3 SL2 SL1 SL0
Set the scroll line number.
Scroll line setting will scroll the displayed image up by SL rows. Icon output CIC will not be affected by Set Scroll Line
command.
Image row 0 row 0 Image row N row 0
: : : :
Image row N-1 : : :
Image row N Image row 63
: Image row 0
: :
Image row 63 row 63 Image row N-1 row 63
SL=0 SL=N

9. Set Page Address

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Page Address PA[3:0] 0 0 1 0 1 1 PA3 PA2 PA1 PA0
Set the SRAM page address before write/read memory from host interface. Each page of SRAM corresponds to 8 COM lines on
LCD panel, except for the last page. The last page corresponds to the icon output CIC.
Possible value = 0~8.

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10. Set VBIAS Potentiometer

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set VBIAS Potentiometer PM [7:0] 0 0 1 0 0 0 0 0 0 1
(Double-byte command) 0 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0
Program VBIAS Potentiometer (PM[7:0]). See section LCD Voltage Setting for more detail.
Effective range: 0 ~ 255 (Default: 49H)

11. Set Partial Display Control

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Partial Display Enable LC [5] 0 0 1 0 0 0 0 1 0 LC5
This command is used to enable partial display function.
LC[5] : 0b: Disable Partial Display, Mux-Rate = CEN+1 (DST, DEN not used.)
1b: Enable Partial Display, Mux-Rate = DEN-DST+1

12. Set RAM Address Control

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set AC [2:0] 0 0 1 0 0 0 1 AC2 AC1 AC0
Program registers AC[2:0] for RAM address control. It controls the auto-increment behavior of CA and PA.

AC[0] – WA, Automatic column/page wrap around.

0: CA or PA (depends on AC[1]= 0 or 1) will stop increasing after reaching boundary
1: CA or PA (depends on AC[1]= 0 or 1) will restart, and CA or PA will increase by one.

AC[1] – Auto-Increment order

0 : column (CA) increasing (+1) first until CA reach CA boundary, then PA will increase by (+/-1).
1 : page (PA) increasing (+/-1) first until PA reach PA boundary, then CA will increase by (+1).

AC[2] – PID, page address (PA) auto increment direction ( 0/1 = +/- 1 )
When WA=1 and CA reaches CA boundary, PID controls whether page address will be adjusted by
+1 or -1.

13. Set Frame Rate

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Frame Rate LC [4:3] 0 0 1 0 1 0 0 0 LC4 LC3
Program LC [3] for frame rate setting
00b: 76 fps 01b: 95 fps 10b: 132 fps 11b: 168 fps
(fps: frame-per-second)

14. Set All Pixel ON

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set All Pixel ON DC [1] 0 0 1 0 1 0 0 1 0 DC1
Set DC[1] to force all SEG drivers to output ON signals. This function has no effect on the existing data stored in display RAM.
(Default: 0)

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15. Set Inverse Display

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Inverse Display DC [0] 0 0 1 0 1 0 0 1 1 DC0
Set DC[0] to force all SEG drivers to output the inverse of the data (bit-wise) stored in display RAM. This function has no effect on
the existing data stored in display RAM. (Default: 0)

16. Set Display Enable

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Display Enable DC[2] 0 0 1 0 1 0 1 1 1 DC2
This command is for programming register DC[2]. When DC[2] is set to 1, UC1609c will first exit from sleep mode, restore the
power and then turn on COM drivers and SEG drivers. (Default: 0)

17. Set LCD Mapping Control

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set LCD Control LC[2:1] 0 0 1 1 0 0 0 MY MX 0
Set LC[2:1] for COM (row) mirror (MY), SEG (column) mirror (MX). (Default: 00b)
MY is implemented by reversing the mapping order between RAM and COM (row) electrodes. The data stored in RAM is not
affected by MY command. MY will have immediate effect on the display image.
MX is implemented by selecting the CA or 63-CA as write/read (from host interface) display RAM column address so this function
will only take effect after rewriting the RAM data.

18. System Reset

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

System Reset 0 0 1 1 1 0 0 0 1 0
This command will activate the system reset.
Control register values will be reset to their default values. Data store in RAM will not be affected.

19. NOP

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

No Operation 0 0 1 1 1 0 0 0 1 1
This command is used for “no operation”.

20. Set Test Control

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set TT 0 0 1 1 1 0 0 1 TT
(Double byte command) 0 0 For test only
This command is used for UltraChip production testing. Please do NOT use.

21. Set LCD Bias Ratio

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set Bias Ratio BR [1:0] 0 0 1 1 1 0 1 0 BR1 BR0
Bias ratio definition:
00b= 6 01b= 7 10b= 8 11b= 9

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22. Set COM End

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set CEN [5:0] 0 0 1 1 1 1 0 0 0 1
(Double-byte command) 0 0 - - CEN register parameter

This command programs the ending COM electrode. CEN defines the number of used COM electrodes, and it should correspond
to the number of pixel-rows in the LCD. When the LCD has less than 64 pixel rows, the LCM designer should set CEN to N-1
(where N is the number of pixel rows) and use COM1 through COM-N as COM driver electrodes. (Default: 63)

23. Set Partial Display Start

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set DST [5:0] 0 0 1 1 1 1 0 0 1 0
(Double-byte command) 0 0 - - DST register parameter

This command programs the starting COM electrode, which has been assigned a full scanning period and will output an active
COM scanning pulse.

24. Set Partial Display End

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set DEN [5:0] 0 0 1 1 1 1 0 0 1 1
(Double-byte command) 0 0 - - DEN register parameter

This command programs the ending COM electrode, which has been assigned a full scanning period and will output an active
COM scanning pulse.
CEN, DST, and DEN are 0-based index of COM electrodes. They control only the COM electrode activity, and do not affect the
mapping of display RAM to each COM electrodes. The image displayed by each pixel row is therefore not affected by the setting
of these three registers.
When LC[5]=1b, the Mux-Rate is narrowed down to DEN – DST + 1. When MUX rate is reduced, reduce the frame rate
accordingly to reduce power. Changing MUX rate also require BR and VLCD to be reduced.
For minimum power consumption, set LC[5]=1b, set (DST, DEN, CEN) to minimize Mux rate, use slowest frame rate which
satisfies the flicker requirement, set PC[0]=0b, and use lowest BR, lowest VLCD which satisfies the contrast requirement. When
Mux-Rate is under 16, it is recommended to set BR=6 for optimum power saving.
In either case, DST/DEN defines a small subsection of the display which will remain active while shutting down all the rest of the
display to conserve energy.
Keep CEN
DEN
DST+ 9
Scan Method Display Result:
0
Not scanned
:
DST
Pulse Enable Display segment
DEN
Not scanned
CEN
Not Scanned
:
63

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Display Function Setting Image in DDRAM Display Function Setting Image in DDRAM
Data (Physical origin: Data (Physical origin:
AIO MX RID AIO MX RID
Direction upper left corner) Direction upper left corner)
AC[1] LC[1] AC[2] AC[1] LC[1] AC[2]

X-Y
Normal 0 0 0 1 0 0
Exchange

X-Y
Y-mirror 0 0 1 Exchange 1 0 1
Y-mirror

X-Y
X-mirror 0 1 0 Exchange 1 1 0
X-mirror

X-Y
X-mirror Exchange
0 1 1 1 1 1
Y-mirror X-mirror
Y-mirror

25. Set MTP Operation Control

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set MTPC [4:0] 0 0 1 1 1 1 1 0 0 0
(Double-byte command) 0 0 - - - MTPC4 MTPC3 MTPC2 MTPC1 MTPC0
This command is for MTP operation control: (MTPC[4:0] : default: D0H)

MTPC[2:0] : MTP command

000 : Sleep 001 : MTP Read 010 : MTP Erase 011 : MTP Program
1xx : For UltraChip use only.

MTPC[3] : MTP Enable (automatically cleared each time after MTP command is done)
MTPC[4] : MTP value valid (set H to active MTP value)
DC[2] and MTPC[3] are mutually exclusive. Only one of these two control flags can be set to ON at any time. In other words,
when DC[2] is ON, all MTP operations will be blocked, and, when MTP operation is active, set DC[2] to 1 will be blocked.

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26. Set MTP Write Mask

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set MTPM [5:0] 0 0 1 1 1 1 1 0 0 1
(Double-byte command) 0 0 - - MTPM[5:0]
This command enables Write to each of the individual MTP bits. When MTPM[x]=1, the x-th bit of the MTP memory will be
programmed to “1”. MTPM[x]=0 means no Write action for x-th bit. And the content of this bit will not change.
The amount of “programming current” increases with the number of 1’s in MTPM. If the “programming current” appears to be too
high for the LCM design (e.g. TST4 ITO trace is not wide enough to supply the current), use multiple write cycles and distribute
the 1’s evenly into these cycles.
MTPM[5:0] : Set PMO value (Default: 00H)

27. Set VMTP1 Potentiometer

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set VMTP1 [7:0] 0 0 1 1 1 1 0 1 0 0
(Double-byte command) 0 0 VMTP1[7:0]

This command is for fine tuning VOPT1 setting (with BR=00).

28. Set VMTP2 Potentiometer

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set VMTP2 [7:0] 0 0 1 1 1 1 0 1 0 1
(Double-byte command) 0 0 VMTP2[7:0]

This command is for fine tuning VMTP2 setting (with BR=11).

29. Set MTP Write Timer

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set MTPWT [7:0] 0 0 1 1 1 1 0 1 1 0
(Double-byte command) 0 0 MTPWT[7:0]

This command is only valid when MTPC[3]=1.

30. Set MTP Read Timer

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Set MTPRT [7:0] 0 0 1 1 1 1 0 1 1 1
(Double-byte command) 0 0 MTPRT[7:0]

This command is only valid when MTPC[3]=1.

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Serial Read Command (Enable only in S8/S9 mode):

31. Get Status

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 1 1 1 1 1 1 0
Get Status 0 1 ID MX MY WA DE WS MD MS
0 1 VER POR PMO5 PMO4 PMO3 PMO2 PMO1 PMO0
See command 3.

32. Read Data Byte from Memory

Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0

Read data 0 0 1 1 1 1 1 1 1 1
(double-byte command) 1 1 # # # # # # # #

See command 2 for more information.

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LCD VOLTAGE SETTING

MULTIPLEX RATES VLCD GENERATION
Multiplex Rate is completely software programmable in VLCD may be supplied either by internal charge pump or by
UC1609c via registers CEN, DST, DEN, and partial display external power supply. The source of VLCD is controlled by
control flags LC[5]. PC[2].

Combined with low power partial display mode and a low bias When VLCD is generated internally, the voltage level of VLCD is
ratio of 6, UC1609c can support wide variety of display control determined by three control registers: BR (Bias Ratio), PM
options. For example, when a system goes into stand-by (Potentiometer), and TC (Temperature Compensation), with
mode, a large portion of LCD screen can be turned off to the following relationship:
conserve power.
VLCD = (CV 0 + C PM × PM ) × (1 + (T − 25) × CT %)
BIAS RATIO SELECTION where
Bias Ratio (BR) is defined as the ratio between VLCD and VD,
CV0 and CPM are two constants, whose value depends on
i.e.
the setting of BR register, as illustrated in the table on the
BR = VLCD /VD, next page,
where PM is the numerical value of PM register,
O
VD = VB1+ – VB1– = VB0+ – VB0–. T is the ambient temperature in C, and
The theoretical optimum Bias Ratio can be estimated by CT is the temperature compensation coefficient as
Mux + 1 . BR of value 15~20% lower/higher than the selected by TC register.
optimum value calculated above will not cause significant
visible change in image quality. VLCD FINE TUNING
Black-and-white STN LCD is sensitive to even a 1%
UC1609c supports four BR as listed below. BR can be
mismatch between IC driving voltage and the VOP of LCD.
selected by software program.
However, it is difficult for LCD makers to guarantee such high
BR 0 1 2 3 precision matching of parts from different venders. It is
therefore necessary to adjust VLCD to match the actual VOP of
Bias Ratio 6 7 8 9 the LCD.
Table 1: Bias Ratios For the best result, software based approach for VLCD
adjustment or MTP is the recommended method for VLCD fine-
TEMPERATURE COMPENSATION tuning. System designers should always consider the contrast
Four different temperature compensation coefficients can be fine tuning requirement before finalizing on the LCM design.
selected via software. The four coefficients are given below:
LOAD DRIVING STRENGTH
TC 0 1 2 3
o
The power supply circuit of UC1609c is designed to handle
% per C –0.00 –0.05 –0.10 –0.15 LCD panels with loading up to ~24nF using 20-Ω/Sq ITO
glass with VDD2/3
2.6V. For larger LCD panels, use lower
Table 2: Temperature Compensation
resistance ITO glass packaging.

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VLCD QUICK REFERENCE

10
VLCD

4
0 32 64 96 128 160 192 224 256
PM

VLCD Programming Curve.

BR CV0 (V) CPM (mV) PM VLCD Range (V)

0 4.82
6 4.821 12.266
255 7.95
0 5.62
7 5.619 14.298
255 9.27
0 6.42
8 6.420 16.343
255 10.59
0 7.22
9 7.217 18.378
233 11.50

Note:
1. For good product reliability, keep VLCD under 11.5V over all temperature.
2. The integer values of BR above are for reference only and may have slight shift.

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©1999~2012 65x192 STN Controller-Driver

HI-V GENERATOR AND BIAS REFERENCE CIRCUIT

VDD
VB0+

VDD CB0
VB0-
VDD2/VDD3
VB1+

VDD2 CB1
VDD3 VB1-

UC1609c VLCDOUT
VLCDIN

VSS CL
VSS2 RL
(OPTIONAL)

FIGURE 1: Reference circuit using internal Hi-V generator circuit

Note
Sample component values: (The illustrated circuit and component values are for reference only. Please optimize for specific
requirements of each application.)
CBx : 2.2 µF/5V or 300x LCD load capacitance, whichever is higher.
CL : 330nF(25V) is appropriate for most applications.
RL: 3.3M~10M Ω to act as a draining circuit when VDD is shut down abruptly.

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LCD DISPLAY CONTROLS

CLOCK & TIMING GENERATOR DRIVER ENABLE (DE)
UC1609c contains a built-in system clock. All required Driver Enable is controlled by the value of DC[2] via Set
components for the clock oscillator are built-in. No external Display Enable command. When DC[2] is set to OFF (logic
parts are required. “0”), both COM and SEG drivers will become idle and
UC1609c will put itself into Sleep Mode to conserve power.
4 different frame rates are provided for system design
flexibility. The frame rate is controlled by register LC[4:3]. When DC[2] is set to ON, the DE flag will become “1”,and
When Mux-Rate is above 45, Frame rate: 76fps, 95fps, UC1609c will first exit from Sleep Mode, restore the power
132fps, and 168 fps. (VLCD, VD etc.) and then turn on COM and SEG drivers.
When Mux-Rate is lowered to 44, 33, 22, and 17, frame rate
will be scaled down automatically by 1.5, 2, 3, and 4 times to ALL PIXELS ON (APO)
reduce power consumption. When set, this flag will force all SEG drivers to output ON
Choose lower frame rate for lower power, and choose higher signals, disregarding the data stored in the display buffer.
frame rate to improve LCD contrast and minimize flicker. This flag has no effect when Display Enable is OFF and it has
no effect on data stored in RAM.
DRIVER MODES
COM and SEG drivers can be in either Idle mode or Active INVERSE (PXV)
mode, controlled by Display Enable flag (DC[2]). When SEG When this flag set to ON, SEG drivers will output the inverse
and COM drivers are in idle mode, they will be connected of the value it received from the display buffer RAM (bit-wise
together to ensure zero DC condition on the LCD. inversion). This flag has no impact on data stored in RAM.

DRIVER ARRANGEMENTS PARTIAL DISPLAY

The naming conventions are: COMx, where x = 1~64, refers
UC1609c provides flexible control of Mux Rate and active
to the row driver for the x-th row of pixels on the LCD panel.
display area. Please refer to commands Set COM End, Set
The mapping of COM(x) to LCD pixel rows is fixed and it is Partial Display Start, and Set Partial Display
not affected by SL, CEN, DST, DEN, MX or MY settings. End for more detail.

DISPLAY CONTROLS
There are three groups of display control flags in the control
register DC: Driver Enable (DE), All-Pixel-ON (APO) and
Inverse (PXV). DE has the overriding effect over PXV and
APO.

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ITO LAYOUT AND LC SELECTION

Since COM scanning pulses of UC1609c can be as short as For good image quality, please minimize SEG ITO trace
91µS, it is critical to control the RC delay of COM and SEG resistance and limit the worst case of SEG signal RC delay as
signal to minimize crosstalk and maintain good mass calculated below.
production consistency.
(RCOL / 2.7 + RSEG) x CCOL < 6.30µS
COM TRACES where
Excessive COM scanning pulse RC decay can cause CCOL: LCD loading capacitance of one pixel column. It
fluctuation of contrast and increase COM direction crosstalk. can be calculated by CLCD / (# of column), where
Please limit the worst case of COM signals RC delay (RCMAX) CLCD is the LCD panel capacitance.
as calculated below RCOL: ITO resistance over one column of pixels within the
(RROW / 2.7 + RCOM) x CROW < 9.23µS active area

where RSEG: SEG routing resistance from IC to the active area +

SEG driver output impedance.
CROW: LCD loading capacitance of one row of pixels. It
can be calculated by CLCD/Mux-Rate, where CLCD is (Use worst case values for all calculations)
the LCD panel capacitance.
SELECTING LIQUID CRYSTAL
RROW: ITO resistance over one row of pixels within the
active area The selection of LC material is crucial to achieve the optimum
image quality of finished LCM.
RCOM: COM routing resistance from IC to the active area
+ COM driver output impedance. When (V90-V10)/V10 is too large, image contrast will deteriorate,
and images will look murky and dull.
In addition, please limit the min-max spread of RC decay to
be: When (V90-V10)/V10 is too small, image contrast will become
too strong, and crosstalk will increase.
| RCMAX – RCMIN | < 2.76µS
For the best result, it is recommended the LC material has the
so that the COM distortions on the top of the screen to the following characteristics:
bottom of the screen are uniform.
(V90-V10)/V10 = (VON-VOFF)/VOFF x 0.72~0.80
(Use worst case values for all calculations)
where V90 and V10 are the LC characteristics, and VON and
VOFF are the ON and OFF VRMS voltage produced by LCD
SEG TRACES driver IC at the specific Mux-rate.
Excessive SEG signal RC decay can cause image dependent
Two examples are provided below:
changes of medium gray shades and sharply increase the
crosstalk of SEG direction. Duty Bias VON/VOFF -1 x0.80 x0.72
1/65 1/9 13.3% 10.6% 9.6%
1/65 1/8 13.1% 10.5% 9.5%

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

RAM
W/R

POL

COM1

COM2

COM3

SEG1

SEG2

FIGURE 2: COM and SEG Electrode Driving Waveform

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

HOST INTERFACE
As summarized in the table below, UC1609c supports two (2) 8-bit parallel bus protocols and three (3) serial bus protocols.
Designers can choose either the 8-bit parallel bus to achieve high data transfer rate, or use serial bus to create compact LCD
modules and minimize connector pins.

Bus Type
2
8080 6800 S8 (4-wire) S9 (3-wire) I C (2-wire)
Width 8-bit 8-bit Serial
Access Read / Write Read (status) / Write R/W
BM[1:0] 10 11 00 01 01
Control & Data Pins

D[7] Data Data -- 0 1

CS[1:0] Chip Select A[3:2]
CD Control/Data 0
__ ___
WR0 WR R/W 0
___
WR1 RD EN 0
D[6,2,1] Data --
D[5:3], D[0] Data D[5:3]=SDA, D[0]=SCK
Connect unused control pins and data bus pins to VDD for “H” or VSS for “L”.

CS CS RESET
Disable Bus Interface Init. Bus State Init. Bus State
8-bit
–

S8 or S9



2
IC – –

• CS disable bus interface – CS can be used to disable Bus Interface Write / Read Access.
• RESET can be pin reset / soft reset / power on reset.

Table 3: Host interfaces Summary

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

PARALLEL INTERFACE
The timing relationship between UC1609c internal control cycle need to be performed before the actual data can
signal RD, WR and their associated bus actions are shown in propagate through the pipeline and be read from data port
the figure below. D[7:0].
The Display RAM read interface is implemented as a two- There is no pipeline in write interface of Display RAM. Data is
stage pipeline. This architecture requires that, every time transferred directly from bus buffer to internal RAM on the
memory address is modified, either in parallel mode or serial rising edges of write pulses.
mode, by either Set CA or Set PA command, a dummy read

External
CD
___
WR
__
RD

D[7:0] L L SB DL DL +K CMSB CL SB Dummy DC DC +1 M MSB ML SB

Internal
Write

Read

Data DL DL+K Dummy DC D C+1 DC +2

Latch
Column
Address L L+K L+K+1 C C+1 C+2 C+3 M

Figure 3: Parallel Interface & Related Internal Signals

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

SERIAL INTERFACE
2
UC1609c supports three serial modes, one 4-wire SPI mode (S8), one 3-wire SPI mode (S9) and one 2-wire SPI mode (I C). Bus
interface mode is determined by the wiring of the BM[1:0] and D[7]. See table in last page for more detail.

S8 (4-WIRE) INTERFACE
Pins CS[1:0] are used for chip select and bus cycle reset. Pin If CD=0, the data byte will be decoded as command. If CD=1,
CD is used to determine the content of the data been these 8 bits will be treated as data and transferred to proper
transferred. During each write cycle, 8 bits of data, MSB first, address in the Display Data RAM on the rising edge of the
are latched on eight rising SCK edges into an 8-bit data last SCK pulse. Pin CD is examined when SCK is pulled low
holder. for the LSB (D0) of each token.

Read Command Read Status

CS0

SDA D7 D6 D5 D4 D3 D2 D1 D0

SCK

CD

Display
D7 D6 D5 D4 D3 D2 D1 D0
Module
MCU Data Display Module Data
Transmission Starts Transmission Starts

FIGURE 4.a: 4-wire Serial Interface (S8) – Read

CS0

SDI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5

SCK

CD

Figure 4.b: 4-wire Serial Interface (S8) – Write

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

S9 (3-WIER) INTERFACE
Pins CS[1:0] are used for chip select and bus cycle reset. On transferred to proper address in the Display Data RAM at the
each write cycle, the first bit is CD, which determines the rising edge of the last SCK pulse.
content of the following 8 bits of data, MSB first. These 8
command or data bits are latched on rising SCK edges into By sending CD information explicitly in the bit stream, control
an 8-bit data holder. If CD=0, the data byte will be decoded as pin CD is not used, and should be connected to either VDD or
command. If CD=1, this 8-bit will be treated as data and VSS. The toggle of CS0 (or CS1) for each byte of
data/command is recommended but optional.

Rea d Command Read Status

CS0

SDA CD D7 D6 D5 D4 D3 D2 D1 D0

SCK

Display
Module D7 D6 D5 D4 D3 D2 D1 D0

MCU Data Display Module Data

Transmission Starts Transmission Starts

FIGURE 5.a: 3-wire Serial Interface (S9) – Read

CS0

SDI CD D7 D6 D5 D4 D3 D2 D1 D0 CD D7 D6

SCK

Figure 5.b: 3-wire Serial Interface (S9) – Write

29
ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

2
I C (2-WIRE) INTERFACE

Write Mode
MPU MPU MPU MPU MPU
⇓ ⇑ ⇓ ⇓ ⇑ ⇓ ⇓ ⇑ ⇑ ⇓
A A C D D D D
S 0 1 1 1 0 A A … ... A A P
3 2 D 7 0 7 0

Read Mode
MPU MPU MPU MPU MPU
⇓ ⇑ ⇑ ⇑ ⇓ ⇑ ⇑ ⇓ ⇓ ⇓
A A C D D D D
S 0 1 1 1 1 A A … ... A N P
3 2 D 7 0 7 0

When BM[1:0] is set to “LH” and D[7] is set to “H”, UC1609c is

2
configured as an I C bus signaling protocol compliant slave START
2
device. Please refer to I C standard for details of the bus
signaling protocol, and AC Characteristic section for timing
parameters of UltraChip implementation.
In this mode, pins CS[1:0] become A[3:2] and is used to Header
configure UC1609c’ device address. Proper wiring to VDD or
2
VSS is required for the IC to operate properly for I C mode.
2 Command =
Each UC1609c I C interface sequence starts with a “S” (Start)
System Reset
from the bus master, followed by a sequence header,
containing a device address, the mode of transfer (CD,
0:Control, 1:Data), and the direction of the transfer (RW,
0:Write, 1:Read).
STOP
Since both WR and CD are expressed explicitly in the header
2
byte, the control pins WR[1:0] and CD are not used in I C
mode and should be connected to VSS.
The direction (read or write) and content type (command or
START
data) of the data bytes following each header byte are fixed
for the sequence. To change the direction (RW) or the
content type (CD), start a new sequence with a START (S)
flag, followed by a new header. Header
After receiving the header, the UC1609c will send out a “A”
(Acknowledge signal, pull to “L”). Then, depends on the
setting of the header, the transmitting device (either the bus Command / Data
master or UC1609c) will start placing data bits on SDA, MSB
to LSB, and the sequence will repeat until a STOP signal (P,
in WRITE mode), or an N (Not Acknowledged, in READ mode)
is sent by the bus master. Command / Data
2
When using I C serial mode, if command System Reset is
to be written, the writing sequence must be finished (STOP)
before succeeding data or commands start. The flow chart on
the right shows a writing sequence with a “System Reset” Command / Data
command.
Note that, for data read (CD=1), the first byte of data
transmitted will be dummy.
STOP

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

HOST INTERFACE REFERENCE CIRCUIT

VDD

VCC VDD

D7~D0 D7~D0

CD CD
WR WR0(WR)
RD WR1(RD)

ADDRESS CS0
MPU UC1609c
IORQ DECODER CS1

RST RST

VDD

ID
BM1
BM0

GND VSS

FIGURE 6: 8080/8bit parallel mode reference circuit

VDD

VCC VDD

D7~D0 D7~D0

CD CD
R/W WR0(R/W)
E WR1(E)

ADDRESS CS0
MPU UC1609c
IORQ DECODER CS1

RST RST

VDD

ID
BM1
BM0

GND VSS

FIGURE 7: 6800/8bit parallel mode reference circuit

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

VDD

VCC VDD

SCK SCK(D0)
SDA SDA(D5-D3)
CD CD
WR0
WR1

ADDRESS CS0
MPU UC1609c
IORQ DECODER CS1

RST RST

VDD

ID
BM1
BM0

GND VSS

FIGURE 8: Serial-8 serial mode reference circuit

VDD

VCC VDD
D7

SCK SCK(D0)
SDA SDA(D5-D3)
CD
WR0
WR1

ADDRESS CS0
MPU UC1609c
IORQ DECODER CS1

RST RST

VDD

ID
BM1
BM0

GND VSS

FIGURE 9: Serial-9 serial mode reference circuit

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

VDD

VCC R1 DB7 VDD

R2

SCK SCK(D0)
SDA SDA(D5-D3)
CD
WR0
WR1
CS0(A2)
CS1(A3)

MPU UC1609c

RST RST

VDD

ID
BM1
BM0

GND VSS

2
FIGURE 10: I C serial mode reference circuit

Note
• The ID pins are for production control. The connection will affect the content of D[7] of the 1-st byte of the Get Status
command. Connect to VDD for “H” or VSS for “L”.
• RST pin is optional. When the RST pin is not used, connect it to VDD.
•
2
When using I C serial mode, CS1/0 are user configurable and affect A[3:2] of device address.
• R1, R2: 2k ~ 10k Ω, use lower resistor for bus speed up to 3.6MHz, use higher resistor for lower power.
• When using Read function:

(8080) Set WR1=0 (8080) Set WR1=1

(6800) Set WR1=1  data output will be enabled. (6800) Set WR1=0  data output will be disabled.
(Serial) Set SCK=0 (Serial) Set SCK=1

• It is REQUIRED to set MPU’s data port to 1 before Data Read or Status Read actions.

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

DISPLAY DATA RAM (DDRAM)

DATA ORGANIZATION ROW MAPPING
The input display data is stored to a dual port static DDRAM COM electrode scanning orders are not affected by Start Line
(DDRAM, for Display Data RAM) organized as 65x192. (SL), Fixed Line (FLT & FLB) or Mirror Y (MY, LC[2]). Visually,
register SL having a non-zero value is equivalent to scrolling
After setting CA and RA, the subsequent data write cycle will the LCD display up or down (depends on MY) by SL rows.
store the data for the specified pixel to the proper memory
location. RAM ADDRESS GENERATION
Please refer to the map in the following page between the The mapping of the data stored in the display SRAM and the
relation of COM, SEG, SRAM, and various memory control scanning electrodes can be obtained by combining the fixed
registers. Rm scanning sequence and the following RAM address
generation formula.
DISPLAY DATA RAM ACCESS
During the display operation, the RAM line address
The Display RAM is a special purpose dual port RAM which generation can be mathematically represented as following:
allows asynchronous access to both its column and row data.
Thus, RAM can be independently accessed both for Host For the 1-st line period of each field
Interface and for display operations. Line = SL
Otherwise
DISPLAY DATA RAM ADDRESSING Line = Mod(Line+1, 64)

A Host Interface (HI) memory access operation starts with Where Mod is the modular operator, and Line is the bit slice
specifying Row Address (RA) and Column Address (CA) by line address of RAM to be outputted to column drivers. Line 0
issuing Set Row Address and Set Column Address corresponds to the first bit-slice of data in RAM.
commands. The above Line generation formula produce the “loop around”
If wrap-around (WA, AC[0]) is OFF (0), CA will stop increasing effect as it effectively resets Line to 0 when Line+1 reaches
after reaching the end of row (191), and system programmers 64.
need to set the values of PA and CA explicitly.
MY IMPLEMENTATION
If WA is ON (1), when CA reaches end of page, CA will be
reset to 0 and PA will increase or decrease, depending on the Row Mirroring (MY) is implemented by reversing the mapping
setting of row Increment Direction (RID, AC[2]). When PA order between row electrodes and RAM, i.e. the mathematical
reaches the boundary of RAM (i.e. PA = 0 or 7), PA will be address generation formula becomes:
wrapped around to the other end of RAM and continue. st
For the 1 line period of each field
Line = Mod(SL + MR -1, 64)
MX IMPLEMENTATION Otherwise
Column Mirroring (MX) is implemented by selecting either (CA) Line = Mod(Line-1 , 64)
or (191–CA) as the RAM column address. Changing MX Visually, the effect of MY is equivalent to flipping the display
affects the data written to the RAM. upside down. The data stored in display RAM is not affected
Since MX has no effect of the data already stored in RAM, by MY.
changing MX does not have immediate effect on the
displayed pattern. To refresh the display, refresh the data
stored in RAM after setting MX.

34
ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

Line Panel MY=0 MY=1

PA[3:0] 0 Ad dress Location SL=0 SL=16 SL=0 SL=16
D0 R0 1 0 COM1 R0 R16 R6 3 R 15
D1 R1 1 0 COM2 R1 R17 R6 2 R 14
D2 R2 1 1 COM3 R2 R18 R6 1 R 13
D3 R3 1 1 COM4 R3 R19 R6 0 R 12
0000 Page 0
D4 R4 1 0 COM5 R4 R20 R5 9 R 11
D5 R5 0 0 COM6 R5 R21 R5 8 R 10
D6 R6 0 1 COM7 R6 R22 R5 7 R9
D7 R7 0 1 COM8 R7 R23 R5 6 R8
D0 R8 COM9 R8 R24 R5 5 R7
D1 R9 COM1 0 R9 R25 R5 4 R6
D2 R10 COM1 1 R10 R26 R5 3 R5
D3 R11 COM1 2 R11 R27 R5 2 R4
0001 Page 1
D4 R12 COM1 3 R12 R28 R5 1 R3
D5 R13 COM1 4 R13 R29 R5 0 R2
D6 R14 COM1 5 R14 R30 R4 9 R1
D7 R15 COM1 6 R15 R31 R4 8 R0
D0 R16 COM1 7 R16 R32 R4 7 R 63
D1 R17 COM1 8 R17 R33 R4 6 R 62
D2 R18 COM1 9 R18 R34 R4 5 R 61
D3 R19 COM2 0 R19 R35 R4 4 R 60
0010 Page 2
D4 R20 COM2 1 R20 R36 R4 3 R 59
D5 R21 COM2 2 R21 R37 R4 2 R 58
D6 R22 COM2 3 R22 R38 R4 1 R 57
D7 R23 COM2 4 R23 R39 R4 0 R 56
D0 R24 COM2 5 R24 R40 R3 9 R 55
D1 R25 COM2 6 R25 R41 R3 8 R 54
D2 R26 COM2 7 R26 R42 R3 7 R 53
D3 R27 COM2 8 R27 R43 R3 6 R 52
0011 Page 3
D4 R28 COM2 9 R28 R44 R3 5 R 51
D5 R29 COM3 0 R29 R45 R3 4 R 50
D6 R30 COM3 1 R30 R46 R3 3 R 49
D7 R31 COM3 2 R31 R47 R3 2 R 48
D0 R32 COM3 3 R32 R48 R3 1 R 47
D1 R33 COM3 4 R33 R49 R3 0 R 46
D2 R34 COM3 5 R34 R50 R2 9 R 45
D3 R35 COM3 6 R35 R51 R2 8 R 44
0100 Page 4
D4 R36 COM3 7 R36 R52 R2 7 R 43
D5 R37 COM3 8 R37 R53 R2 6 R 42
D6 R38 COM3 9 R38 R54 R2 5 R 41
D7 R39 COM4 0 R39 R55 R2 4 R 40
D0 R40 COM4 1 R40 R56 R2 3 R 39
D1 R41 COM4 2 R41 R57 R2 2 R 38
D2 R42 COM4 3 R42 R58 R2 1 R 37
0101 D3 R43 COM4 4 R43 R59 R2 0 R 36
Page 5
D4 R44 COM4 5 R44 R60 R1 9 R 35
D5 R45 COM4 6 R45 R61 R1 8 R 34
D6 R46 COM4 7 R46 R62 R1 7 R 33
D7 R47 COM4 8 R47 R63 R1 6 R 32
D0 R48 COM4 9 R48 R0 R1 5 R 31
D1 R49 COM5 0 R49 R1 R1 4 R 30
D2 R50 COM5 1 R50 R2 R1 3 R 29
D3 R51 COM5 2 R51 R3 R1 2 R 28
0110 Page 6
D4 R52 COM5 3 R52 R4 R1 1 R 27
D5 R53 COM5 4 R53 R5 R1 0 R 26
D6 R54 COM5 5 R54 R6 R9 R 25
D7 R55 COM5 6 R55 R7 R8 R 24
D0 R56 COM5 7 R56 R8 R7 R 23
D1 R57 COM5 8 R57 R9 R6 R 22
D2 R58 COM5 9 R58 R10 R5 R 21
0111 D3 R59 COM6 0 R59 R11 R4 R 20
Page 7
D4 R60 COM6 1 R60 R12 R3 R 19
D5 R61 COM6 2 R61 R13 R2 R 18
D6 R62 COM6 3 R62 R14 R1 R 17
D7 R63 COM6 4 R63 R15 R0 R 16
1000 D0 R64 Page 8 CIC R64 R64 R6 4 R 64
SEG129
SEG130
SEG131
SEG132
SEG128
MX=0
SEG1
SEG2
SEG3
SEG4

SEG5
SEG6
SEG7
SEG8
SEG131
SEG130
SEG129

SEG125
SEG132

SEG128
SEG127
SEG126
MX=1

SEG1
SEG5
SEG4
SEG3
SEG2

Example for memory mapping: let MX = 0, MY = 0, SL = 0, according to the data shown in the above table:
⇒ Page 0 SEG 1 (D7-D0) : 0001 1111b
⇒ Page 0 SEG 2 (D7-D0) : 1100 1100b

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

RESET & POWER MANAGEMENT

depending on the time required for VDD to stabilize, and then
TYPES OF RESET trigger the System Reset.
UC1609c has two different types of Reset:
System Reset can also be activated by connecting the RST
Power-ON-Reset and System-Reset. pin to ground.
Power-ON-Reset is performed right after VDD is connected to In the following discussions, Reset means System Reset.
power. Power-On-Reset will first wait for about ~5mS,

The differences between pin reset and software reset are

Pin Reset Software
Procedure (Restoring to default value)
(Power On Reset) Reset
Column Address : CA[7:0]=0 V V
Page Address : PA[3:0]=0 V V
RAM Address Control : AC[2:0]=001b V V
Temp. Compensation : TC[1:0]=00b V X
Power Control : PC[2:0]=110b V X
Scroll Line : SL[5:0]=0 V X
Vbias Potentiometer : PM[7:0]=49h V X
Partial Display Control : LC[5]=0b V X
Frame Rate : LC[4:3] V X
All-Pixel-On : DC[1]=0b V X
Inverse Display : DC[0]=0b V X
Display Enable : DC[2]=0b V X
LCD Mapping Control : LC[2:1]=00b V X
Test Control V X
LCD Bias Ratio : BR[1:0]=11b V X
COM End : CEN[6:0]=63d V X
Partial Display Command V X
MTP Function Control V X

RESET STATUS
When UC1609c enters RESET sequence: For each mode, the related statuses are as below:

• Operation mode will be “Reset” Mode Reset Sleep Normal

OM 00 10 11
• All control registers are reset to default values. Refer to
Control Registers for details of their default values. Host Interface Active Active Active
Clock OFF OFF ON
OPERATION MODES LCD Drivers OFF OFF ON
UC1609c has three operating modes (OM): Charge Pump OFF OFF ON
Reset, Sleep, Normal. Draining Circuit ON ON OFF

Table 4: Operating Modes

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

Both Reset mode and Sleep mode drain the charges stored in
CHANGING OPERATION MODE
the external capacitors CB0, CB1, and CL. When entering
In addition to Power-ON-Reset, two commands will initiate Reset mode or Sleep mode, the display drivers will be
OM transitions: disabled.
Set Display Enable, and System Reset.
The difference between Sleep mode and Reset mode is that
When DC[2] is modified by Set Display Enable, OM will be Reset mode clears all control registers and restores them to
updated automatically. There is no other action required to default values, while Sleep mode retains all the control
enter Sleep mode. registers values set by the user.
OM changes are synchronized with the edges of UC1609c’ It is recommended to use Sleep Mode for Display OFF
internal clock. To ensure consistent system states, wait at operations as UC1609c consumes very little energy in Sleep
least 10µS after issuing the Set Display Enable mode (typically under 5µA).
command or triggering System Reset.
EXITING SLEEP MODE
Action Mode OM
UC1609c contains internal logic to check whether VLCD and
RST_ pin pulled “L” VD are ready before releasing COM and SEG drivers from
Reset 00
Power ON reset their idle states. When exiting Sleep or Reset mode, COM
Set Driver Enable to “0” Sleep 10 and SEG drivers will not be activated until UC1609c internal
Set Driver Enable to “1” Normal 11 voltage sources are restored to their proper values.
Table 5: OM changes

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

POWER-UP SEQUENCE

Turn ON the Power

Wait  3 mS : After each power-up, a Pin Reset,
which is set in 3mS, is required.

Wait  3mS
Wait
3 uS :

Set RST Low

Wait
3uS

Set RST High

Wait
5mS

If VDD and VDD2/3 are turned ON separately,

MTP-Read sample code each one needs to be followed by a RST in 3mS.
(if using MTP function)

Wait
5mS : The system program is required

Set LCD Bias Ratio (BR) to wait for only 5mS before starting to issue
Set Potential Meter (PM) commands to UC1609c. No additional waits
are required thereafter.

Set External Pump

(if using external pump)

Set Display Enable (AFH)

External Power ON
(if using external pump)

FIGURE 11: Reference Power-Up Sequence

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

There’s no delay needed while turning ON VDD and VDD2/3, and either one can be turned ON first.

Either VDD or VDD2/3

may be turned on first.
VDD2/3 ≥ 2.5V
VDD ≥ 1.8V
TWait > 10mS
VDD < 0.1V VDD2/3 ≥ VDD

Tf < 10 mS 10µS < T1< 10 mS

Figure 12: Power Off-On Sequence

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

Power-Down Sequence
ENTER/EXIT SLEEP MODE SEQUENCE
UC1609c enters Sleep mode from Display mode by issuing To prevent the charge stored in capacitor CL causing
Set Display OFF command. To exit Sleep mode, Set Display abnormal residue horizontal line on display when VDD is
ON. switched off, use Reset mode to enable the built-in charge
draining circuit to discharge these external capacitors.
When internal VLCD is not used, UC1609c will NOT drain VLCD
Display Mode during RESET. System designers need to make sure external
VLCD source is properly drained off before turning off VDD.

Set Display OFF Set RST Low

Sleep Mode
Wait
3uS

Set Display ON

Set RST High

Display Mode

Figure 13 : Enter/Exit Sleep Mode Sequence Turn OFF the power

FIGURE 14: Reference Power-Down Sequence

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

SAMPLE COMMAND SEQUENCES FOR POWER MANAGEMENT

The following tables are examples of command sequence for sections of the datasheet and find out what the best
power-up, power-down and display ON/OFF operations. parameters and control sequences are for their specific
These are only to demonstrate some “typical, generic” design needs.
scenarios. Designers are encouraged to study related

Type Required: These items are required

Customized: These items are not necessary if customer parameters are the same as default
Advanced: We recommend new users to skip these commands and use default values.
Optional: These commands depend on what users want to do.
C/D The type of the interface cycle. It can be either Command (0) or Data (1)
W/R The direction of data flow of the cycle. It can be either Write (0) or Read (1).

POWER-UP
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Chip action Comments
R Turn on VDD and VDD2/3 Wait until VDD, VDD2/3 are stable
R Wait  3 mS
R Set RST pin Low Wait 3uS after RST is Low
R Set RST pin High Wait 5mS after RST is High
C 0 0 1 1 1 1 0 1 0 0 Set V MTP1 Potentiometer Set MTP VLCD
C 0 0 1 0 0 0 0 0 1 1 MTP2: 83h (6.4V)
C 0 0 1 1 1 1 0 1 1 1 Set MTP Read Timer Set MTP Timer
C 0 0 0 0 0 0 0 0 1 1 MTP5: 03h (10mS)
C 0 0 1 1 1 1 1 0 0 1 Set MTP Write Mask Set MTP Bit Mask
Ex: To read MTPM[5:0],
C 0 0 0 0 1 1 1 1 1 1 MTPM1
set the value to 00111111b
C 0 0 1 1 1 1 1 0 0 0 Set MTP Control Set MTPC[3]=1
C 0 0 - - 0 1 1 0 0 1 Set MTPC[2:0]=010
C Wait 150 mS
C 0 0 0 0 1 0 0 1 # # Set Temp. Compensation Set up LCD format specific
R 0 0 1 1 0 0 0 # # # Set LCD Mapping Control parameters, MX, MY, etc.
A 0 0 1 0 1 0 0 0 0 # Set Frame Rate Fine tune for power, flicker, contrast.
R 0 0 1 1 1 0 1 0 # # Set LCD Bias Ratio
0 0 1 0 0 0 0 0 0 1 LCD specific operating voltage setting
R Set VBIAS Potentiometer
0 0 # # # # # # # #
0 0 1 1 1 1 1 0 0 0
C Set MTP function Set MTP use & MTP read
0 0 0 0 0 1 1 0 0 1
C Wait  50 mS
1 0 # # # # # # # #
. . . . . . . . . .
O Write display RAM Set up display image
. . . . . . . . . .
1 0 # # # # # # # #
R 0 0 1 0 1 0 1 1 1 1 Set Display Enable
Note: Issue the commands in blue color only when using MTP functions.

POWER-DOWN
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Chip action Comments
R Set RST pin Low Wait 3 uS after RST is Low
R Set RST pin High
R Draining capacitor Wait ~3mS before VDD OFF

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

DISPLAY-OFF
Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Chip action Comments
R 0 0 1 0 1 0 1 1 1 0 Set Display Disable
C 1 0 # # # # # # # # Write display RAM Set up display image (Image update
. . . . . . . . . . is optional. Data in the RAM is
. . . . . . . . . . retained through the SLEEP state.)
1 0 # # # # # # # #
R 0 0 1 0 1 0 1 1 1 1 Set Display Enable

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

MULTI-TIME PROGRAM (MTP) NV MEMORY

OVERVIEW As illustrated above, the {MS, WS} will go through a
{0,0}{1,0}{1,1}{0,1} transition. When the {MS, WS}={0,1}
MTP feature is available for UC1609c such that LCM makers state is reached, it means the LCM is ready to be turned on.
can record an PM offset value in non-volatile memory cells,
which can then be used to adjust the effective VLCD value, in Although user can use Read Status command in a polling
order to achieve high level of consistency for LCM contrast loop to make sure {MS, WS}={0, 1} before proceeding with
across all shipments. the normal operations, however, it may be simpler to just
To accomplish this purpose, three operations are supported issue Set Display Enable command every 0.5~2 second,
by UC1609c: repeatedly, together with other LCM optimization settings,
such as BR, CEN, TC, etc.
MTP-Erase, MTP-Program, MTP-Read.
The above “Periodical re-initializing” approach is also an
MTP-Program requires an external power source supplied to effective safeguard against accidental display off events such
TST4 pin. MTP allows to program at least 10 times and as
should be performed only by the LCM makers.
• ESD strikes
MTP-Read is facilitated by the internal DC-DC converter built-
• Mechanical shocks causing LCM connector to
in on UC1609c, no external power source is required, and it is
malfunction temporarily
performed automatically after hardware RESET (power-ON
and pin RESET). HARDWARE VS. SOFTWARE RESET

OPERATION FOR THE SYSTEM USERS The auto-MTP-READ is only performed for hardware RESET
(power-ON and RST pin), but not for software RESET
For the MTP version of UC1609c, the content of the NV command. This enables the ICs to turn on display faster
memory will be read automatically after the power-on and without the delay caused by MTP-READ.
hardware pin RESET. There is no user intervention or
external power source required. When set up properly, the It is recommended to use software RESET for normal
VLCD will be fine tuned to achieve high level of consistency for operation control purpose and hardware RESET only during
the LCM contrast. the event of power up and power down.

The MTP-READ is a relatively slow process and the time OPERATION FOR THE LCM MAKERS
required can vary quite a bit. For a successful MTP-READ
Always ERASE the MTP NV memory cells, before starting the
operation, the MS and WS bits in the Read Status commands
Write process.
will exhibit the following waveforms.

MTP-read Sample Code

RST
150mS

MS

WS

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

MTP OPERATION FOR LCM MAKERS

1. High voltage supply and timer setting
In MTP Program operation, two different high voltages are No external power source is required for MTP Erase and
needed. In chip design, one high voltage is generated by Read operation. For these MTP operations, TST4 should be
internal charge pump (VLCD), the other high voltage must be open, or connected to VDD3.
input from TST4 by external voltage source.
VLCD TST4 (external input)
VLCD value is controlled by register MTP3 and MTP2. The
default values of these two registers are appropriate for most Program MTP3 : FFh (12V) 10V (1mA per bit)
applications.
Erase MTP3 : FFh (12V) Floating or VDD3
External TST4 power source is required for MTP Program
operation. MTP Programming speed depends on the TST4 Read MTP2 : 83h (6.4V) Floating or VDD3
voltage. Considering the ITO trace resistance in COG
Note: Do Erase before Program and program one bit at a
modules, it is recommended to program the MTP cells one at
time.
a time, so that the required 10V at TST4 can be maintained
with proper consistency.

2. Read MTP status bits

With normal Get Status method (CD=0, W/R=1), MTP operation will be ended with WS=1. If it failed, last operation
operation status can be monitored in the real time. There are will be automatically retried two more times. If it fails 3 times,
3 status bits (WS, MD, MS) in status register. MTP control WS will be set to 0 and the operation is aborted. MD is MTP
circuit will read to verify if the operation (program, erase) ID, which is either 1 for MTP IC. No transition.
success or not. If the operation succeeded, and current

Program: 10 V

TST4
Program / Erase
Erase: VDD3 Read to verify
VLCD=12V
VLCD=6.4V

VLCD
May repeat 3 times
MTP
Commands

MD

MS

WS

MTP status bits, TST4 & VLCD Waveform

3. MTP Cell Value Usage

There are 6 MTP cell bits. They are divided into two groups for different purpose.
MTP[5:0] : VLCD Trim
When PMO[5]=1: PM with trim = PM – PMO[4:0]
When PMO[5]=0: PM with trim = PM + PMO[4:0]

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ULTRACHIP UC1609C_A1.0
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MTP COMMAND SEQUENCE SAMPLE CODES

The following tables are examples of command sequence for MTP operations (Erase, Program, and Read) and Set Display
MTP Program and Erase operations. These are only to ON is mutual exclusive. There is no harm done to the IC or
demonstrate some “typical, generic” scenarios. Designers are the LCM if this is violated. However, the violating commands
encouraged to study related sections of the datasheet and will be ignored.
find out what the best parameters and control sequences are
for their specific design needs.

Type Required: These items are required

Customized: These items are not necessary if customer parameters are the same as default
Advanced: We recommend new users to skip these commands and use default values.
Optional: These commands depend on what users want to do.
C/D The type of the interface cycle. It can be either Command (0) or Data (1)
W/R The direction of dataflow of the cycle. It can be either Write (0) or Read (1).
MTP Program Sample Code

Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Chip Action Comments

R Set RST pin Low Wait 3uS after RST is Low
R Set RST pin High Wait 5mS
R 0 0 1 0 1 0 0 0 1 1 Set Line Rate Set LC[4:3]=11b
R 0 0 1 1 1 1 0 1 0 0 Set VMTP1 Potentiometer Set MTP VLCD
R 0 0 1 0 0 0 0 0 1 1 MTP2: 83h (6.4V)
R 0 0 1 1 1 1 0 1 0 1 Set VMTP2 Potentiometer Set MTP VLCD
R 0 0 1 1 1 1 1 1 1 1 MTP3: FFh (12V)
R 0 0 1 1 1 1 0 1 1 0 Set MTP Write Timer Set MTP Timer
R 0 0 0 1 0 0 1 1 0 1 MTP4: 4Dh (200mS)
R 0 0 1 1 1 1 0 1 1 1 Set MTP Read Timer Set MTP Timer
R 0 0 0 0 0 0 0 0 1 1 MTP5: 03h (10mS)
R 0 0 1 1 1 1 1 0 0 1 Set MTP Write Mask Set MTP Bit Mask
Ex: To program MTPM[0] to be 1,
C 0 0 0 0 0 0 0 0 0 1 MTPM
set the value to 00000001b *
Apply TST4 voltage
R
Program: 10V
R 0 0 1 1 1 1 1 0 0 0 Set MTP Control Set MTPC[3]=1
R 0 0 - - 0 0 1 0 1 1 Set MTPC[2:0]=011
R 0 1 - - - - - WS - MS Get Status & PM Check MTP Status until MS=0, WS=1
R Remove TST4 voltage
R VDD=0V Power OFF
* It is recommended that users program one bit at a time.

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ULTRACHIP UC1609C_A1.0
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MTP Erase Sample Code

Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Chip action Comments

R Set RST pin Low Wait 3uS after RST is Low
R Set RST pin High Wait 5mS
R 0 0 1 0 1 0 0 0 1 1 Set Line Rate Set LC[4:3]=11b
R 0 0 1 1 1 1 0 1 0 0 Set VMTP1 Potentiometer Set MTP VLCD
R 0 0 1 0 0 0 0 0 1 1 MTP2: 83h (6.4V)
R 0 0 1 1 1 1 0 1 0 1 Set VMTP2 Potentiometer Set MTP VLCD
R 0 0 1 1 1 1 1 1 1 1 MTP3: FFh (12V)
R 0 0 1 1 1 1 0 1 1 0 Set MTP Write Timer Set MTP Timer
R 0 0 0 1 0 0 1 1 0 1 MTP4: 4Dh (200mS)
R 0 0 1 1 1 1 0 1 1 1 Set MTP Read Timer Set MTP Timer
R 0 0 0 0 0 0 0 0 1 1 MTP5: 03h (10mS)
R 0 0 1 1 1 1 1 0 0 1 Set MTP Write Mask Set MTP Bit Mask
Ex: To erase MTPM[3:0],
C 0 0 0 0 0 0 1 1 1 1 MTPM1
set the value to 00001111b *
R 0 0 1 1 1 1 1 0 0 0 Set MTP Control Set MTPC[3]=1
R 0 0 - - 0 0 1 0 1 0 Set MTPC[2:0]=010
Check MTP Status
R 0 1 - - - - - WS - MS Get Status & PM
until MS=0 WS=1
R VDD=0V Power OFF
* It is recommended that users clear first all the bits to be programmed.

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ULTRACHIP UC1609C_A1.0
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MTP Read Sample Code

Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Chip action Comments

R Set RST pin Low Wait 3uS after RST is Low
R Set RST pin High Wait 5mS
R 0 0 1 1 1 1 0 1 0 0 Set VMTP1 Potentiometer Set MTP VLCD
R 0 0 1 0 0 0 0 0 1 1 MTP2: 83h (6.4V)
R 0 0 1 1 1 1 0 1 1 1 Set MTP Read Timer Set MTP Timer
R 0 0 0 0 0 0 0 0 1 1 MTP5: 03h (10mS)
R 0 0 1 1 1 1 1 0 0 1 Set MTP Write Mask Set MTP Bit Mask
Ex: To read MTPM[5:0],
C 0 0 0 0 1 1 1 1 1 1 MTPM1
set the value to 00111111b *
R 0 0 1 1 1 1 1 0 0 0 Set MTP Control Set MTPC[3]=1
R 0 0 - - 0 1 1 0 0 1 Set MTPC[2:0]=010
R Wait 150mS
Check MTP Status
R 0 1 - - - - - WS - MS Get Status & PM
until MS=0, WS=1
R (other initialization settings
for starting the IC)
* It is recommended that users read first all the bits to be programmed.

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

ESD CONSIDERATION
UC1600 series products usually are provided in bare die format to customers. This makes the product particularly sensitive to
ESD damage during handling and manufacturing process. It is, therefore, highly recommended that LCM makers strictly follow
the “JESD 625-A Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices” when manufacturing LCM.
The following pins in UC1609c require special “ESD Sensitivity” consideration in particular:

Test Mode Machine Mode Human Body Mode

Pins VDD VSS VDD VSS
LCD Driver 200V 200V 2.0KV 2.0KV
LCM Digital Interface 300V 300V 3.0KV 3.0KV
TST1/2/4 300V 300V 3.0KV 3.0KV
CB pins 300V 300V 2.0KV 2.5KV
LCM HV Interface
VLCDIN 250V 250V 2.0KV 2.5KV
VLCDOUT 300v 300V 3.0KV 3.0KV
PWR/GND – 300V – 3.0KV

According to UltraChip’s Mass Production experiences, the ESD tolerance conditions are believed to be very stable and can
produce high yield in multiple customer sites. However, special care is still required during handling and manufacturing process to
avoid unnecessary yield loss due to ESD damages.

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ULTRACHIP UC1609C_A1.0
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ABSOLUTE MAXIMUM RATINGS

In accordance with IEC134 – notes 1, 2 and 3.

Symbol Parameter Min. Max. Unit

VDD Logic Supply voltage -0.3 +4.0 V
VDD2 LCD Generator Supply voltage -0.3 +4.0 V
VDD3 Analog Circuit Supply voltage -0.3 +4.0 V
VDD2/3-VDD Voltage difference between VDD and VDD2/3 -- 1.2 V
VLCD LCD Generated voltage -0.3 +13.2 V
VIN / VOUT Any input/output -0.4 VDD + 0.3 V
o
TOPR Operating temperature range -30 +85 C
o
TSTR Storage temperature -55 +125 C

Notes
1. VDD is based on VSS = 0V
2. Stress values listed above may cause permanent damages to the device.

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ULTRACHIP UC1609C_A1.0
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SPECIFICATIONS
DC CHARACTERISTICS
Symbol Parameter Conditions Min. Typ. Max. Unit
VDD Supply for digital circuit 1.7 1.8~3.3 3.6 V
VDD2/3 Supply for bias & pump 2.6 2.7~3.3 3.6 V
O
VLCD Charge pump output VDD2/3
2.6V, 25 C 4.8~11.5 11.5 V
O
VD LCD data voltage VDD2/3
2.6V, 25 C 0.80 1.32 V
VIL Input logic LOW 0.1VDD V
VIH Input logic HIGH 0.9VDD V
VOL Output logic LOW 0.2VDD V
VOH Output logic HIGH 0.8VDD V
IIL Input leakage current 1.5 µA
o
ISB Standby current VDD = VDD2/3 = 3.3V, Temp = 85 C 50 µA
CIN Input capacitance 5 10 PF
COUT Output capacitance 5 10 PF
R0(SEG) SEG output impedance VLCD = 9V 2200 2800 Ω
R0(COM) COM output impedance VLCD = 9V 2200 2800 Ω
FFR Average Frame Rate LC[4:3] = 01b -10% 95 +10% Hz

POWER CONSUMPTION
VDD = 2.7V, Bias Ratio = 11b, PM = 73,
VLCD = 8.54V Frame Rate = 01b, PMO = 00H,
Mux Rate = 65, Bus mode = 6800, CB0 / CB1 = 2.2µF,
o
Temperature = 25 C, CL = 330nF, All outputs are open circuit.
Display Pattern Conditions Typ. Max.
All-ON Bus = idle 196 392
All-OFF Bus = idle 197 394
2-pixel checker Bus = idle 222 444
- Bus = idle (standby current) - 5

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ULTRACHIP UC1609C_A1.0
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AC CHARACTERISTICS
錯誤!
錯誤
CD
tAS80 tAH80
CS0
CS1
tCSSA80 tCY80 tCSH80
tPWR80, tPWW80 tHPW80
WR0
WR1
tr tDS80 tf tDH80
Write
D[7:0]
tACC80 tOD80
Read
D[7:0]

FIGURE 15: Parallel Bus Timing Characteristics (for 8080 MCU)

Symbol Signal Description Condition Min. Max. Unit

o
(2.5V  VDD  3.6V, Ta= –30 to +85 C) (Read / Write)
tAS80 Address setup time 5
CD – nS
tAH80 Address hold time 10
tCSSA80 Chip select setup time 5
CS1, CS0 – nS
tCSH80 Chip select hold time 5
tCY80 System Cycle time 170 / 110
tPWR80 / tPWW80 WR0, WR1 Pulse width 70 / 40 – nS
tHPW80 High pulse width 70 / 40
tDS80 D7~D0 Data setup time 35
– nS
tDH80 (Write) Data hold time 5
tACC80 D7~D0 Read access time – 70
CL = 100pF nS
tOD80 (Read) Output disable time – 40
o
(1.7V  VDD < 2.5V, Ta= –30 to +85 C) (Read / Write)
tAS80 Address setup time 5
CD – nS
tAH80 Address hold time 10
tCSSA80 Chip select setup time 5
CS1, CS0 – nS
tCSH80 Chip select hold time 5
tCY80 System cycle time 270 / 190
tPWR80 / tPWW80 WR0, WR1 Pulse width 120 / 80 – nS
tHPW80 High pulse width 120 / 80
tDS80 D7~D0 Data setup time 60
– nS
tDH80 (Write) Data hold time 5
tACC80 D7~D0 Read access time – 120
CL = 100pF nS
tOD80 (Read) Output disable time – 80
Note: tr (rising time), tf (falling time) :  15nS

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

CD
tAS68 tAH68
CS0
CS1
tCSSA68 tCY68 tCSH68
tPWR68, tPWW68 tHPW68

WR1 tr tf
tDS68 tDH68
Write
D[7:0]
tACC68 tOD68
Read
D[7:0]

FIGURE 16: Parallel Bus Timing Characteristics (for 6800 MCU)

Symbol Signal Description Condition Min. Max. Unit

o
(2.5V  VDD  3.6V, Ta= –30 to +85 C) (Read / Write)
tAS68 Address setup time 5
CD – nS
tAH68 Address hold time 10
tCSSA68 Chip select setup time 5
CS1, CS0 – nS
tCSH68 Chip select hold time 5
tCY68 System cycle time 170 / 110
tPWR68 / tPWW68 WR1 Pulse width 70 / 40 – nS
tHPW68 High pulse width 70 / 40
tDS68 D7~D0 Data setup time 35
– nS
tDH68 (Write) Data hold time 5
tACC68 D7~D0 Read access time – 70
CL = 100pF nS
tOD68 (Read) Output disable time – 40
o
(1.7V  VDD < 2.5V, Ta= –30 to +85 C) (Read / Write)
tAS68 Address setup time 5
CD – nS
tAH68 Address hold time 10
tCSSA68 Chip select setup time 5
CS1, CS0 – nS
tCSH68 Chip select hold time 5
tCY68 System cycle time 270 / 190
tPWR68 / tPWW68 WR1 Pulse width 120 / 80 – nS
tHPW68 High pulse width 120 / 80
tDS68 D7~D0 Data setup time 60
– nS
tDH68 (Write) Data hold time 5
tACC68 D7~D0 Read access time – 120
CL = 100pF nS
tOD68 (Read) Output disable time – 80
Note: tr (Rising time), tf (falling time) :  15nS

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

CD
tASS8 tAHS8
CS0
CS1
tCSSAS tCYS8 tCSHS8
tLPWS8 tHPWS8

SCK

tDSS8 tDHS8

SDA
Write
tACCS8 tODS8
SDA
Read

FIGURE 17: Serial Bus Timing Characteristics (for S8)

Symbol Signal Description Condition Min. Max. Unit

o
(2.5V  VDD  3.6V, Ta= –30 to +85 C) (Read / Write)
tASS8 Address setup time 5
CD – nS
tAHS8 Address hold time 10
tCSSAS8 Chip select setup time 10
CS1, CS0 – nS
tCSHS8 Chip select hold time 10
tCYS8 System Cycle time 190 / 80
tLPWS8 SCK Low pulse width 80 / 25 – nS
tHPWS8 High pulse width 80 / 25
tDSS8 SDA Data setup time 25
– nS
tDHS8 (Write) Data hold time 10
tACC8 SDA Read access time – 80
CL = 100pF nS
tOD8 (Read) Output disable time – 30
o
(1.7V  VDD < 2.5V, Ta= –30 to +85 C) (Read / Write)
tASS8 Address setup time 5
CD – nS
tAHS8 Address hold time 10
tCSSAS8 Chip select setup time 10
CS1, CS0 – nS
tCSHS8 Chip select hold time 10
tCYS8 System Cycle time 230 / 110 – nS
tLPWS8 SCK Low pulse width 100 / 40 – nS
tHPWS8 High pulse width 100 / 40 – nS
tDSS8 SDA Data setup time 24
– nS
tDHS8 (Write) Data hold time 10
tACC8 SDA Read access time – 100
CL = 100pF nS
tOD8 (Read) Output disable time – 60
Note: tr (Rising time), tf (falling time) :  15nS

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

CS0
CS1

tCSSAS9 tCYS9 tCSHS9

tLPWS9 tHPWS9
SCK

tDSS9 tDHS9
SDA
Write
tACCS9 tODS9
SDA
Read

FIGURE 18: Serial Bus Timing Characteristics (for S9)

Symbol Signal Description Condition Min. Max. Unit

o
(2.5V  VDD  3.6V, Ta= –30 to +85 C) (Read / Write)
tCSSAS9 Chip select setup time 10
CS1, CS0 – nS
tCSHS9 Chip select hold time 10
tCYS9 System cycle time 190 / 80
tLPWS9 SCK Low pulse width 80 / 25 – nS
tHPWS9 High pulse width 80 / 25
tDSS9 SDA Data setup time 25
– nS
tDHS9 (Write) Data hold time 10
tACC9 SDA Read access time – 80
CL = 100pF nS
tOD9 (Read) Output disable time – 30
o
(1.7V  VDD < 2.5V, Ta= –30 to +85 C) (Read / Write)
tCSSAS9 10
CS1, CS0 Chip select setup time – nS
tCSHS9 10
tCYS9 System cycle time 230 / 110
tLPWS9 SCK Low pulse width 100 / 40 – nS
tHPWS9 High pulse width 100 / 40
tDSS9 SDA Data setup time 24
– nS
tDHS9 (Write) Data hold time 15
tACC9 SDA Read access time – 100
CL = 100pF nS
tOD9 (Read) Output disable time – 60
Note: tr (Rising time), tf (falling time) :  15nS

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ULTRACHIP UC1609C_A1.0
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tCYI2C
START tHPWI2C tLPWI2C STOP

SCK

tSSTAI2C tHSTAI2C tSDATI2C tHDATI2C tSSTOI2C

tBUF
SDA

2
FIGURE 19: Serial bus timing characteristics (for I C)

Symbol Signal Description Condition Min. Max. Unit

o
(2.5V  VDD  3.6V, Ta= –30 to +85 C) (Read / Write)
tCYI2C SCK cycle time 610 / 305
tHPWI2C SCK High pulse width 290 / 110 – nS
tLPWI2C Low pulse width 290 / 165
tSSTAI2C Setup time – START 28
tHSTAI2C Hold time – START 55
SCK
tSDAI2C Setup time – Data 40 – nS
SDA
tHDAI2C Hold time – Data 11
tSSTOI2C Setup time – STOP 28
Bus Free time between
tBUF SDA 165 – nS
STOP and START
o
(1.7V  VDD < 2.5V, Ta= –30 to +85 C) (Read / Write)
tCYI2C SCK cycle time 780 / 360
tHPWI2C SCK High pulse width 375 / 130 – nS
tLPWI2C Low pulse width 375 / 200
tSSTAI2C Setup time – START 33
tHSTAI2C Hold time – START 80
SCK
tSDAI2C Setup time – Data 80 – nS
SDA
tHDAI2C Hold time – Data 11
tSSTOI2C Setup time – STOP 33
Bus Free Time between
tBUF SDA 220 – nS
STOP and START
Note: tr (Rising time), tf (falling time) :  15nS

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

Resetting…

FIGURE 20: Reset Characteristics

o
(1.7V  VDD  3.6V, Ta= –30 to +85 C)

Symbol Signal Description Condition Min. Max. Unit

tRW RST Reset low pulse width 3 – µS
tR RST, Internal Status Reset to Internal Status pulse delay 6 – mS

Note:
For each mode, the signal’s rising and falling times (tr, tf) are stipulated to be equal to or less than 15nS each.

tr 15nS tf 15nS

80%

20%

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

PHYSICAL DIMENSIONS

Circuit / Bump View:

SEG192
SEG191
SEG190
COM63

COM64
COMS

COMS
COM5
COM3
COM1

COM2
COM4
COM6
SEG3
SEG2
SEG1
:
:
:

:
:
:
:
:
:
:

:
:
:
Y

(0, 0) X

Die Size: (7500 µM ± 40 µM) x (667 µM ± 40 µM) Bump Size: 15.6 µM x 100 µM
Die Thickness: 400 µM ± 20 µM Bump Pitch: 27.6 µM
2
Die TTV: (DMAX – DMIN) within die  2 µM Shear Force: >5 g /µM
2
Hardness: 90 Hv ± 25 Hv Bump Area: 1560 µM
Bump Height: 10 µM ± 3 µM Coordinate origin: Chip center
(HMAX – HMIN) within die  2 µM Pad reference: Pad center

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

ALIGNMENT MARK INFORMATION

X
(0, 0)

D-Left D-Right
Mark Mark

Shape of the alignment mark:

Remark:
The cross mark itself is symmetric
both horizontally and vertically.

Coordinates:

D-Left Mark (+) D-Right Mark (+)

Point X Y X Y
1 -3486.5 -243 3449.4 -243
2 -3466.5 -293 3469.4 -293
3 -3501.5 -258 3434.4 -258
4 -3451.5 -278 3484.4 -278
C -3476.5 -268 3459.4 -268

Top Metal and Passivation:

Remark:
Alignment marks are on Metal3
and under Passivation

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ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

PAD COORDINATES
# PAD X Y W H # PAD X Y W H
1 DUMMY2 -3686 -276.5 50 45 50 VDD -125.15 -276.5 50 45
2 DUMMY5 -3621 -276.5 50 45 51 VDD -60.15 -276.5 50 45
3 DUMMY6 -3556 -276.5 50 45 52 VDD 18.7 -276.5 50 45
4 DATA_pad<7> -3303.55 -276.5 50 45 53 VDD2 105.4 -276.5 50 45
5 VDDX -3238.55 -276.5 50 45 54 VDD2 184.25 -276.5 50 45
6 DATA_pad<6> -3173.55 -276.5 50 45 55 VDD2 249.25 -276.5 50 45
7 DATA_pad<5> -3108.55 -276.5 50 45 56 VDD2 314.25 -276.5 50 45
8 DATA_pad<4> -3021.85 -276.5 50 45 57 VDD2 379.25 -276.5 50 45
9 DATA_pad<3> -2956.85 -276.5 50 45 58 VDD3 444.25 -276.5 50 45
10 DATA_pad<2> -2870.15 -276.5 50 45 59 VDD3 509.25 -276.5 50 45
11 DATA_pad<1> -2805.15 -276.5 50 45 60 VDD3 574.25 -276.5 50 45
12 DATA_pad<0> -2718.45 -276.5 50 45 61 VDD3 639.25 -276.5 50 45
13 RSTB_pad -2644.65 -276.5 50 45 62 VDD3 712.65 -276.5 50 45
14 WR_pad<0> -2579.65 -276.5 50 45 63 TST4_pad 893 -276.5 50 45
15 VDDX -2514.65 -276.5 50 45 64 TST4_pad 958 -276.5 50 45
16 WR_pad<1> -2449.65 -276.5 50 45 65 TST4_pad 1034 -276.5 50 45
17 CD_pad -2384.65 -276.5 50 45 66 TST4_pad 1099 -276.5 50 45
18 CS_pad<0> -2319.65 -276.5 50 45 67 TST2_pad 1164 -276.5 50 45
19 VDDX -2254.65 -276.5 50 45 68 TST2_pad 1265.45 -276.5 50 45
20 CS_pad<1> -2189.65 -276.5 50 45 69 VBP_pad<0> 1385.35 -276.5 50 45
21 BM_pad<0> -2117.85 -276.5 50 45 70 VBP_pad<0> 1450.35 -276.5 50 45
22 VDDX -2052.85 -276.5 50 45 71 VBP_pad<0> 1525.5 -276.5 50 45
23 BM_pad<1> -1987.85 -276.5 50 45 72 VBP_pad<0> 1590.5 -276.5 50 45
24 ID_pad -1922.85 -276.5 50 45 73 VBP_pad<1> 1655.5 -276.5 50 45
25 VDDX -1857.85 -276.5 50 45 74 VBP_pad<1> 1720.5 -276.5 50 45
26 POR_dis_pad -1792.85 -276.5 50 45 75 VBP_pad<1> 1795.65 -276.5 50 45
27 VSS -1718.75 -276.5 50 45 76 VBP_pad<1> 1860.65 -276.5 50 45
28 VSS -1653.75 -276.5 50 45 77 VBN_pad<1> 1942.65 -276.5 50 45
29 VSS -1588.75 -276.5 50 45 78 VBN_pad<1> 2007.65 -276.5 50 45
30 VSS -1523.75 -276.5 50 45 79 VBN_pad<1> 2082.8 -276.5 50 45
31 VSS -1458.75 -276.5 50 45 80 VBN_pad<1> 2147.8 -276.5 50 45
32 VSS -1393.75 -276.5 50 45 81 VBN_pad<0> 2212.8 -276.5 50 45
33 DUMMY7 -1301.6 -276.5 50 45 82 VBN_pad<0> 2277.8 -276.5 50 45
34 DUMMY8 -1236.6 -276.5 50 45 83 VBN_pad<0> 2352.95 -276.5 50 45
35 DUMMY9 -1171.6 -276.5 50 45 84 VBN_pad<0> 2417.95 -276.5 50 45
36 VSS2 -1079.45 -276.5 50 45 85 VLCDIN_pad 2501.95 -276.5 50 45
37 VSS2 -1014.45 -276.5 50 45 86 VLCDIN_pad 2566.95 -276.5 50 45
38 VSS2 -949.45 -276.5 50 45 87 VLCDIN_pad 2663.95 -276.5 50 45
39 VSS2 -884.45 -276.5 50 45 88 VLCDIN_pad 2728.95 -276.5 50 45
40 VSS2 -819.45 -276.5 50 45 89 VLCDOUT_pad 2793.95 -276.5 50 45
41 VSS2 -754.45 -276.5 50 45 90 VLCDOUT_pad 2858.95 -276.5 50 45
42 DUMMY10 -669.8 -276.5 50 45 91 VLCDOUT_pad 2934.95 -276.5 50 45
43 DUMMY11 -604.8 -276.5 50 45 92 VLCDOUT_pad 2999.95 -276.5 50 45
44 DUMMY12 -522.3 -276.5 50 45 93 DUMMY15 3064.95 -276.5 50 45
45 DUMMY13 -457.3 -276.5 50 45 94 DUMMY16 3129.95 -276.5 50 45
46 DUMMY14 -392.3 -276.5 50 45 95 DUMMY17 3194.95 -276.5 50 45
47 VDD -320.15 -276.5 50 45 96 DUMMY18 3259.95 -276.5 50 45
48 VDD -255.15 -276.5 50 45 97 DUMMY19 3324.95 -276.5 50 45
49 VDD -190.15 -276.5 50 45 98 DUMMY20 3389.95 -276.5 50 45

59
ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

# PAD X Y W H # PAD X Y W H
99 DUMMY21 3536 -276.5 50 45 149 SEG_pad<14> 2254.4 235.5 15.6 115
100 DUMMY22 3601 -276.5 50 45 150 SEG_pad<15> 2226.8 235.5 15.6 115
101 DUMMY3 3666 -276.5 50 45 151 SEG_pad<16> 2199.2 235.5 15.6 115
102 DUMMY4 3704.2 243 15.6 100 152 SEG_pad<17> 2171.6 235.5 15.6 115
103 COMS_PAD 3676.6 243 15.6 100 153 SEG_pad<18> 2144 235.5 15.6 115
104 COM_pad<64> 3649 243 15.6 100 154 SEG_pad<19> 2116.4 235.5 15.6 115
105 COM_pad<62> 3621.4 243 15.6 100 155 SEG_pad<20> 2088.8 235.5 15.6 115
106 COM_pad<60> 3593.8 243 15.6 100 156 SEG_pad<21> 2061.2 235.5 15.6 115
107 COM_pad<58> 3566.2 243 15.6 100 157 SEG_pad<22> 2033.6 235.5 15.6 115
108 COM_pad<56> 3538.6 243 15.6 100 158 SEG_pad<23> 2006 235.5 15.6 115
109 COM_pad<54> 3511 243 15.6 100 159 SEG_pad<24> 1978.4 235.5 15.6 115
110 COM_pad<52> 3483.4 243 15.6 100 160 SEG_pad<25> 1950.8 235.5 15.6 115
111 COM_pad<50> 3455.8 243 15.6 100 161 SEG_pad<26> 1923.2 235.5 15.6 115
112 COM_pad<48> 3428.2 243 15.6 100 162 SEG_pad<27> 1895.6 235.5 15.6 115
113 COM_pad<46> 3400.6 243 15.6 100 163 SEG_pad<28> 1868 235.5 15.6 115
114 COM_pad<44> 3373 243 15.6 100 164 SEG_pad<29> 1840.4 235.5 15.6 115
115 COM_pad<42> 3345.4 243 15.6 100 165 SEG_pad<30> 1812.8 235.5 15.6 115
116 COM_pad<40> 3317.8 243 15.6 100 166 SEG_pad<31> 1785.2 235.5 15.6 115
117 COM_pad<38> 3290.2 243 15.6 100 167 SEG_pad<32> 1757.6 235.5 15.6 115
118 COM_pad<36> 3262.6 243 15.6 100 168 SEG_pad<33> 1730 235.5 15.6 115
119 COM_pad<34> 3235 243 15.6 100 169 SEG_pad<34> 1702.4 235.5 15.6 115
120 COM_pad<32> 3207.4 243 15.6 100 170 SEG_pad<35> 1674.8 235.5 15.6 115
121 COM_pad<30> 3179.8 243 15.6 100 171 SEG_pad<36> 1647.2 235.5 15.6 115
122 COM__pad<28> 3152.2 243 15.6 100 172 SEG_pad<37> 1619.6 235.5 15.6 115
123 COM_pad<26> 3124.6 243 15.6 100 173 SEG_pad<38> 1592 235.5 15.6 115
124 COM_pad<24> 3097 243 15.6 100 174 SEG_pad<39> 1564.4 235.5 15.6 115
125 COM_pad<22> 3069.4 243 15.6 100 175 SEG_pad<40> 1536.8 235.5 15.6 115
126 COM_pad<20> 3041.8 243 15.6 100 176 SEG_pad<41> 1509.2 235.5 15.6 115
127 COM_pad<18> 3014.2 243 15.6 100 177 SEG_pad<42> 1481.6 235.5 15.6 115
128 COM_pad<16> 2986.6 243 15.6 100 178 SEG_pad<43> 1454 235.5 15.6 115
129 COM_pad<14> 2959 243 15.6 100 179 SEG_pad<44> 1426.4 235.5 15.6 115
130 COM_pad<12> 2931.4 243 15.6 100 180 SEG_pad<45> 1398.8 235.5 15.6 115
131 COM_pad<10> 2903.8 243 15.6 100 181 SEG_pad<46> 1371.2 235.5 15.6 115
132 COM_pad<8> 2876.2 243 15.6 100 182 SEG_pad<47> 1343.6 235.5 15.6 115
133 COM_pad<6> 2848.6 243 15.6 100 183 SEG_pad<48> 1316 235.5 15.6 115
134 COM_pad<4> 2821 243 15.6 100 184 SEG_pad<49> 1288.4 235.5 15.6 115
135 COM_pad<2> 2793.4 243 15.6 100 185 SEG_pad<50> 1260.8 235.5 15.6 115
136 SEG_pad<1> 2613.2 235.5 15.6 115 186 SEG_pad<51> 1233.2 235.5 15.6 115
137 SEG_pad<2> 2585.6 235.5 15.6 115 187 SEG_pad<52> 1205.6 235.5 15.6 115
138 SEG_pad<3> 2558 235.5 15.6 115 188 SEG_pad<53> 1178 235.5 15.6 115
139 SEG_pad<4> 2530.4 235.5 15.6 115 189 SEG_pad<54> 1150.4 235.5 15.6 115
140 SEG_pad<5> 2502.8 235.5 15.6 115 190 SEG_pad<55> 1122.8 235.5 15.6 115
141 SEG_pad<6> 2475.2 235.5 15.6 115 191 SEG_pad<56> 1095.2 235.5 15.6 115
142 SEG_pad<7> 2447.6 235.5 15.6 115 192 SEG_pad<57> 1067.6 235.5 15.6 115
143 SEG_pad<8> 2420 235.5 15.6 115 193 SEG_pad<58> 1040 235.5 15.6 115
144 SEG_pad<9> 2392.4 235.5 15.6 115 194 SEG_pad<59> 1012.4 235.5 15.6 115
145 SEG_pad<10> 2364.8 235.5 15.6 115 195 SEG_pad<60> 984.8 235.5 15.6 115
146 SEG_pad<11> 2337.2 235.5 15.6 115 196 SEG_pad<61> 957.2 235.5 15.6 115
147 SEG_pad<12> 2309.6 235.5 15.6 115 197 SEG_pad<62> 929.6 235.5 15.6 115
148 SEG_pad<13> 2282 235.5 15.6 115 198 SEG_pad<63> 902 235.5 15.6 115

60
ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

# PAD X Y W H # PAD X Y W H
199 SEG_pad<64> 874.4 235.5 15.6 115 249 SEG_pad<114> -505.6 235.5 15.6 115
200 SEG_pad<65> 846.8 235.5 15.6 115 250 SEG_pad<115> -533.2 235.5 15.6 115
201 SEG_pad<66> 819.2 235.5 15.6 115 251 SEG_pad<116> -560.8 235.5 15.6 115
202 SEG_pad<67> 791.6 235.5 15.6 115 252 SEG_pad<117> -588.4 235.5 15.6 115
203 SEG_pad<68> 764 235.5 15.6 115 253 SEG_pad<118> -616 235.5 15.6 115
204 SEG_pad<69> 736.4 235.5 15.6 115 254 SEG_pad<119> -643.6 235.5 15.6 115
205 SEG_pad<70> 708.8 235.5 15.6 115 255 SEG_pad<120> -671.2 235.5 15.6 115
206 SEG_pad<71> 681.2 235.5 15.6 115 256 SEG_pad<121> -698.8 235.5 15.6 115
207 SEG_pad<72> 653.6 235.5 15.6 115 257 SEG_pad<122> -726.4 235.5 15.6 115
208 SEG_pad<73> 626 235.5 15.6 115 258 SEG_pad<123> -754 235.5 15.6 115
209 SEG_pad<74> 598.4 235.5 15.6 115 259 SEG_pad<124> -781.6 235.5 15.6 115
210 SEG_pad<75> 570.8 235.5 15.6 115 260 SEG_pad<125> -809.2 235.5 15.6 115
211 SEG_pad<76> 543.2 235.5 15.6 115 261 SEG_pad<126> -836.8 235.5 15.6 115
212 SEG_pad<77> 515.6 235.5 15.6 115 262 SEG_pad<127> -864.4 235.5 15.6 115
213 SEG_pad<78> 488 235.5 15.6 115 263 SEG_pad<128> -892 235.5 15.6 115
214 SEG_pad<79> 460.4 235.5 15.6 115 264 SEG_pad<129> -919.6 235.5 15.6 115
215 SEG_pad<80> 432.8 235.5 15.6 115 265 SEG_pad<130> -947.2 235.5 15.6 115
216 SEG_pad<81> 405.2 235.5 15.6 115 266 SEG_pad<131> -974.8 235.5 15.6 115
217 SEG_pad<82> 377.6 235.5 15.6 115 267 SEG_pad<132> -1002.4 235.5 15.6 115
218 SEG_pad<83> 350 235.5 15.6 115 268 SEG_pad<133> -1030 235.5 15.6 115
219 SEG_pad<84> 322.4 235.5 15.6 115 269 SEG_pad<134> -1057.6 235.5 15.6 115
220 SEG_pad<85> 294.8 235.5 15.6 115 270 SEG_pad<135> -1085.2 235.5 15.6 115
221 SEG_pad<86> 267.2 235.5 15.6 115 271 SEG_pad<136> -1112.8 235.5 15.6 115
222 SEG_pad<87> 239.6 235.5 15.6 115 272 SEG_pad<137> -1140.4 235.5 15.6 115
223 SEG_pad<88> 212 235.5 15.6 115 273 SEG_pad<138> -1168 235.5 15.6 115
224 SEG_pad<89> 184.4 235.5 15.6 115 274 SEG_pad<139> -1195.6 235.5 15.6 115
225 SEG_pad<90> 156.8 235.5 15.6 115 275 SEG_pad<140> -1223.2 235.5 15.6 115
226 SEG_pad<91> 129.2 235.5 15.6 115 276 SEG_pad<141> -1250.8 235.5 15.6 115
227 SEG_pad<92> 101.6 235.5 15.6 115 277 SEG_pad<142> -1278.4 235.5 15.6 115
228 SEG_pad<93> 74 235.5 15.6 115 278 SEG_pad<143> -1306 235.5 15.6 115
229 SEG_pad<94> 46.4 235.5 15.6 115 279 SEG_pad<144> -1333.6 235.5 15.6 115
230 SEG_pad<95> 18.8 235.5 15.6 115 280 SEG_pad<145> -1361.2 235.5 15.6 115
231 SEG_pad<96> -8.8 235.5 15.6 115 281 SEG_pad<146> -1388.8 235.5 15.6 115
232 SEG_pad<97> -36.4 235.5 15.6 115 282 SEG_pad<147> -1416.4 235.5 15.6 115
233 SEG_pad<98> -64 235.5 15.6 115 283 SEG_pad<148> -1444 235.5 15.6 115
234 SEG_pad<99> -91.6 235.5 15.6 115 284 SEG_pad<149> -1471.6 235.5 15.6 115
235 SEG_pad<100> -119.2 235.5 15.6 115 285 SEG_pad<150> -1499.2 235.5 15.6 115
236 SEG_pad<101> -146.8 235.5 15.6 115 286 SEG_pad<151> -1526.8 235.5 15.6 115
237 SEG_pad<102> -174.4 235.5 15.6 115 287 SEG_pad<152> -1554.4 235.5 15.6 115
238 SEG_pad<103> -202 235.5 15.6 115 288 SEG_pad<153> -1582 235.5 15.6 115
239 SEG_pad<104> -229.6 235.5 15.6 115 289 SEG_pad<154> -1609.6 235.5 15.6 115
240 SEG_pad<105> -257.2 235.5 15.6 115 290 SEG_pad<155> -1637.2 235.5 15.6 115
241 SEG_pad<106> -284.8 235.5 15.6 115 291 SEG_pad<156> -1664.8 235.5 15.6 115
242 SEG_pad<107> -312.4 235.5 15.6 115 292 SEG_pad<157> -1692.4 235.5 15.6 115
243 SEG_pad<108> -340 235.5 15.6 115 293 SEG_pad<158> -1720 235.5 15.6 115
244 SEG_pad<109> -367.6 235.5 15.6 115 294 SEG_pad<159> -1747.6 235.5 15.6 115
245 SEG_pad<110> -395.2 235.5 15.6 115 295 SEG_pad<160> -1775.2 235.5 15.6 115
246 SEG_pad<111> -422.8 235.5 15.6 115 296 SEG_pad<161> -1802.8 235.5 15.6 115
247 SEG_pad<112> -450.4 235.5 15.6 115 297 SEG_pad<162> -1830.4 235.5 15.6 115
248 SEG_pad<113> -478 235.5 15.6 115 298 SEG_pad<163> -1858 235.5 15.6 115

61
ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

# PAD X Y W H # PAD X Y W H
299 SEG_pad<164> -1885.6 235.5 15.6 115 332 COM_pad<7> -2904.3 243 15.6 100
300 SEG_pad<165> -1913.2 235.5 15.6 115 333 COM_pad<9> -2931.9 243 15.6 100
301 SEG_pad<166> -1940.8 235.5 15.6 115 334 COM_pad<11> -2959.5 243 15.6 100
302 SEG_pad<167> -1968.4 235.5 15.6 115 335 COM_pad<13> -2987.1 243 15.6 100
303 SEG_pad<168> -1996 235.5 15.6 115 336 COM_pad<15> -3014.7 243 15.6 100
304 SEG_pad<169> -2023.6 235.5 15.6 115 337 COM_pad<17> -3042.3 243 15.6 100
305 SEG_pad<170> -2051.2 235.5 15.6 115 338 COM_pad<19> -3069.9 243 15.6 100
306 SEG_pad<171> -2078.8 235.5 15.6 115 339 COM_pad<21> -3097.5 243 15.6 100
307 SEG_pad<172> -2106.4 235.5 15.6 115 340 COM_pad<23> -3125.1 243 15.6 100
308 SEG_pad<173> -2134 235.5 15.6 115 341 COM_pad<25> -3152.7 243 15.6 100
309 SEG_pad<174> -2161.6 235.5 15.6 115 342 COM__pad<27> -3180.3 243 15.6 100
310 SEG_pad<175> -2189.2 235.5 15.6 115 343 COM_pad<29> -3207.9 243 15.6 100
311 SEG_pad<176> -2216.8 235.5 15.6 115 344 COM_pad<31> -3235.5 243 15.6 100
312 SEG_pad<177> -2244.4 235.5 15.6 115 345 COM_pad<33> -3263.1 243 15.6 100
313 SEG_pad<178> -2272 235.5 15.6 115 346 COM_pad<35> -3290.7 243 15.6 100
314 SEG_pad<179> -2299.6 235.5 15.6 115 347 COM_pad<37> -3318.3 243 15.6 100
315 SEG_pad<180> -2327.2 235.5 15.6 115 348 COM_pad<39> -3345.9 243 15.6 100
316 SEG_pad<181> -2354.8 235.5 15.6 115 349 COM_pad<41> -3373.5 243 15.6 100
317 SEG_pad<182> -2382.4 235.5 15.6 115 350 COM_pad<43> -3401.1 243 15.6 100
318 SEG_pad<183> -2410 235.5 15.6 115 351 COM_pad<45> -3428.7 243 15.6 100
319 SEG_pad<184> -2437.6 235.5 15.6 115 352 COM_pad<47> -3456.3 243 15.6 100
320 SEG_pad<185> -2465.2 235.5 15.6 115 353 COM_pad<49> -3483.9 243 15.6 100
321 SEG_pad<186> -2492.8 235.5 15.6 115 354 COM_pad<51> -3511.5 243 15.6 100
322 SEG_pad<187> -2520.4 235.5 15.6 115 355 COM_pad<53> -3539.1 243 15.6 100
323 SEG_pad<188> -2548 235.5 15.6 115 356 COM_pad<55> -3566.7 243 15.6 100
324 SEG_pad<189> -2575.6 235.5 15.6 115 357 COM_pad<57> -3594.3 243 15.6 100
325 SEG_pad<190> -2603.2 235.5 15.6 115 358 COM_pad<59> -3621.9 243 15.6 100
326 SEG_pad<191> -2630.8 235.5 15.6 115 359 COM_pad<61> -3649.5 243 15.6 100
327 SEG_pad<192> -2658.4 235.5 15.6 115 360 COM_pad<63> -3677.1 243 15.6 100
328 COMS_PAD -2793.9 243 15.6 100 361 DUMMY1 -3704.7 243 15.6 100
329 COM_pad<1> -2821.5 243 15.6 100
330 COM_pad<3> -2849.1 243 15.6 100
331 COM_pad<5> -2876.7 243 15.6 100

62
ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

TRAY INFORMATION

TPy Dy

Dx
X

TPx
Px
Py

63
ULTRACHIP UC1609C_A1.0
©1999~2012 65x192 STN Controller-Driver

REVISION HISTORY
Revision Contents Date
0.6 First Release Jun. 8, 2012
(1) The tray drawing presents.
(2) The VLCD Quick Reference section is updated.
0.8 Jul. 24, 2012
(3) The Maximum Power Consumption data present.
(4) Some AC timings are updated.
1.0 MTP-Read related descriptions are revised. Aug. 3, 2012

64