Module-3:

CPU
Organization

Computer Organization and

8/24/2020 1
Architecture (15B11CI313)
 Basic Computer Organization

ALU: Arithmetic and Logical

Unit
L1: Level 1
L2: Level2
Basic Computer Organization-Adopted from [Ref.9]
Computer Organization and Architecture

(15B11CI313) 2
 Why CPU?
The computer does its primary work in a part of
the machine that cannot be see:
❖ A control center that converts data input to
information output.
❖ The CPU interacts closely with primary storage, or
main memory, referring to it for both instructions
and data.
 Central Processing Unit (CPU)

CPU is the abbreviation for central processing

unit or simply as the central processor, but
more commonly known as processor, the
CPU considered as the brains of the
computer and major data processing
undergoes in it[Ref.4].
 Central Processing Unit
(CPU)

Figure2: Schematic diagram of CPU i.e Dark-box in Figure2 - adopted from [Ref.2]
Modern Von Neumann Processor

Figure 3: CPU is marked by a dark box- adopted from [Ref.2]

 Components of CPU
The CPU is made up of three main components:
❖ Control Unit(CU)
❖ Arithmetic and Logic Unit(ALU)
❖ Immediate Access Store: Registers
along with above components , there are
interconnect as a system bus for data transfer
and
the clock.
 Function of CPU
The CPU is placed inside the computer case on the
motherboard. Its initial job is to carry out
commands. Whenever you press a key on keyboard,
click the mouse, or start an application, you're
sending instructions to the CPU.
CPU works in conjunction with the RAM and
retrieves data from it. Once CPU having instruction
and data together, it is ready to execute.
 Continued
…
Function of CPU
During execution of instructions that perform a set
of basic operations:
❖ Arithmetic operations such as addition, subtraction
multiplication and division.
❖ Memory operations for data movement from one
location to another.
 Instruction Representation

❖ CPU operation is determined by the instruction

it executes.
❖ Instruction Set is a collection of instructions
that can be executed on CPU.
❖ An instruction is represented as sequence of
bits, for example:
Opcode Operand 1 Operand 2
1001 0001 0000 0011 1010 1011 0010
1011
 Continued
…
Instruction Representation
Opcode (eg., 91) signifies the operation to be
performed. In previous slides, it indicates a data
copy operation by two operands: one source and
other destination.
Opcode represents
❖ operands type(data or address), operand 1
- address and operand 2 –data.
❖ Mode(register or memory): operand 1 -
memory, and operand 2 - immediate data.
❖ Instructions having two operand is not
necessary.
 Datapath and Control Unit
❖ The CPU in a computer system consists of
data path and control unit.
❖ The datapath composed of registers, function
units such as shifters and ALUs (arithmetic and
logic units), internal busses of processor and
dedicated paths, and unit interface for main
memory and I/O busses.
❖ The control unit manages the sequence of steps
taken by the data path during the execution of a
user-evident instruction, or macroinstruction (e.g.,
load, store ,sub, add).
 Continued
…

Datapath and Control Unit

❖ A pieceof action of the datapath is called
a register transfer. It governs the transfer of
information within the data path,
performs the transformation
possibly of data , address, or
instruction bits by the function units.
❖ A register transfer is consummated by gating out
(sending) register contents onto internal processor
busses, selecting the operation of ALUs, shifters,
etc., through which that information might pass,
and gating in (receiving) new values for one or
more Computer Organization and
Architecture (15B11CI313)
 Continued
…

Datapath and Control Unit

❖ Register-enabling signals, which control the
sending or receiving of data at the registers, and
operation-selection signals, which control the
actions of the functional units, are called control
signals.
❖ These signals are supplied by the control unit. The
collections of logic gates in the datapath that
respond to enabling signals and allow the sending or
receiving of data at the registers are called the
called control points .
C omputer Organization and Architecture
(15B11CI313)
 Continued
…
Datapath and Control Unit
❖ Each step in the execution of a
macroinstruction thus consists of one or more
a complete macroinstruction is executed by
register transfers, and
generating an appropriately timed sequence of
groups of control signals.
❖ Individual datapath or sets of related
actions are often called microoperations.
❖ Figure.2 depict that the ALU performs I/O
operations on stored data in the registers, while the
Control Unit sends /receives control signals for data
in conjunction with the register file.
 Continued
Datapath and Control Unit …

❖ To elaborate this concept more clearly , consider

an exampleas simple processing unit in Figure 4.

❖ The datapath of the processing unit, supports an

accumulator-based instruction set of four
macroinstructions (load, add, store, and conditional
branch).

❖ The accumulator (ACC) and program counter

(PC) are visible to the macroinstruction-level
programmer, but the other registers are not.
 Continued
Datapath and Control Unit …

Figure4: Data path of four instruction- small circles are control unit [Ref.3]
 Continued
Datapath and Control Unit …

In the datapath shown in the previous slides, control

signals such as ACC_in and ACC_out are register-
enabling signals, and control signals such
as aluadd and pcincr are operation-selection signals.
The description of four macroinstructions are [Ref.3]
:
(opcode 00) load address : ACC <- memory[ address ]
(opcode 01) add address : ACC <- ACC + memory[ address ]

(opcode 10) store address : memory[ address ] <- ACC

(op8c/2o4/2d02e0 11) brzComputer
address : if( ACC == 0 ) PC <-
Organization and Architecture
(15B11CI313)
 Control signal for the datapath
• ACC_in : ACC <- CPU internal bus
• ACC_out : CPU internal bus <- ACC
• aluadd : addition is selected as the ALU
operation
• IR_in : IR <- CPU internal bus
• IR_out : CPU internal bus <- address portion of
IR
• MAR_in : MAR <- CPU internal bus
• MDR_in : MDR <- CPU internal bus [Ref.3]
 Continued
…
Control signal for the datapath

• MDR_out : CPU internal bus <- MDR

• PC_in : PC <- CPU internal bus
• PC_out : CPU internal bus <- PC
• pcincr : PC <- PC + 1
• read : MDR <- memory[ MAR ]
• TEMP_out : CPU internal bus <- TEMP
• write : memory[ MAR ] <- MDR
[Ref.3]
 Continued
…
Data path and Control path
Control sequence for the macro-instructions is
based on control signal discussed in previous slides.
Also assumed that the read and write operation in
single clock cycle(T=1).

time steps T0-T3 for each instruction

fetch: T0: PC_out, MAR_in
T1: read, pcincr
T2: MDR_out, IR_in
T3: time step (if needed) for decoding the opcode in
the IR [Ref.3] .
 Continued
Datapath and Controlpath …

time steps T4-T6 for the load instruction:

T4: IR_out (addr part), MAR_in
T5: read
T6: MDR_out, ACC_in, reset to T0

time steps T4-T7 for the add instruction:

T4: IR_out (addr part), MAR_in
T5: read
T6: ACC_out, aluadd
Computer Organization and
22
8/ 24/
EMP_out, ACC_in, reset to T0
Architecture (15B11CI313)
 Continued
…

Datapath and Controlpath

time steps T4-T6 for the store instruction:
T4: IR_out(addr part), MAR_in
T5: ACC_out, MDR_in
T6: write, reset to T0 time steps T4-T5

for the brz (branch on zero) instruction:

T4: if (acceq0) then { IR_out(addr part), PC_in}
T5: reset to T0 [Ref.3]
 Instruction Execution
❖ To implementthe processing of these four
instructions on this datapath. The following steps
have been considered : fetch ,decode and
execute.

❖ The control signal generated for each of the phase

of different instructions may varies.

❖ Fetching the data from memory should be

keenly handle.
 Microinstruction

❖ A sequence of control signal generated at any time

step, is stored in control word is called as
microinstruction.
❖ Collection of these control words help to perform a
task know as microprogram.
❖ Microinstructions are
pseudo-instructions represented in
microcode's.
 Conclusion
❖ The key components of a computer system are its
control unit, registers, memory, ALU, and data
path.
❖ Computer systems follows Instruction execution
cycles to run program on it.
❖ An assembler translates mnemonic code to
machine code.
❖ A internal clock keeps everything
synchronized.
 Continued
…

Conclusion

❖ Control units can be microprogrammed or hardwired

❖ The Intel architecture(8085,8086) is an example of

a CISC machine whereas MIPS is an example of a
RISC machine.
 References
[Ref.1] John L. Hennessy and David A Patterson, Computer Architecture A
quantitative Approach, Morgan Kaufmann / Elsevier, Fourth Edition, 2007
.
[Ref.2] Mafla, E. Course Notes, CDA3101, @ URL [Link]
(as-of 11 Apr 2001)
[Ref.3] [Link]
[Ref.4] Ramesh Gaonkar, Microprocessor Architecture Programming and Applications
with the 8085, Prentice Hall, Fifth Edition, 1996.
[Ref.5] William Stallings, Computer Organization and Architecture–Designing for
Performance, Ninth Edition, Pearson Education, 2013.
[Ref.6] Barry B. Brey, The Intel Microprocessors: 8086/8088, 80186/80188, 80286,
80386, 80486, Pentium, Pentium Pro Processor, Pentium II, Pentium III, Pentium
4, and Core2 with 64-bit Extensions : Architecture, Programming, and
Interfacing. Pearson Education India, Eigth Edition, 2019.
[Ref.7] Nicholas Carter, Schaum’s outline of Computer Architecture, Tata McGraw
Hill, Second Edition, 2014.
 References
[Ref.8] Patterson, D.A. and J.L. Hennesey. Computer Organization and Design: The
Hardware/Software Interface, Second Edition, San Francisco, CA: Morgan
Kaufman (1998).

[Ref.9][Link]
e03-05_internalHardware.html

[Ref.10][Link] and T.G. Rauscher. Foundations of Microprogramming. New

York: Academic Press, 1976.