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SystemVerilog Array Types Explained

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18 views13 pages

SystemVerilog Array Types Explained

Uploaded by

cplprethi123
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

SystemVerilog Arrays

In SystemVerilog, arrays are used to store multiple values of the same data type. They help in
organizing data efficiently for processing within testbenches and RTL designs.
SystemVerilog provides various types of arrays to handle different needs in hardware
modeling and verification.

Why?
SystemVerilog arrays efficiently store and manage data, reducing redundancy and
optimizing memory, especially with packed arrays for bit-level manipulation. They are
essential in testbenches for storing test vectors and expected outputs, supporting dynamic
and associative arrays for flexibility. Arrays are widely used in protocol verification (e.g.,
PCIe, AXI, APB) to handle large data sets, making them crucial for scalable and efficient
hardware modeling.

Types of an array :
1. Fixed-size array in SystemVerilog
Single dimensional array
Multidimensional array
a. Two-dimensional array.
b. Three-dimensional array
2. Packed and Unpacked array in SystemVerilog
3. Dynamic array in SystemVerilog
4. Associative array in SystemVerilog

Fixed-size array in SystemVerilog :


A fixed-size array (or static array) in SystemVerilog has a predefined number of elements, allocated
at compile time. The size cannot be changed during simulation. These arrays are commonly used for
storing data in a structured manner when the number of elements is known beforehand.

Syntax:

int arr[5]; // Fixed-size array of 5 integers


Example:

module fixed_array_example;

int arr[5] = '{1, 2, 3, 4, 5}; // Initializing a fixed-size array

initial begin

foreach (arr[i])

$display("arr[%0d] = %0d", i, arr[i]);

end

endmodule

Multidimensional Array in SystemVerilog

A multidimensional array in SystemVerilog is an array with more than one dimension,


allowing structured data storage like matrices. These arrays help in organizing complex data
and are widely used in verification environments for handling large datasets.
Types of Multidimensional Arrays:

1. Two-Dimensional Array: Represents a table or matrix format.

int arr2D[3][4]; // 3 rows, 4 columns

2. Three-Dimensional Array: Extends into a cube-like structure.

int arr3D[2][3][4]; // 2 blocks, 3 rows, 4 columns

Example:

module multi_array_example;

int arr2D[2][3] = '{'{1, 2, 3}, '{4, 5, 6}}; // 2x3 matrix

initial begin

foreach (arr2D[i, j])

$display("arr2D[%0d][%0d] = %0d", i, j, arr2D[i][j]);

end

endmodule

Packed and Unpacked Arrays in SystemVerilog

Packed Array

A packed array is a contiguous collection of bits stored together, allowing bit-level


operations. It is used for efficient memory usage and precise control over data
representation.

Syntax:
logic [7:0] packed_array; // 8-bit packed array

bit [2:0][3:0] array;


Example:

module packed_2d_array_foreach;

logic [3:0][7:0] data; // 4 rows, each row is 8-bit wide

initial begin

// Assign values using foreach

foreach (data[i]) begin

data[i] = i * 8'h11; // Assigning unique values to each row

end

// Display values using foreach

foreach (data[i]) begin

$display("Row %0d: %b", i, data[i]);

end

end

endmodule

Unpacked Array

An unpacked array is an array where each element is stored separately in memory. It


provides flexibility for data storage but is less efficient in terms of memory.

Syntax :

int array[2:0] [3:0]; // Unpacked array


int [7:0] array [2:0];

Example:

module unpacked_2d_array_foreach;

byte [3:0] a[5:0]; // 6x4 unpacked array

initial begin

// Assign values using foreach

foreach (a[i, j]) begin

a[i][j] = i * 10 + j; // Assign unique values

end

// Display values using foreach

foreach (a[i, j]) begin

$display("a[%0d][%0d] = %0d", i, j, a[i][j]);

end

end

endmodule
Program:

module fixed_array_methods;

int arr[5] = '{4, 1, 3, 5, 2};

initial begin

// size()

$display("Original Array : %p", arr);

$display("Size : %0d", [Link]());

// reverse()

int reversed[5];

reversed = [Link]();

$display("Reversed Array : %p", reversed);

// sort()

int sorted[5];

sorted = [Link]();

$display("Sorted Array : %p", sorted);

// sum()

int total;

total = [Link]();

$display("Sum of Elements : %0d", total);

// find()

int found[$]; // dynamic array to hold found values

found = [Link] with (item > 2);

$display("Elements > 2 : %p", found);

end

endmodule
Dynamic Array

 A dynamic array is an array whose size can change during runtime.


 Unlike static arrays, you don't need to fix the size at compile time.
 It is useful when the number of elements is not known in advance.

Example program : (methods):

module dynamic_array_methods;

int da[]; // Declare dynamic array

initial begin

// Allocate memory using .new[]

da = new[5];

$display("After new[5], size = %0d", [Link]());

// Assign some values

foreach (da[i])

da[i] = i * 10;

// Display array elements

foreach (da[i])

$display("da[%0d] = %0d", i, da[i]);

// Check if an index exists

if ([Link](3))

$display("Index 3 exists with value = %0d", da[3]);

else

$display("Index 3 does not exist");

// Delete the array

[Link]();

$display("After delete, size = %0d", [Link]());

end

endmodule
Associative Array – Simple Explanation

 An associative array is an array indexed by keys, not by fixed integer positions.


 The index can be of any data type (int, string, etc.)
 Useful when the index is sparse or not sequential.

Syntax:

int aa[string]; // Associative array with string index

aa["apple"] = 10;

📌 Key Methods of Associative Arrays

Method Description Example

.exists(index) Checks if a given index exists [Link]("apple")

.delete(index) Deletes the given index [Link]("apple")

.num() Returns number of entries [Link]()

.first(var) Gets the first index [Link](i)

.last(var) Gets the last index [Link](i)

.next(var) Gets next index after current [Link](i)

.prev(var) Gets previous index before current [Link](i)


Example:

module assoc_array_example;

int aa[string]; // Associative array with string index

string idx;

initial begin

aa["apple"] = 10;

aa["banana"] = 20;

aa["cherry"] = 30;

// Display elements

foreach (aa[key])

$display("%s = %0d", key, aa[key]);

// Check existence

if ([Link]("banana"))

$display("banana exists!");

// Get first and next key

[Link](idx);

$display("First key: %s", idx);

[Link](idx);

$display("Next key: %s", idx);

// Total entries

$display("Total entries = %0d", [Link]());

end

endmodule
SystemVerilog Queue

 A queue is like a dynamic array, but with built-in push and pop features.
 The size can grow and shrink during runtime.
 Elements are ordered, and indexing is like arrays.

Syntax :

int q[$]; // Declare an integer queue

📌 Queue Methods

Method Description Example

.size() Returns number of elements [Link]()

.push_front() Adds element at the front q.push_front(10)

.push_back() Adds element at the end q.push_back(20)

.pop_front() Removes and returns first element q.pop_front()

.pop_back() Removes and returns last element q.pop_back()

q[index] Access element at specific index q[1]

.delete() Clears the queue [Link]()

Types
Declaration :
bit q_1[$]; // Unbounded queue of bit
byte q_2[$]; // Unbounded queue of byte
int q_3 [$:9]; // Bounded queue with qsize = 10

int q_4[$] = {5,6,7};

Example:

module queue_example;

int q[$]; // Declare a queue of integers

initial begin

// Add elements

q.push_back(10);

q.push_back(20);

q.push_front(5);

$display("Queue: %p", q); // Output: '{5, 10, 20}

$display("Size = %0d", [Link]());

// Pop elements

int x = q.pop_front();

$display("Popped front: %0d", x); // 5

x = q.pop_back();

$display("Popped back: %0d", x); // 20

// Final state

$display("Final Queue: %p", q); // '{10}

end

endmodule
UNION

 A union lets you store different types of data in the same memory location.
 Only one member is active at a time — changing one will affect others.
 Useful for memory optimization or interpreting data in multiple ways.

Example:

module union_example;

typedef union packed {

logic [15:0] whole;

struct packed {

logic [7:0] low;

logic [7:0] high;

} bytes;

} data_u;

data_u data;

initial begin

[Link] = 16'hABCD;

$display("Whole = %h, Low = %h, High = %h",

[Link], [Link], [Link]);

end

endmodule

Disadvantages of union in SystemVerilog

1. Only One Member at a Time


o You can store only one value at a time, even though multiple members exist.
2. Overwriting Issues
o Writing to one member overwrites the others since they share memory.
3. Hard to Debug
o It’s difficult to track which member is currently valid, which may lead to
unintended bugs.
Struct:

 A struct is a user-defined data type that groups multiple variables of different


types into a single unit.
 All members have separate memory.
 Useful for organizing related data.

Example :

module struct_example;

typedef struct packed {

logic [7:0] id;

logic [3:0] opcode;

logic enable;

} instr_t;

instr_t inst;

initial begin

[Link] = 8'hAA;

[Link] = 4'hF;

[Link] = 1'b1;

$display("ID = %h, Opcode = %h, Enable = %b",

[Link], [Link], [Link]);

end

endmodule

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