COEN 212 Tutorial 7 – Combination Circuit Design-Part 1
1- Design a logic circuit incrementer. A circuit that adds 1 to a four-bit binary
number.
Option 1: Using full adders
Use four full adders:
• Connect the four bits 𝐴𝐴0 –𝐴𝐴3 to one side.
• Connect constant 1 to the least significant carry input 𝐶𝐶𝑖𝑖𝑖𝑖 .
• Connect 0 to other B inputs.
• The output gives 𝐴𝐴 + 1.
Option 2: Using logic gates only
Use XOR and AND gates per the equation: 𝑆𝑆0 = 𝐴𝐴′0
𝑆𝑆1 = 𝐴𝐴1 ⊕ 𝐴𝐴0
𝑆𝑆2 = 𝐴𝐴2 ⊕ (𝐴𝐴1 𝐴𝐴0 )
𝑆𝑆3 = 𝐴𝐴3 ⊕ (𝐴𝐴2 𝐴𝐴1 𝐴𝐴0 )
𝐶𝐶𝑜𝑜𝑜𝑜𝑜𝑜 = 𝐴𝐴3 𝐴𝐴2 𝐴𝐴1 𝐴𝐴0
2- Design a 3-bit × 3-bit unsigned binary multiplier that multiplies A=a2a1a0 by
B=b2b1b0.
Draw it based on 4*3 multiplier in slides (Lecture 6 slide 21)
3- Design an excess-3-to-binary decoder using the unused combinations of the
code as don’t-care conditions. Excess-3 code is used for binary values in the
range of 0-9.
4- Using one decoder and external gates, design the combinational circuit defined
by the following two Boolean functions:
𝐹𝐹1 = 𝑥𝑥ʹ𝑦𝑦𝑦𝑦ʹ + 𝑥𝑥𝑥𝑥
𝐹𝐹2 = 𝑥𝑥𝑥𝑥ʹ𝑧𝑧ʹ + 𝑥𝑥𝑥𝑥
5- Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and
a 2-to-4 line decoder. Use block diagrams for the components.
6- Design each of the following functions F using a decoder:
a) F(A,B,C)=Ʃm (0,1,3,5,6) /or the output of these minterms of decoder
b) F(A,B,C)=ΠM(3,5,7) /The same
c) F(A,B,C)= A’ + (BC + C’)(ABC + B’) /
c) F=B’+ BC+B’C’= Ʃm(0,1,2,3,4,7)
7- Assume XOR delay = 10 ns and AND/OR delay = 5 ns. Calculate the worst-case
propagation delay of the 4-bit adder with:
(a) ripple-carry, as presented in Figure 1.
(b) Carry lookahead as presented in Figure 2.
a) Ripple: 4*(10+5+5)=80
b) (5+5) for carry lookahead(Ci) (Pi:10) (Final Xor for Sum (Si): 10=>total:30