COEN 212 Tutorial 9 – Combination Circuit Design-Part 2
1- Construct a 4-to-16-line decoder with five 2-to-4-line decoders with enable.
2- Design an 8-to-3 priority encoder (inputs D7..D0, D7 highest priority, D0
lowest).
a) show the truth table for the encoder.
b) Draw a logical gate diagram that implements the encoder
D0D1D2D3D4D5D6D7 xy z V
00000000 XXX 0
10000000 000 1
X1000000 001 1
XX100000 010 1
XXX 1 0 0 0 0 011 1
XXXX1000 100 1
XXXXX100 101 1
XXXXXX10 110 1
XXXXXXX1 111 1
x= 𝐷𝐷4𝐷𝐷5ʹ𝐷𝐷6ʹ𝐷𝐷7ʹ + 𝐷𝐷5𝐷𝐷6ʹ 𝐷𝐷7ʹ + 𝐷𝐷6𝐷𝐷7ʹ + 𝐷𝐷7
similar for y and z, and then simplify and draw the logic gate
V=D0+D1+D2…..+D7
3- Implement the following Boolean function with a multiplexer.
a) 𝐹𝐹(𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷) = 𝛱𝛱(2,6,11)
b) F(A, B, C, D) = Σ(0, 2, 5, 7, 11, 14)
a)
b)
Draw the MUX similar to part a
4- Design each of the following functions F using a multiplexer:
(a) F(A, B, C, D) = B C’ + A’ B + BC D’ + A’ B’ D + A B’ C’ D
(b) F(A, B, C, D) = A’ B’ + B’ C’ + C D + A’D’
a)
b) Similar method
5- Implement the following Boolean function with a 4 × 1 multiplexer and external
gates.
𝐹𝐹 (A,B,C,D) = ∑(0,1,4, 5, 10,12,14,15)
6- A demultiplexer routes a single data input E to one of four outputs D0, D1, D2,
D3 according to two select lines S1S0.
a) Write the truth table for the 1-to-4 demux.
b) Obtain Boolean expressions for each output Dk(S1,S0,E).
c) Draw a gate-level diagram using AND gates and inverters only
Draw the gate-level diagram based on D0 to D4 (above)