Chapter: THE MICROPROCESSOR

OBJECTIVES :

Know the role of the microprocessor

Know the different components of a microprocessor and their roles.
Understanding how the microprocessor works and the interaction between the
different units.
Master the steps necessary for executing programs by the
microprocessor.

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 1. Definition
A microprocessor is a complex integrated circuit characterized by a very high level of integration.
and endowed with the abilities to interpret and execute the instructions of a program. It is responsible
to organize the tasks specified by the program and ensure their execution. He must also take
count the information outside the system and ensure their processing. It is the brain of the system.
Currently, a microprocessor combines functionalities in just a few square millimeters.
always more complex. Their power continues to increase and their bulk decreases
regularly always respecting, for the moment, the famous Moore's law.

[Link] architecture of a microprocessor

A microprocessor is built around two main elements:
A control unit: also called Control and Command Unit (CCU)
A processing unit

associated with registers loaded to store the various information to be processed. These three elements
are interconnected by internal buses allowing the exchange of information.

3. The control unit

It allows sequencing the execution of instructions. It performs memory search for
the instruction. Since each instruction is encoded in binary form, it ensures decoding for
finally carry out its execution and then prepare the following instruction. For this, it is
composed by:
the program counter: (in English Program Counter PC) also called ordinal counter
(CO). The CO consists of a register whose content represents the address of the next
instruction to execute. It is therefore initialized with the address of the first instruction of the program.
Then it will be automatically incremented to point to the next instruction to be executed.
the instruction register: Contains the instruction currently being processed.
the instruction decoder:
The sequencer: It organizes the execution of instructions at the pace of a clock. It develops all
the internal or external synchronization signals (control bus) of the microprocessor in
function of the various control signals coming from the instruction decoder or the register
for example. It is an automaton designed either wired (obsolete) or in a way
micro-programmed, we then talk about micro-microprocessor.

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 4. The processing unit
It is the heart of the microprocessor. It combines the circuits that perform the necessary processing.
the execution of instructions. The processing unit is composed of three main execution units,
the first is the arithmetic and logic unit (ALU) and then two others were added which are the unit
de calcul en virgule flottante et l’unité multimédia pour des raisons d’optimisation des performances
microprocessors.

4.1. Arithmetic and Logic Unit: (ALU)

It is composed of logic circuits such as adders, subtractors, comparators.
logics…etc., in order to perform the calculations and logical operations of the various instructions to
execute, the data to be processed is presented at the inputs of the UAL, is processed, then the result is
provided as output and generally stored in a register called an accumulator. The information that
concerning the operation are sent to the state register.
The following diagram shows the UAL as well as its inputs and outputs.

EntryB EntryA

Accumulator

Orders: type of
the operation to be performed UAL Register
of state
(+,*,/, or, not, -,……)

DepartureoftheUAL

Scheme of the arithmetic and logical unit (its inputs and outputs)

[Link]-point unit:
It is a unit that is capable of performing calculation operations for real numbers as well as calculations.
complex mathematics and sciences.
Initially, the task of this unit was performed by a separate processor; in 1989 it was integrated.
in microprocessors to optimize calculations.

[Link] Unit:
It is a unit tasked with accelerating the execution of multimedia programs involving
videos, sound, 3D graphics, etc.…
This unit is named MMX for the first Pentium (MultiMedia eXtensions) integrating
multimedia management functions, as well as the 3DNOW technology for AMD and SSE for the
Pentium III.

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These units were created because of the strong trend towards multimedia in all types of programs.
computers (games, software on the Internet, encyclopedias...).

Figure 1. Functional diagram

5. Other units of the microprocessor

[Link] memory unit:
The cache memory has the main function of optimizing access to various instructions and
data that the microprocessor needs when executing programs. The task of this unit
is to put in the cache memory which is much faster than main memory, the
most frequently used information that the microprocessor needs. Access to
Information will therefore be faster and program execution is more optimal.
The principle of storing information in this memory is done by a controller that uses
specific algorithms that allow choosing which data and instructions in the
central memory to include in this memory and when it needs to be replaced since the size of the
Cache memory is very limited compared to the size of the main memory.
The performance of the microprocessor is closely related to the validity of the predictions made by the controller.
cache memory. There are two levels of cache memory. Level 1 cache is always
Integrated into the microprocessor, its size is a few kilobytes and can reach 256 KB in some cases.
microprocessors. The second level cache is typically on the motherboard, its size ranges from 256
KO up to 1MB.

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 [Link] interface unit:
Manages exchanges through the bus between the microprocessor and other components, if the
the microprocessor needs, for example, data in RAM, the bus interface unit
responsible for bringing it back by controlling memory access and placing the result on the data bus which
it will forward it to the data registry.

5.3. Segmentation and pagination units:

These units have become necessary especially for the microprocessors of the INTEL X86 family in
reason for their particular ways of managing memory.
These units allow the translation of logical addresses manipulated in programs into addresses.
physical addresses that correspond to real addresses in memory. These units vary from a
microprocessor to another depending on the memory management technology used.

[Link] Unit:
It decomposes and analyzes the instruction found in the instruction register, according to the code.
operation, it sends the nature of the operations to be carried out to the command unit and precisely the
sequencer that will then generate the necessary microcommands for the different components
participant in the execution of the ongoing instruction.

RI Operation code zone addresses

Microcommands
Unit of
decoding Command bus
Sequencer

Example:
For a microprocessor with a two-address instruction format, the addition instruction of
two variables in memory A and B are represented in the instruction register as follows:

ADD address of A address of B

Operation code
Memory address zones of the operands

Command signals for

Decoding of the c-op search for the addresses of A and B
in memory and to carry out
the addition by the UAL

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 5.5. Anticipation unit and the queue (or waiting line):
The anticipation unit's role is to fetch the instructions to be executed from memory.
Instructions are first searched in the processor's internal cache memory. If they are not found there.
do not find, the anticipation unit addresses the bus interface unit so that they can be read in the
central memory.
During this operation, the content of the following memory addresses is also read and placed in
the processor's cache memory. In this way, the next requested instructions will be
available more quickly (provided that the content is not modified by then).
The anticipation unit puts the instruction in a queue and takes care of fetching the next one. Thanks
In this device, the execution unit almost never has to wait for the instructions to be executed.
may be brought about (this can however happen if a series of very rapid instructions to be executed...
presents). Conversely, if the instructions require significant execution time, the queue becomes
Fill it. In this case, the anticipation unit stops working until space becomes available for
new instructions.

6. The registers of the microprocessor

A register is a small memory area inside the microprocessor that allows for
memorize words, memories or addresses temporarily during execution of
instructions.
The number and type of registers that the CPU has are a determining part of its architecture.
and have a significant influence on programming. The structure of the CPU registers varies
considerably from one manufacturer to another. However, the basic functions performed by the
different registers are essentially the same. We will describe the most registers.
important, their function and how they can be modified programmatically.
There are two types of registers: general registers and address registers:
The general registers:
These are fast memories, inside the microprocessor, that allow the execution unit to
manipulate data at high speed. They are connected to the internal data bus of the microprocessor.
The address of a register is associated with its name (a letter is usually given as a name) A, B, C...
These registers allow for the storage of information used in programs or
intermediate results, this avoids accesses to memory, thus speeding up execution of
programmes.
The general registers are available to the programmer who normally has a choice.
instructions for manipulating them like
Loading a register from memory or another register.
Recording in memory the content of a register.

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 Transfer of content from a register to the accumulator and vice versa.
Incrementing or decrementing a register.
-
Address registers (pointers)
These are registers connected to the address bus, their content is a central memory address.
There are several types. We can cite the following registers:
The ordinal counter (program pointer PC)
The stack pointer (SP)
The index registers (Source index SI and Destination index DI)
1- The ordinal counter: (program pointer PC)

Figure 2. Descriptive diagram of the operation of the ordinal counter register

It contains the address of the instruction to be searched in memory. The control unit increments the
ordinal counter (PC) of the number of bytes on which the instruction being executed is coded. The
the ordinal counter will then contain the address of the next instruction.
(PC)=10000H; it points to the memory that contains the instruction MOV C,B which is encoded on
two bytes (89 D9H); the control unit will increment the content of the PC by two: (PC) = 10002H
(the memory will be assumed to be organized in bytes).
2-The instruction register:
contains the instruction that must be processed by the microprocessor, this instruction is searched for in
memory then placed in this register to be decoded by the decoder and prepared for execution.
An instruction is a basic operation of a programming language, that is to say the most
small order that a computer can understand.
Example: ADD A,B this instruction corresponds to a command given to the computer in language
assembler that allows adding data A and B.
Every instruction actually presents two types of information:
What action to take (addition, display, division …)
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 With what data to carry out this action.

Operational zone Zone addresses

Composition of an instruction
Operation zone: This zone allows determining the nature of the operation to be carried out by the
microprocessor.
Address zone: contains the memory addresses of the operands involved in an operation,
in some cases it contains the operand itself. There are several addressing modes to access
to the data.
3-The address register:
This is a register that contains the address of the word to be accessed in main memory. With each access
memory, the sought address is stored in this register. It has the size of an address which is the same
that of the address bus which makes it possible to determine the number of addressable memory words and
the addressable memory space.
4- The memory register or data register:
Contains the word memory subject to a read or write operation in the memory
central. This register has the size of a memory word, which is the same as that of the working registers.
the accumulator which is equal to the size of the data bus.
The diagram below shows the operation of the two address registers and the memory word.

Word 1 Adr 1
Register Dispositif de sélection et Word 2 Adr 2
of address access to memory
Selection Word 3 Adr 3
Transfer address Word 4 Adr 4
....

Writing
Memory word register
or data
Lecture

Reading and writing in the central memory is done as follows:

. Lecture: l’adresse du mot à lire est transférée au registre d’adresse, le dispositif d’accès à la
memory takes care of searching for the word and putting it in the memory word register.
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. Writing: the address register is loaded with the memory address where we are going to write, the word to be written is
placed in the register memory. When the write order is given, the content of the cells
memory will be overwritten and replaced with the new value. However, in the case of reading, the content of the
memory cases are not destroyed.
5- The accumulator register:
It is a very important work register of the UAL, in most arithmetic operations and
logically, the accumulator holds one of the operands before execution and the result after. It can also
serve as a buffer register in input/output operations. Generally, the accumulator has the same
size of a memory word.
Naturally, the programmer has access to this register which is always highly requested during processing.
data. Some processors have multiple accumulators, and in this case, the operation codes
specify the accumulator used.
6- The state register: (PSW program status word)
It is a register that contains the different bits called flags indicating the state of a
condition particulière dans le CPU. Ces bits peuvent être testés par un programme et donc décider des
action plans to take.
To correctly perform his work, the sequencer must also know the state of a certain
name other components and have information regarding the operation(s) that have already
were executed (for example, should we take into account in the ongoing addition any possible withholding
preliminary generated by a previous addition). The state register provides this information.
The number of bits in this register changes from one microprocessor to another, for example in the case of a
8088 this register is 16 bits:

U U U U O D I T S Z U AC U P U C
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

U : undefined refers to an undefined bit.

The different bits of the status register are:
. Carry bit: it is bit C or carry which is bit number 0. This bit is set to 1 if there is a carry.
generated during an arithmetic operation.
. Parity bit: parity bit number 2, this bit is set to 1 if the number of 1s in the accumulator is even.
. Intermediate carry bit: the AC (auxiliary carry) bit, it is bit number 4, it is set to 1 if a
carry is generated between groups of 4 bits (carry propagation).
. Bit zero: it is bit number 6, it is set to 1 if the result of an arithmetic operation is zero.
. The sign bit: bit number 7, it is 1 if the result of an arithmetic operation is negative.

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. The overflow bit: bit number 11, O for overflow, it is 1 if there is an overflow.
capacity in arithmetic operations. For example, in 8 bits in two's complement, the numbers
binaries are coded on 8 bits. Numbers can be coded from -128 (10000000) to
+127(01111111). If we add 107+28 it gives 135 which cannot be represented, hence generation of
overflow.

Example 1: addition of binary numbers on 8 bits

11111100
+ 10000010 FCH + 82H = 17EH
carry :1= 01111110 +
(252)10(130)10(382)10 =

Example 2: The Labascule C(carry) is also used to capture the bit expelled during an operation
shift or rotation
Left shift of one bit of this byte: 10010110
the carry collects the 1 from the heavy carry: 100101100

Example 3: overflow

104 x 18 1110 1110

+26 + 0001 1010 118 1000 1010
=130 = 1000 0010 (-126) -136
0111 1000 (120) with C=1

The overflow indicator is a logical function (exclusive OR) of the carry (C) and the sign.
(S).

7- The stack pointer register: (Stack Pointer)

. It contains the address of the stack. This is a part of the memory, it allows to store some
information (the content of the registers) relating to the handling of interruptions and subs
programmes
. The stack is managed in LIFO: (Last IN First Out) last in first out. The operation is
identique à une pile d'assiette
. The stack pointer SP points to the top of the stack (31000H in the diagram), it is decremented before
each stack, and incremented after each pop.
. There are two instructions for pushing and popping : PUSH and POP.
example:
PUSH A pushes the register A and POP A will pop it.

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 In figure 1, we will show how the stack operates during instructions like PUSH and POP.

Figure 3. Backup Diagram on the Stack

Question?
What will happen during the execution of the program starting at 12E30H? What will SP be and what
Will the stack contain this address at the end of the program?

Réponse.
The program starts by saving the content of C onto the stack (PUSH C). For this (SP) is
decremented by two ((SP)=31000H-2=30FFEH), then we write (C) into memory at
the address (SP): (30FFEH) = 6142H.
For PUSH A we get: (30FFCH)=1234H, and for PUSH B: (30FFAH)=2D5AH.
For the POP B instruction, ((SP)) is loaded into register B ((SP)=30FFAH; (B)=2D5AH) then (SP)
is incremented by two ((SP)= 30FFAH+2=30FFCH).
Finally, for POP A we get: (A)=1234H and (SP)=30FFCH + 2 = 30FFEH
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8- The index registers (source index SI and destination index DI)
Index registers can be used as general registers for saving and for
to count. But in addition they have a special function that is of great use in the manipulation of
data tables. They can indeed be used to manipulate addresses and allow for
memorizing an address, following a specific form of addressing, called indexed addressing.
Example:
MOV A,[SI+10000H] places the content of the memory at address 10000H plus the content of SI into the
register A.

Figure 4. Example on the index register

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 7. STEPS FOR EXECUTING AN INSTRUCTION
(Instruction execution cycle)
The microprocessor only understands a certain number of instructions that are coded in binary.
The processing of an instruction can be broken down into three phases.
Phase 1: Research of the instruction to be processed

1. The PC contains the address of the next instruction of the program. This value is placed on the bus.
from addresses by the control unit that issues a read command.
2. After a certain amount of time (access time to memory), the content of the memory cell
Selected is available on the data bus.
The instruction is stored in the instruction register of the processor.

Phase 2: Decoding the instruction and operand retrieval

The instruction register now contains the first word of the instruction that can be coded on
several words. This first word contains the operational code that defines the nature of the operation to
perform (addition, rotation,...) and the number of words in the instruction.
The control unit transforms the instruction into a series of elementary commands necessary
to the processing of the instruction.

2. If the instruction requires data from memory, the control unit retrieves it.
value on the data bus.
The operand is stored in a register.

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Phase 3: Execution of the instruction
The micro-program performing the instruction is executed.
2. The flags are positioned (state register).
3. The control unit positions the CPU for the next instruction.

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 8. Game of Instructions
[Link]
The first step in the design of a microprocessor is defining its instruction set.
The instruction set describes the entire set of elementary operations that the microprocessor can execute. It will
therefore partly determine the architecture of the microprocessor to be created, particularly that of the sequencer. At a
The same set of instructions can correspond to a large number of different implementations of the microprocessor.

[Link] of instructions
The instructions found in every microprocessor can be classified into 4 groups.
:
. Data transfer to load or save in memory, perform register transfers to
register, etc...
. Arithmetic operations: addition, subtraction, division, multiplication
. Logical operations: AND, OR, NOT, NAND, comparison, test, etc...
. Sequence control: connection, testing, etc...

[Link]
Instructions and their operands (parameters) are stored in main memory. The total size
the number of bits needed to represent it in memory depends on the type of instruction and
also of the operand type. Each instruction is always coded on an integer number of bytes to facilitate
its decoding by the processor. An instruction is made up of two fields:
. the instruction code, which tells the processor which instruction to execute
. the operand field that contains the data, or a reference to a data in memory (its
address).

Example:

The number of instructions in the instruction set is directly related to the format of the instruction code. Thus, a
An octet allows for the distinction of up to 256 different instructions.

[Link] mode
An addressing mode defines how the microprocessor will access the operand. The
Different addressing modes depend on the microprocessors, but generally we find:

. the register addressing where the data contained in a register is processed

. immediate addressing where the value of the data is defined immediately
. direct addressing where data is processed in memory

Depending on the data addressing mode, an instruction will be coded by 1 or more bytes.

[Link] time
Each instruction requires a certain number of clock cycles to execute. The number of
cycles depend on the complexity of the instruction and also on the addressing mode. It takes longer to access the
main memory than a processor register. The duration of a cycle depends on the clock frequency of the
sequencer.

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 8.6. Programming language
Machine language is the language understood by the microprocessor. This languageHigh language
levelis difficult to master since each instruction is coded by its own sequence of bits. In order to
To facilitate the task of the programmer's compilation, we have created different languages that are more or less advanced.

Assembly language
(sta, lda, cmp, mov, bra, etc…)
Assembly language is the language
the closest to machine language. It is composed of instructions in general assembly quite
rudimentary ones that are called
Machine language
(0001 1101, 1111 0110, etc…)
mnemonics. They are essentially data transfer operations between the
registers and the outside of the microprocessor (memory or peripheral), or arithmetic operations or
logics. Each instruction represents a different machine code. Each microprocessor can have a
different assembler.
The difficulty of implementing this type of language, and their strong dependence on the machine
the necessity of designing high-level languages, more suitable for humans, and for the applications they were looking for
to develop. Disregarding any machine architecture, these languages allow expression
of algorithms in a form that is easier to learn and master (C, Pascal, Java, etc.). Each instruction
In high-level language, it will correspond to a sequence of instructions in assembly language. Once
developed, the program in high-level language is therefore not comprehensible by the microprocessor. It
it needs to be compiled to translate it into assembly language and then assembled to convert it into machine code
understandable by the microprocessor. These operations are carried out using specialized software called
compiler and assembler.

Example of program:

@00 C6 64 LDAB A=0 ;

#100
Load Accumulator A
@01 B6 00 for (i=1; i<101; i++) A=A+i;
#0
@03 1B ret ABA
@04 5A DECB
@05 26 03 BNE ret

[Link] of a microprocessor
The power of a microprocessor can be characterized by the number of instructions it is capable of
processed per second. To do this, we define:

. the CPI (Cycles Per Instruction) which represents the average number of clock cycles needed
pour l’exécution d’une instruction pour un microprocesseur donné.
. MIPS (Millions of Instructions Per Second) which represents the processing power of the
microprocessor
F
H with FHen MHz

MIPS=
CPI
To increase the performance of a microprocessor, one can either increase the clock frequency.
(material limitation), either decrease the CPI (choice of a suitable instruction set).

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 [Link] of RISC and CISC architecture
Currently, the architecture of microprocessors consists of two main families:

The CISC (Complex Instruction Set Computer) architecture

The RISC architecture (Reduced Instruction Set Computer)

10.1. The CISC architecture

Why
In the past, the design of CISC machines was the only feasible option. Indeed, given that memory
worked very slowly compared to the processor, it was thought that it was more interesting to submit to
complex instruction microprocessor. Thus, instead of coding a complex operation with several
smaller instructions (which would require the same amount of very slow memory access), it seemed preferable to add
In the microprocessor instruction set, a complex instruction that would handle this operation.
Moreover, the development of high-level languages posed many problems regarding design.
of compilers. There has thus been a tendency to incorporate instructions closer to the processor level.
structure of these languages.

Comment
It is therefore an architecture with a large number of instructions where the microprocessor must execute.
complex tasks by single instruction. For a given task, a CISC machine thus executes a small
number of instructions but each requires a greater number of clock cycles. The machine code of
these instructions vary from one instruction to another and therefore require a complex decoder (micro-code)

10.2. The RISC architecture

Why
Statistical studies conducted during the 1970s clearly showed that the programs
generated by compilers most often consisted of assignments, additions, and multiplications by
of constants. Thus, 80% of high-level language processing relied on only 20% of the
microprocessor instructions. Hence the idea of reducing the instruction set to those most commonly used.
and improve processing speed.

Comment
It is therefore an architecture in which the instructions are limited in number (loading,
branching, subprogram call). RISC architectures can therefore be implemented from
wired sequencer. Their realization frees up space allowing for an increase in the number of registers or
of processing units for example. Each of these instructions thus executes in one clock cycle. Well
Often, these instructions only have one addressing mode. Access to memory takes place
only from two instructions (Load and Store). On the other hand, complex instructions must be
carried out from sequences based on elementary instructions, which requires a very
evolved in the case of programming in high-level language.

[Link]
The choice will depend on the intended applications. Indeed, if we reduce the number of instructions, we create
complex instructions (CISC) that require more cycles to be decoded and if we reduce the number of
cycles per instruction, we create simple instructions (RISC) but then we increase the number of instructions
necessary to carry out the same treatment.

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 RISC Architecture CISC Architecture

simple instructions taking only one complex instructions taking several

cycle cycles
fixed format instructions variable format instructions

simple decoder (wired)

complex decoder (microcode)
many registers few records

only the LOAD and STORE instructions are all instructions are likely
access to memory to access memory

few addressing modes many addressing modes

complex compiler simple compiler

11. Improvements to the underlying architecture

The set of improvements in microprocessors aims to reduce the execution time of
program.
The first idea that comes to mind is simply to increase the clock frequency of the
microprocessor. But the acceleration of frequencies causes an increase in consumption which leads to
a rise in temperature. We are then led to equip processors with cooling systems
or to lower the power supply voltage.
Another possibility to increase the processing power of a microprocessor is to decrease the
average number of clock cycles required for the execution of an instruction. In the case of a
high-level language programming, this improvement can be achieved by optimizing the compiler. It is necessary to
that it be able to select the instruction sequences minimizing the average number of cycles per
instructions. Another solution is to use a microprocessor architecture that reduces the number of
cycles per instruction.

[Link] pipeline
Prince
The execution of an instruction is broken down into a succession of steps, and each step corresponds
to the use of one of the functions of the microprocessor. When an instruction is in one of the steps,
the components associated with the other steps are not used. The functioning of a microprocessor
simple is therefore not effective.
The pipeline architecture improves the efficiency of the microprocessor. Indeed, when the first
Once the execution step of an instruction is completed, the instruction enters the second stage of its execution.
and the first phase of the execution of the following instruction begins. Therefore, there may be an instruction in progress.
execution in each of the steps and each of the components of the microprocessor can be used at each
clock cycle. Efficiency is at its maximum. The execution time of an instruction is not reduced but the throughput
the execution of instructions is significantly increased. A pipeline machine is characterized by the
number of steps used to execute an instruction, this number of steps is also called the number
of the pipeline stages.
Example of the execution in 4 phases of an instruction:

Classic model:

R1 R2 R3

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 Cycles
Number of 1 2 3 4 5 6 78910 11 12

Pipelined model:

R1 R2 R3 R4 R5 R6 R7 R8 R9

Number of

1 2 3 4 5 6 78910 11 12
Cycles

Performance gain
In this structure, the machine begins executing an instruction at each cycle and the pipeline is
fully occupied from the fourth stage. The gain obtained therefore depends on the number of stages in the pipeline.
Indeed, to execute instructions, assuming that each instruction executes in k clock cycles, it
fault

. n.k clock cycles for a sequential execution.

. k clock cycles to execute the first instruction then n-1 cycles for the n-1 instructions
following if we use a k-stage pipeline

The gain obtained is therefore:

nk

i
G=
k+n-1

So when the number of instructions to execute is large compared to k, we can assume that we
divide the execution time park.
Remarks :
The processing time in each unit must be roughly equal; otherwise, the fast units must
to wait the units lenses.

Examples:
The AMD Athlon includes an 11-stage pipeline.
The Intel Pentium 2, 3, and 4 have a pipeline of 12, 10, and 20 stages, respectively.

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Problems
The implementation of a pipeline poses several problems. In fact, the longer the pipeline, the more the
The number of cases where it is not possible to achieve maximum performance is high. There are 3 main cases.
where the performance of a pipelined processor can be degraded; these cases of performance degradation are
called unforeseen events:

. structural hazard which corresponds to the case where two instructions need to use the same
processor resource (dependency conflict)
. data hazard that occurs when an instruction produces a result and the instruction
next use this result before it has been written into a register,
. control hazard that occurs every time a branch instruction is executed.
When a branch instruction is loaded, one usually has to wait to know the address of
destination of the connection in order to load the next instruction. The instructions that follow the jump and
those that are being processed on the lower floors are generally for nothing, it will then be necessary to empty the
pipeline. To mitigate the effect of branching, one can specify instructions after the branch that
will always be executed. Branch prediction is also used to keep track of during
the most likely branching behavior. Branch prediction mechanisms allow
to achieve a prediction reliability of around 90 to 95%.

Bubbles (NOP)

When a hazard occurs, it means that an instruction cannot continue to progress in the
pipeline. During one or more cycles, the instruction will remain blocked in a stage of the pipeline, but the
instructions situées plus en avant pourront continuer à s’exécuter jusqu’à ce que l’aléa ait disparu. Plus le
the pipeline has stages, the greater the penalty. Compilers strive to generate sequences
instructions to maximize the filling of the pipeline. The empty stages of the pipeline are called
pipeline 'bubbles', in practice a bubble actually corresponds to a NOP (No OPeration) instruction issued
instead of the blocked instruction.

[Link] of memory cache

Problem posed
The performance gap between the microprocessor and memory continues to widen. In fact, the
memory components benefit from the same technological advances as microprocessors but the
Decoding addresses and reading/writing data are difficult steps to accelerate. Thus, the
Processor cycle time decreases faster than memory access time, causing a bottleneck.
The memory is no longer able to deliver information as quickly as the processor is capable.
de les traiter. Il existe donc une latence d’accès entre ces deux organes.
Principle
Since the early 80s, one of the solutions used to mask this latency is to have
a very fast memory between the microprocessor and memory. It is called cache memory.
thus compensates for the low relative speed of the memory by allowing the microprocessor to acquire the
data at its own speed. It is made from a small-sized SRAM cell (due to cost). Its

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the memory capacity is therefore much lower than that of the main memory and its function is to store the
most recent or most frequently used information by the microprocessor. Initially, this memory
was integrated outside the microprocessor but is now an integral part of the microprocessor and
is expressed even on several levels.
The principle of cache is very simple: the microprocessor is not aware of its presence and it
sends all its requests as if it were acting as the main memory:

. Either the data or the required instruction is present in the cache and it is then sent.
directly to the microprocessor. We talk about cache success. (a)
. either the data or the instruction is not in the cache, and the cache controller then sends
a request to the main memory. Once the information is retrieved, it sends it back to the microprocessor while
storing it in the cache. We are talking about a cache miss.

a)
up

Unit of Control Processing Unit Cache

memory

Of course, the memory cache only provides a performance gain in the first case. Its performance
is therefore entirely connected to its success rate. It is common to encounter average success rates of
around 80 to 90%.

Notes:
A cache will use a map to know which words from the main memory it has a
copy. This card must have a simple structure.
There are two copies of the same information in the system: the original in the main memory and the
copy into the cache. If the microprocessor modifies the data present in the cache, it will be necessary to plan for a
main memory update. When the cache needs to store a piece of data, it is required to erase one.
other. There is therefore a controller that allows knowing when the data was last used
times. The oldest unused one is then replaced by the new one. It is worth noting that one can reuse the same
principle for hard drives and CD/DVD.

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 [Link] Architecture
Another way to gain performance is to execute multiple instructions at the same time.
The superscalar approach involves equipping the microprocessor with several processing units that work in parallel.
parallel. The instructions are then distributed among the different execution units. Therefore, it is necessary to be able to
support a significant flow of instructions and therefore have an efficient cache.

Scalar architecture:

Superscalar architecture:

I1

N/2 cycles

Note
:

This is the type of architecture implemented in the first Intel Pentiums that appeared in 1993.

[Link] pipeline and superscalar

The principle is to execute the instructions in a pipelined manner in each of the processing units.
working in parallel.

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 12. Special processors
12.1. The microcontroller
They are minimum systems on a single chip. They contain a CPU, RAM, ROM, and
input/output ports (parallel, serial, I2C, etc.). They also include specific functions such as
programmable counters for measuring durations, ADCs to see DACs to fit in
acquisition chains, field network interfaces, etc ...
It is designed to best meet the needs of embedded applications (device
appliances, acquisition chain, chip card reader, etc...). However, it is generally less
powerful in terms of speed, size of processable data, or size of addressable memory than a
microprocessor.

12.2. The signal processor

The signal processor is much more specialized. While a microprocessor is not designed
for a specific application, the DSP (Digital Signal Processor) is optimized to perform
digital signal processing (FFT calculation, convolution, digital filtering, etc...)
The application areas of DSPs were originally telecommunications and the military sector.
Today, applications have diversified towards multimedia (CD player, MP3, etc.) and consumer electronics.
public (digital television, mobile phone, etc...), automation, instrumentation, electronics
automobile, etc...

[Link]
Here are two examples of the architecture of two processors that were at the top of their game when they were released.
In 1999: AMD's Athlon and Intel's Pentium III. (f ≈ 500MHz)

AMD Athlon :

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 AGU : Adress Generation Unit BTB : Branch Target Buffer IEU : Integer Execution Unit BHB : Branch History Buffer
Characteristics:

. 9 processing units consisting of:

o 1 ALU (integer processing) including 6 processing units:
. 3 units for data processing (IEU)
. 3 units for data addressing (AGU)
o 1 FPU (real processing) including 3 units:
. 1 FPU store
. 1 Fadd / MMX / 3Dnow !
. 1 Fmul /MMX / 3Dnow !
. Total pipeline: 10 floors, floating pipeline: 15 floors.
. Dynamic prediction and out-of-order execution of processing
. 6 parallel decoding units (3 micro-programmed, 3 wired) but only 3 can
function at the same time.
. Level 1 cache (L1): 128 KB
o 64 Ko for data
o 64 Ko for instructions
. L2 cache controller supporting from 512KB to 8MB with programmable speed (1/2 or 1/3 of
the CPU speed

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Intel Pentium III

Characteristics:

. Multiple processing units but with 5 instructions executed simultaneously on 5 ports:

o Port 0: ALU, FPU, AGU MMX and SSE
o Port 1: ALU, SSE, MMX
o Port 2 : AGU (load)
o Port 3: AGU (store)
o Port 4: Store Data Unit
. Whole pipeline: 12 to 17 floors, floating pipeline: about 25 floors
. Dynamic prediction and out-of-order execution
. 3 parallel decoding units: 1 micro-programmed, 2 wired.
. 5 pipelines of 10 floors
. Level 1 (L1) cache memory: 32 KB
o 16 KB for data
o 16 Ko for the instructions
. L2 cache controller supporting up to 512 KB at half the CPU speed
. 9.5 million transistors

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References
Malek Zribi Course, ISET Sfax
Dumartin Course (.pdf)
Livre : « Architectures des ordinateurs » [Link] »

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