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Digital Circuits
Assignment- Week 7
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15
______________________________________________________________________________
QUESTION 1:
For the logic circuit given below, the decimal count sequence and the modulus of the
circuit corresponding to A B C D are?
A) 8 4 2 1 9 5 (MOD 6)
B) 8 4 2 9 5 3 (MOD 6)
C) 2 5 9 1 3 (MOD 6)
D) 8 5 1 3 7 (MOD 5)
Correct Answer: B
Detailed Solution:
The J-K flip-flop with J=k+1 is implementing negative edge triggered T- flip flop.
The output D will change whenever C changes from 1 0.
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The 3 – bit ring counter will count through 3 stages initialization is important to
start ring counter hence let any 1 bit will be 1 say (C = 1)
A B C D
0 0 1 0 2
1 0 0 1 Toggle 9
0 1 0 1 5
0 0 1 1 3
1 0 0 0 Toggle 8
0 1 0 0 4
0 0 1 0 2
The output sequence is
2 9 5
4 8 3
The counter counts 6 stages. Hence it is mod- 6 counter.
QUESTION 2:
The contents of the following registers (Q4Q3Q2Q1Q0) after two clock transitions are.
(Assume initial values of all flip-flops are logic 1).
A) 1 1 1 1 0
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B) 1 1 0 0 1
C) 1 1 0 1 0
D) 1 1 1 0 0
Correct Answer: D
Detailed Solution:
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QUESTION 3:
The minimum number of flip-flops required to design a mod-150 counter?
A) 8
B) 7
C) 6
D) 15
Correct Answer: A
Detailed Solution:
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QUESTION 4:
An eight – bit binary ripple UP counter with a modulus of 256 is holding the count
01111111. What will be the count after 135 clock pulses?
a) 0000 0101
b) 1111 1001
c) 0000 0110
d) 0000 0111
Correct Answer: C
Detailed Solution:
01111111 127
After 135 clock cycles, we will get 127 + 135 = 262.
The total number of clock pulses will be 262.
As the modulus is 256, after 256 clock pulses, the sequence will repeat.
262 = 256 + 6
257 00 00 00 01
258 00 00 00 10
259 00 00 00 11
260 00 00 01 00
261 00 00 01 01
262 00 00 01 10
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____________________________________________________________________________
QUESTION 5:
In a Johnson counter circuit using negative edge-triggered J-K flip-flops, all flip-flops
are initially reset, resulting in outputs Q₃Q₂Q₁Q₀ = 0000. What are the outputs of the
flip-flops after the fifth negative going pulse?
(A) Q₃Q₂Q₁Q₀ = 0101
(B) Q₃Q₂Q₁Q₀ = 1000
(C) Q₃Q₂Q₁Q₀ = 0010
(D) Q₃Q₂Q₁Q₀ = 1110
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Correct Answer: D
Detailed Solution:
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Sequence Summary
Thus, the first part of the Johnson counter sequence is:
0000 → 0001 → 0011 → 0111 → 1111 → 1110 ⋯0000
QUESTION 6:
The state transition diagram for the logic circuit shown is
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A)
B)
C)
D)
Correct Answer: D
Detailed Solution:
Output expression Y for 2 x 1 MUX is given as
---------------(1)
The next state of D flip-flop is :
--------------------(2)
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From the given circuit :
We know that :
From the given data :
From the equation (2)
A Present State (Q) Next State
0 0 Q=1
0 1 Q=0
1 0 Q=0
1 1 Q=1
QUESTION 7:
If a counter having 10 FFS is initially at 0, what count will it hold after 2060 pulses?
a) 000 000 1100
b) 000 001 1100
c) 000 001 1000
d) 000 000 1110
Correct Answer: A
Detailed Solution:
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QUESTION 8:
For the circuit shown, the counter state (Q 1 Q0) follows the sequence
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a) 00, 01, 10, 11, 00 ….
b) 00, 01, 10, 00, 01 ….
c) 00, 01, 11, 00, 01 ….
d) 00, 10, 11, 00, 10 ….
Correct Answer: B
Detailed Solution:
D-flipflop is a flipflop that produces a delay of exactly one cycle to the CLK.
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QUESTION 9:
A 4-bit shift register is initially loaded with the bit pattern 1010. The register is
clocked repeatedly, and with each clock pulse, the entire pattern shifts one position
to the right; the serial input (leftmost bit) receives the XOR of certain register
outputs (as shown in the feedback loop). After how many clock pulses will the
register content once again become 1010?
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a) 5
b) 7
c) 9
d) 11
Correct Answer: (b)
Detailed Solution:
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Total no. of clock 7.
QUESTION 10:
The following state diagram represents which of the input equation. ( Given D A : [A,
x, y ] ) Where DA denotes a DFF with output A. The x and y are the inputs to the
circuit.
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a)
b)
c)
d)
Correct Answer: C
Detailed Solution:
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QUESTION 11:
The diagram is shown is of a / an _____________
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a) Asynchronous Counter
b) Ring Counter
c) Synchronous Counter
d) Combinational Circuit
Correct Answer: a
Detailed Solution: Follow the lecture material.
QUESTION 12:
Assume initial contents of all D flip-flops are reset to logic 0. The serial input is tied
to logic 1. What are the contents of the registers after three clock cycles?
a) 1100
b) 1110
c) 1011
d) 0011
Correct Answer: b
Detailed Solution:
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This is a 4-bit serial-in, serial-out shift register built from D flip-flops. All flip-
flops are initially reset to 0. The serial input (SI) is tied to logic 1. On every clock
edge, each flip-flop captures the value from the left.
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QUESTION 13:
A three bit shift register is shown below. To have content 000 again, the number of
clock pulses required would be:
a) 2
b) 3
c) 6
d) 7
Correct Answer: C
Detailed Solution:
D - flipflos Truth Table and circuit diagram are shown below :
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When CP =1 then Q = 0 for D = 0
Q1+ = D1 = Q3
Q2+ = D2 = Q1
Q3+ = D3 = Q2
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From the above table, it is clear that the content 0 0 0 will repeat after 6 th clock
pulse.
QUESTION 14:
A counter is constructed with three D flip-flops. The input-output pairs are named
(D0, Q0), (D1, Q1), (D2, Q2), where the subscripts 0 denotes the least significant bit.
The output sequence is desired to be the grey code sequence 000, 001, 011, 010,
110, 111, 101, and 100 repeating periodically. Note that the bits are listed in the
Q2Q1Q0 format. The combinational logic expression for D 1 is,
a)
b)
c)
d) +
Correct Answer: D
Detailed Solution:
Given
000 → 001 → 011 → 010 → 110 →111 → 101 → 100 → 000 → ……….
Table for given condition
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Present State Next state
Q2 Q1 Q0 Q2+ Q1+ Q0+ D2 D1 D0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 1
0 1 1 0 1 0 0 1 0
0 1 0 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1
1 1 1 1 0 1 1 0 1
1 0 1 1 0 0 1 0 0
1 0 0 0 0 0 0 0 0
D1 will have high logic at (1, 3 , 2 , 6) → D1 = 𝛴 m(1, 3, 2, 6)
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QUESTION 15:
The group of bits 01100 is serially shifted (right-most bit first) into 1 5 bits parallel
output shift register with an initial state of 01011. What is the value contained in the
register after 2 clock pulses?
A) 00001
B) 00010
C) 10001
D) 10011
Correct Answer: B
Detailed Solution:
The register consists of four flip-flop stages labelled A, B, C, D. Data in is loaded
serially into stage A with each clock pulse. The output of each stage (QA, QB, QC, QD)
represents the parallel data outputs available at any time.
After the necessary number of clock pulses, the data word can be read in parallel at
these output pins. Key Points from the Image Serial Input: Data is introduced
gradually, one bit per clock pulse, into the first flip-flop.
Parallel Output: Once data filling is complete, all bits can be accessed simultaneously
from the outputs of the flip-flops. Stage Connection: The first flip-flop receives the
serial data, while subsequent flip-flops receive data from the output of the preceding
stage.
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