 Course code : AM522I2A

Course Name : ADVANCED RISC MACHINES

Course Code : AM522I2A
 Text book :
1. Andrew N Sloss, Dominic Symes and Chris Wright, ARM system
developers guide, Elsevier, Morgan Kaufman publishers, 2008
2. Pete Warden, Daniel Situnayake - "TinyML: Machine Learning with
TensorFlow Lite on Arduino and Ultra-Low-Power Microcontrollers"
(O'Reilly Media, 2019)

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 MODULE – 1
PART 1
ARM EMBEDDED SYSTEMS

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 INTRODUCTION TO ARM
• “Acorn Computers Ltd. (Cambridge, England) Nov.
1990
• First called Acorn RISC Machine, then Advanced RISC
Machine
• Based on RISC architecture work done at UCal Berkley
and Stanford
• ARM cores are widely used in mobile phones,
handheld organizers, and a multitude of other
everyday portable consumer devices.
• Optimized for low power & performance

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 ARM PRODUCTS

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 ARM PRODUCT EXAMPLE

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
BRIEF HISTORY OF ARM CORE
• 1985, First ARM (ARM1)
• 1995, ARM7TDMI (Thumb instruction , Debugger,
Multiplier , In circuit emulator )
– Most successful ARM core
– 3-stage pipeline, 120 Dhrystone MIPS (VAX 11/780)
• 1997, ARM9
– 5-stage pipeline
– Harvard (I+D cache), MMU (OS’s VM)
• 1999, ARM10
– 6-stage pipeline
– VFP(Vector Float Point) (7-stage pipeline)
• 2003, ARM11
– 8-stage pipeline
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
Mr. Sharathchandra N R, Department of
Sahyadri College of Engineering and Management
CSE ( AI & ML )
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 CISC VS. RISC

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 THE RISC DESIGN PHILOSOPHY
• The ARM core uses a RISC architecture.
• RISC aimed at delivering
– simple and powerful instructions that execute
within a single cycle at a high clock speed.
– As it provides greater flexibility and intelligence in
software rather than hardware.
• CISC relies more on the hardware for instruction
functionality

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 RISC DESIGN RULES
• Four major design rules:
1. Instructions—
• Has a reduced number of instruction classes.
• These classes provide simple operations that can
each execute in a single cycle.
• Complicated instructions are synthesized by
combining simpler instructions.
• Each instruction has fixed length- For Pipelining
concept.
Note: In CISC –variation in length and no. of cycles for
execution.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 RISC DESIGN RULES
2. Pipelines:
– The processing of instructions is broken down into
smaller units that can be executed in parallel by
pipelines.
– Ideally the pipeline advances by one step on each
cycle for maximum throughput.
– Instructions can be decoded in one pipeline stage.
Note: In CISC – An instruction is executed by a miniprogram
called microcode.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 RISC DESIGN RULES
3. Registers
– RISC machines have a large general-purpose
register set.
– Any register can contain either data or an address.
– Registers act as the fast local memory store for all
data processing operations.
Note: In CISC – dedicated registers for specific
purposes.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 RISC DESIGN RULES
4. Load-store architecture:
– The processor operates on data held in registers.
– Separate load and store instructions transfer data
between the register bank and external memory.
– As memory accesses are costly, they perform
operations only on register data.
Note: In CISC – data processing operations can act
on memory directly.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 THE ARM DESIGN PHILOSOPHY
• Physical features of ARM processor design:
1. Power: The ARM processor has been specifically
designed to be small to reduce power
consumption and extend battery operation
• essential for applications such as mobile phones and
personal digital assistants (PDAs).
2. High Code Density: since embedded systems
have limited memory
• due to cost and/or physical size restrictions.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 PHYSICAL FEATURES OF ARM
PROCESSOR DESIGN
3. Price sensitive :
§ use slow and low-cost memory devices.
4. Reduce the area of the die :
– For a single-chip solution, the smaller the area
used by the embedded processor, the more
available space for specialized peripherals.
– This in turn reduces the cost.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
PHYSICAL FEATURES OF ARM
PROCESSOR DESIGN
5. Debug technology within the processor:
– So the software engineers can view what is
happening while the processor is executing code.
With greater visibility.
– software engineers can resolve issues faster
– Hence reduces development costs.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
PHYSICAL FEATURES OF ARM
PROCESSOR DESIGN
• Note: The ARM core is not a pure RISC
architecture:
a. Primary application is the embedded system.
b. In some sense the strength of the ARM core is
that it does not take the RISC concept too far.
c. In today’s systems the key is not raw processor
speed but total effective system performance and
power consumption.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
INSTRUCTION SET FOR EMBEDDED
SYSTEMS
1. Variable cycle execution for certain
instructions:
– Not every ARM instruction executes in a single
cycle.
– For example, load-store-multiple instructions
vary in the number of execution cycles
depending upon the number of registers being
transferred.(Mainly depends on whether the
access is sequential/random)

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
INSTRUCTION SET FOR EMBEDDED
SYSTEMS
[Link] barrel shifter leading to more complex
instructions:
– The inline barrel shifter is a hardware component
that preprocesses one of the input registers
before it is used by an instruction.
– This expands the capability of many instructions to
improve core performance and code density.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
INSTRUCTION SET FOR
EMBEDDED SYSTEMS
3. Thumb 16-bit instruction set:
– ARM enhanced the processor core by adding a
second 16-bit instruction set called Thumb that
permits the ARM core to execute either 16- or 32-
bit instructions.
– The 16-bit instructions improve code density by
about 30% over 32-bit fixed-length instructions.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
INSTRUCTION SET FOR EMBEDDED
SYSTEMS
4. Conditional execution:
– An instruction is only executed when a specific condition
has been satisfied.
– This feature improves performance and code density by
reducing branch instructions.
5. Enhanced instructions:
– The enhanced digital signal processor (DSP) instructions
were added to the standard ARM instruction set to
support fast 16×16-bit multiplier operations and
saturation.
– These instructions allow a faster-performing ARM
processor.
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
EMBEDDED SYSTEM HARDWARE

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 EMBEDDED SYSTEM HARDWARE
• Each box represents a feature or function.
• The lines connecting the boxes are the buses
carrying data.
• The device into four main hardware
components:
– ARM processor
– Controllers
– Peripherals
– Bus
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 EMBEDDED SYSTEM HARDWARE
1. ARM Processor :
– An ARM processor comprises a core (the
execution engine that processes instructions and
manipulates data)
– It is surrounded with components that interface it
with a bus.
– These components can include memory
management and caches.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 EMBEDDED SYSTEM HARDWARE
2. Controllers:
– Coordinates important functional blocks of the system.
– 2 Controllers:
• Interrupt controllers
• memory controllers
3. Peripherals:
– Required for input-output operation external to the chip
4. A bus :
– Used to communicate between different parts of the
device

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 ARM BUS TECHNOLOGY
• Embedded systems use different bus technologies than those
designed for x86 PC.
– Embedded device use an on-chip bus
– Core is master who initiates a data transfer.
• A Bus has two architecture levels
– The First is a physical level that covers the electrical
characteristics and bus width (16, 32, or 64 bits).
– The Second level deals with protocol.– the logical rules
governing the communication between processor and
peripheral.
• ARM seldom implements the electrical characteristics of the
bus, but it routinely specifies the bus protocol.
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 AMBA BUS PROTOCOL
• AMBA: Advanced Micro controller Bus Architecture
– 1996, it’s introduced and widely adopted as the on-chip bus architecture
for ARM processors.
– The first AMBA buses introduced were
• ASB : Advanced System Bus, and
• APB : Advanced Peripheral Bus
– Later, ARM introduced another bus design
• AHB: Advacned High-performance Bus

• Using AMBA
– Peripheral designers can reuse the same design on multiple projects (with
different processor architecture).
– Plug-and-play

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 AMBA BUS PROTOCOL
• AHB
– provides higher data throughput than ASB. Because
• It use a Centralized Multiplexed Bus Scheme
• This change allows the AHB bus to run at higher clock speed.
• 64/128 bits width.

• Two variations on the AHB bus

• Multi-layer AHB, and
– allows multiple active bus masters,
• AHB-Lite: only one master

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 MEMORY
• Memory is necessary
– An embedded system has to have some form of
memory to store and execute code.
• You have to consider
– price, performance and power consumption
• Specific memory characteristics
– hierarchy, width, and type

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 MEMORY(HIERARCHY)
• Cache
– is used to speed up data transfer between Core and Main
Memory (DRAM)
• But,
– It makes the performance unpredicted
– It doesn’t help Real-Time system response
• Note that many small embedded systems do not require the
benefit of a cache.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 MEMORY(WIDTH)
• Memory width :
– In number of bits the memory returns on each access
• 8, 16, 32, or 64 bits.
– 32-bit ARM instructions and 16-bit-wide memory chips:
• then the processor will have to make two memory
fetches per instruction. Each fetch requires two 16-bit
loads.
– Hence it is better to have 16-bit Thumb instructions with 16-
bit-wide memory .

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 MEMORY(TYPES)
• DRAM
– the most commonly used RAM for devices;
– Dynamic: need to have its storage cells refreshed and given a new
electronic charge every few milliseconds, so you need to set up a
DRAM controller before using the memory.
• SRAM
– is faster than the more traditional DRAM (SRAM does not require a
pause between data access).
• SDRAM
– is one of many subcategories of DRAM.
– accessed pipelined, transferred in a burst.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 PERIPHERALS
• Embedded system that interact with the outside world need
some form of peripheral device.
– Peripherals range from a simple serial communication device to a more
complex 802.11 wireless device.

• All ARM peripherals are memory mapped – the programming

interface is a set of memory addressed register.

• Controllers are specialized peripherals that implement higher

level of functionality within an embedded system.
– Two important types of controllers are
• Memory Controller
• Interrupt Controller
– Normal IC
– Vectoring IC

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
PERIPHERALS (MEMORY CONTROLLER)
• Memory Controllers: Connect different types of
memory to the processor bus.
– On power-up a memory controller is configured in
hardware to allow certain memory device to be active.
These memory devices allow the initialization code to be
executed.
– Some memory devices must be set up by software.
• e.g. When using DRAM, you first have to set up the memory
timings and refresh rate before it can be accessed.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
PERIPHERALS (INTERRUPTCONTROLLER)
• When a peripheral or device requires attention,
– it raise an interrupt to the processor.
• An interrupt controller
– provides a programmable governing policy

• There are two types of interrupt controller available for the

ARM processor
– Standard interrupt controller
• Sends an interrupt signal; Can be programmed to ignore or mask an
individual or set of devices.
• It’s interrupt handler determines which device requiring service.

– Vector interrupt controller (VIC)

• Associate a “priority” and a “handler address” to each interrupt.
• Depending on its type, VIC will either call the standard interrupt exception
handler (loading the handler address from VIC) or cause core to jump to
the handler for the device directly.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 EMBEDDED SYSTEM
SOFTWARE
• An embedded system needs software to drive it.
• There are four typical software components required
to control an embedded device.
• Each software component in the stack uses a higher level of
abstraction to separate the code from the hardware device.
– Initialization Code (e.g. Boot loader)
– Operating System
– Device Drivers
– Application

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 INITIALIZATION (BOOT)
CODE
• Initialization code (or boot code)
– takes the processor from the reset state to a state where the
operating system can run.
• Configuring memory controller, caches
• Initializing some devices
• Debug Monitor (replace OS in simple system)
• Three phases
– Initial hardware configuration
• Satisfy the requirements of the booted image
– e.g. re-organization of the memory map
– Diagnostics
• Fault identification and isolation
– Booting
• Loading an image and handing control over to the image
• The boot process may be complicated if the system must boot
different operating systems or different versions of the same
operating system.
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
INITIALIZATION (BOOT) CODE
EXAMPLE: MEMORY REORGANIZATION
• Start from ROM
• Remap to RAM
– easy IVT
modification

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 OPERATING SYSTEM
• OS organizes the system resources
– peripherals, memory, and processing time
• With an OS controlling these resources, they can be
efficiently used by different applications running within
the OS environment.
• ARM processors support over 50 OSes
– Two main categories: RTOS, platform OS
• RTOS: guarantee response times to event
• platform OS: require MMU(Memory Mgmt Unit ) and
tend to have secondary storage (for large application).
– These two categories of OSes are not mutually exclusive.
– ARM has developed a set of processor cores that
specially target each category.
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 APPLICATIONS
• The OS schedules applications
– code dedicated to handling a particular task.
• ARM processors are found in numerous
market segments, including
– networking, automotive, mobile and consumer
devices, mass storage, and imaging.
• In contrast, ARM processors are not found in
applications that require leading-edge high
performance.(Because they will be low
volume and high cost)
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
ARM PROCESSOR FUNDAMENTALS
DATA-PATH IN ARM

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 REGISTERS
• OrthogonalRegisters
(ref. VAX, PDP-11)
– We say R0~R13 are orthogonal, for
given instruction, if it can use R0, then
others can also be used.
• SPRs
– R13(stack pointer), R14(link register),
R15(program counter)
• Current PSR/Saved PSR
– Condition Codes: N, Z, C, V
– Interruption mask: I(IRQ), F(FIQ)
– Thumb Enable Bit
– Mode( 5 bit )
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 CURRENT PROGRAM
STATUS REGISTER
• cpsr :
– Divided into four fields, each 8 bits wide:
• flags, status, extension, and control.
– The control field contains the processor mode,
state, and interrupt mask bits.
– The flags field contains the condition flags.
• Condition Codes: N, Z, C, V
• Interruption mask: I(IRQ), F(FIQ)
• Thumb Enable Bit
• Mode(5-bit)
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 CURRENT PROGRAM
STATUS REGISTER
• The cpsr :Dedicated 32-bit register and resides
in the register file

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
Mr. Sharathchandra N R, Department of
Sahyadri College of Engineering and Management
CSE ( AI & ML )
 CONDITION FLAGS

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 PROCESSOR MODES
• Determines which registers are active and the
access rights to the cpsr register
• Two modes: either privileged or nonprivileged
– A privileged mode allows full read-write access to
the cpsr.
– In nonprivileged mode only allows read access to
the control field in the cpsr but still allows read-
write access to the condition flags.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 PROCESSOR MODES
• There are seven processor modes in total:
– six privileged modes
• abort, fast interrupt request, interrupt request,
supervisor, system, and undefined) one nonprivileged
mode
– one nonprivileged mode
• user

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 BANKED REGISTERS

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 BANKED REGISTERS
• 37 registers in the register file:
– 20 registers are hidden
• (Banked Registers-shaded in diagram)

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 BANKED REGISTERS
• As per the diagram the
change of mode from
user->IRQ
• - values of register
changes

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 STATE AND INSTRUCTION SETS
• There are three instruction sets: ARM, Thumb,
and Jazelle.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
STATE AND INSTRUCTION SETS

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 INTERRUPT MASKS
• Interrupt masks are used to stop specific
interrupt requests from interrupting the
processor.
• Two interrupt request levels available on the
– interrupt request (IRQ) (I bit=1)
– fast interrupt request (FIQ) (F bit=1)

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 CONDITION FLAGS

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 CONDITIONAL EXECUTION

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 PIPELINE
• A pipeline is the mechanism a RISC processor
uses to execute instructions.
– Using a pipeline speeds up execution by fetching
the next instruction while other instructions are
being decoded and executed.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 PIPELINE(EXAMPLE)

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 PIPELINE
• ARM7
– 3 stages: Fetch, Decode, Execute
• More stages (deeper pipeline)
– means “More latency”, “More Dependence”
• ARM9 (+13% ARM7)
– 5 stages: FI, DI, EX, M, WB
• ARM10 (+34% ARM7)
– 6 stages: FI, Issue, DI, EX, M, WB
• ARM7 instruction runs on ARM9/10 ?
– Yes, same pipeline architecture as ARM7
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 PIPELINE(EXAMPLE)

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 PIPELINE EXECUTING
CHARACTERISTICS

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 EXCEPTIONS, INTERRUPTS,
AND THE VECTOR TABLE
• When an exception or interrupt occurs:
– the processor sets the pc to a specific memory
address.
– The address is within a special address range
called the vector table. The entries in the vector
table are instructions that branch to specific
routines designed to handle a particular exception
or interrupt.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
EXCEPTIONS, INTERRUPTS,
AND THE VECTOR TABLE

• The memory map address 0x00000000

– Is reserved for the vector table, a set of 32-bit
words.
– the vector table can be optionally located at a
higher address in memory (starting at the offset
0xffff0000)

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 VECTOR TABLE (ENTRIES)
Each vector table entry contains a form of branch instruction pointing to the
start of a specific routine:
•Reset vector
– It is the location of 1st instruction after power-up;
•Undefined instruction vector
– Is used when processor cannot decoded instruction.
•Software interrupt vector is called when:
– SWI instruction being executed(To invoke OS routine)
•Prefetch Abort vector (PABT) occurs :
– try to access invalidaddress for instruction;
•Data Abort (DABT)
– Try to access invalid address for data;
•IRQ
•FIQ
Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 CORE EXTENSIONS
• Cache & Tightly Coupled Memory(TCM)
– Unified vs. I/D
– TCM: fast SRAM, very near Core (unwired with AMBA)

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 CORE EXTENSIONS

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
 CORE EXTENSIONS
• Memory Management interface
– No MM: for simple embedded system;
– MPU(Memory Protect Unit): section protection;
– MMU is an h/w available on ARM: Translation table to provide Fine-grain
protection on memory (Virtual- Physical address Map)
• Coprocessor interface
• The coprocessor can be accessed through a group of dedicated ARM instructions
that provide a load-store type interface.
– By Extend Instruction Set vs. CSR register;
– E.g.
• CP15: cache, TCM and MMU via load/store like instr.

Mr. Sharathchandra N R, Department of CSE ( AI & ML ) Sahyadri College of Engineering and Management
THANK YOU
ALL THE BEST

Mr. Sharathchandra N R

Assistant Professor at Department of CSE ( AI & ML)

Managing Director at Samanvaya Sahyadri Tech LLP

Sahyadri College of Engineering and Management, Mangalore

Mob : +91 9740069397

Email : [Link]@[Link]