Advanced Microprocessors – Model Answers
Q.1 Attempt any six of the following (6 Marks)
(i) The virtual memory accessible by 80386 is: 64 TB. Explanation: The Intel 80386 supports 32-bit
addressing with paging and segmentation. The virtual address space is 2^46 bytes = 64 TB.
(ii) Which of the following is not a machine controlled instruction? → ESC. Explanation: ESC (Escape) is
used to pass instructions to a coprocessor, not directly controlled by CPU machine instructions.
(iii) The bit which is used by REP instruction is: Zero Flag (ZF). Explanation: REP (Repeat) instruction
uses CX register as counter and checks the Zero Flag for string operations like REPE/REPNE.
(iv) The physical address of memory addressed by 8086 is: 20-bit. Explanation: The 8086 has 20
address lines, so it can directly access 2^20 = 1 MB of memory.
(v) The status bit which is used by REP instruction is: Zero Flag (ZF).
(vi) For 8086 Microprocessor, the data segment may have maximum memory: 64 KB. Explanation:
Each segment in 8086 can be of maximum 64 KB size.
(vii) The assembler directive which defines ENDS is: END of Segment. Explanation: ENDS marks the
end of a segment definition.
(viii) Which one is not a type of Procedure? → None of these. Explanation: All three are valid procedure
types in 8086.
Q.2 Attempt any three of the following (6 Marks)
(a) Physical Address: It is the actual location in memory hardware where data or instructions are stored.
In 8086, Physical Address = (Segment × 10H) + Offset, allowing 1 MB addressing.
(b) Minimum & Maximum Mode: Decided by MN/MX# pin. Logic 1 = Minimum mode (single processor).
Logic 0 = Maximum mode (multiprocessor).
(c) REP Prefix: A prefix used with string instructions. It repeats until CX=0. Variants REPE/REPZ and
REPNE/REPNZ depend on Zero Flag.
(d) Difference between GPR and Segment Register: GPRs (AX, BX, CX, DX) used for arithmetic/data,
can be divided (AH/AL). Segment registers (CS, DS, SS, ES) hold base addresses, strictly 16-bit.
Q.3 Attempt any three of the following (6 Marks)
(a) ALP to add two 16-bit numbers: MOV AX,[NUM1]; ADD AX,[NUM2]; MOV [RESULT],AX; HLT. This
loads two numbers, adds, and stores result.
(b) Function of RESET and ALE: RESET initializes processor, clears IP, CS, flags. ALE separates
address and data from multiplexed bus.
(c) ROR Instruction: Rotates bits to right. Example: AL=10110001b → after ROR AL,1 →
AL=11011000b.
Q.4 Attempt any two of the following (8 Marks)
(a) Protected Mode of 80386: Supports 32-bit address space (4 GB) and 64 TB virtual memory.
Provides memory protection, multitasking, paging, and privilege levels. Used in modern OS like
Windows/Linux.
(b) Features of Pentium Processor: 1) Superscalar architecture with dual pipelines. 2) 64-bit data bus,
32-bit address bus. 3) On-chip FPU. 4) Branch prediction and cache memory.
(c) Minimum vs Maximum Mode of 8086: Minimum = single processor, control signals by CPU.
Maximum = multiprocessor, external controller 8288. Minimum is simpler; maximum supports complex
systems.
(d) AAA Instruction: ASCII Adjust after Addition. Corrects AL register result after adding ASCII decimal
numbers. Example: If AL=35H+38H, after AAA → AL=03H and AH incremented.
Q.5 Attempt any one of the following (6 Marks)
(a) Internal Architecture of 8086: 8086 has 20-bit address and 16-bit data bus (1 MB memory). Divided
into Bus Interface Unit (BIU) and Execution Unit (EU). BIU handles address generation, instruction
fetch, segment registers, queue. EU executes instructions, contains ALU, registers, flags. Pipelined
architecture increases speed.
(b) ALP to find smallest number in array: MOV CX,10; LEA SI,ARRAY; MOV AL,[SI]; DEC CX; NEXT:
INC SI; CMP AL,[SI]; JBE SKIP; MOV AL,[SI]; SKIP: LOOP NEXT; MOV [RESULT],AL; HLT. This
compares each element and stores smallest.
(c) Physical Memory Organization of 8086: 8086 has 20 address lines (1 MB). Memory divided into 64
KB segments: Code (CS), Data (DS), Stack (SS), Extra (ES). Segment registers hold base addresses,
offsets provide location. Enables modular programming and efficient memory use.