module andGate(
input a ,b,
output y
);
and (y , a , b);
endmodule
module tb;
reg a, b;
wire y;
andGate and_l(a, b, y); // function call
initial
begin
a = 0; b= 0;
#10
a = 0; b= 1;
#10
a = 1; b= 0;
#10
a = 1; b= 1;
#10;
end
endmodule
-----------------------------------------------------------------------------------------------------------------------------
module half_adder(input a, b, output s, Cout);
assign S = a ^ b;
assign Cout = a & b;
endmodule
----------------------
test bench code= Half Adder
module tb_top;
reg a, b;
wire s, c_out;
half_adder ha(a, b, s, c_out);
initial begin
$monitor("At time %0t: a=%b b=%b, sum=%b, carry=%b",$time, a,b,s,c_out);
a = 0; b = 0;
#1;
a = 0; b = 1;
#1;
a = 1; b = 0;
#1;
a = 1; b = 1;
end
endmodule
----------------------------------------------------------------------------------------------------------------------------
module full_adder(input a, b, cin, output S, Cout);
assign S = a ^ b ^ cin;
assign Cout = (a & b) | (b & cin) | (a & cin);
endmodule
------------------------------------------------------------
Test bench code=Full Adder
module tb_top;
reg a, b, c;
wire s, c_out;
full_adder fa(a, b, c, s, c_out);
initial begin
$monitor("At time %0t: a=%b b=%b, cin=%b, sum=%b, carry=%b",$time, a,b,c,s,c_out);
a = 0; b = 0; c = 0; #1;
a = 0; b = 0; c = 1; #1;
a = 0; b = 1; c = 0; #1;
a = 0; b = 1; c = 1; #1;
a = 1; b = 0; c = 0; #1;
a = 1; b = 0; c = 1; #1;
a = 1; b = 1; c = 0; #1;
a = 1; b = 1; c = 1;
end
endmodule
----------------------
Output
----------
At time 0: a=0 b=0, cin=0, sum=0, carry=0
At time 1: a=0 b=0, cin=1, sum=1, carry=0
At time 2: a=0 b=1, cin=0, sum=1, carry=0
At time 3: a=0 b=1, cin=1, sum=0, carry=1
At time 4: a=1 b=0, cin=0, sum=1, carry=0
At time 5: a=1 b=0, cin=1, sum=0, carry=1
At time 6: a=1 b=1, cin=0, sum=0, carry=1
At time 7: a=1 b=1, cin=1, sum=1, carry=1