Hardware Debugging
© Copyright 2018 Xilinx
Objectives
˃ After completing this module, you will be able to:
Understand the key benefits provided by the Vivado logic debug feature
List various debugging cores and their functionality
Describe the process of including debug tool sampling cores in the Vivado Design Suite
Hardware Debugging 17-2
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Outline
˃ Introduction
˃ Logic Debug Cores
˃ Logic Debug Probing Flows
˃ Summary
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Debug and Verification is Critical
Final Device
˃ Debug and verification can account for over
40% of creating a FPGA design
Design Verification
˃ Serial nature of debug and verification can and Debug
make it difficult to optimize 40%
of
Design
˃ Inefficient strategy may result in product Time
launch delay
Design
Implementation
Design
Specification
Hardware Debugging 17-4
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Recommended Debug Methodology
˃ Engineers are trained to solve problems logically Create
Break a problem into smaller parts design
Simplify by reducing variables & variation
Make a prediction, verify the results
Plan how and where to debug early in the design Probe &
cycles Implement
Fix design
˃ FPGA design is an iterative process
Bug
˃ Debugging a FPGA design is an iterative process
1) Probe: Adding/modify debug probes
2) Implement: Compile design w/probes
3) Analyze: Look for bugs using probes Find Download &
4) Fix: Fix any bugs, repeat as necessary Bug Analyze
Design
in HW
The reconfigurable nature of FPGAs
Finish Design:
facilitates the iterative debug process No bugs!
Hardware Debugging 17-5
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Xilinx Hardware Solutions for Debugging Designs
˃ Hardware debugging tool
Vivado logic analyzer for hardware
Functionally replaces need for external logic analyzer
˃ Now included in the Xilinx tool suite
˃ A single JTAG connection to the PC can be used for
Programming the programmable logic
Hardware debugging
Hardware Debugging 17-6
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Vivado Logic Analyzer Feature Overview
˃ Run-time software interface for interacting with ILA and VIO cores
˃ Supports simultaneous ILA waveform viewers
˃ Waveform formats can be saved and applied later for quick configurations
Hardware Debugging 17-7
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Vivado Logic Analyzer Feature
Common Waveform Viewer
˃ Shared across Vivado features
Simulator, Logic Analyzer, etc.
Reduces learning curve
Eases transition between features
˃ New functionality
Cursors and markers w/measure
Zoom mouse gestures
Custom colors
Find next/previous transition
Find signal name
Multiple radix selections
Integrated analog plot w/row resize
Hardware Debugging 17-8
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Vivado Logic Analyzer Feature
Tcl Scripting
˃ Enables automation of logic debug
Uses common Vivado Tcl engine and concepts
Run tests in interactive or batch mode
Save results for future viewing
˃ Allows you to create custom functions and
tests
Create repeatable tests
Link custom Tcl to toolbar buttons in Vivado
IDE
More easily integrate into custom test
environments
Hardware Debugging 17-9
© Copyright 2018 Xilinx
Benefits of Vivado Logic Debug
Simplified Debugging
˃ Single trigger comparator type (a.k.a. “match unit”) per PROBE
All comparison types, bit values
˃ No ICON core instantiation required
Handled by auto detection and connections during implementation
˃ Most debug parameters are set during runtime
Minimize unnecessary re-implementation
Focus on
debugging the
design,
not on the debug
core!
Hardware Debugging 17-10
© Copyright 2018 Xilinx
Benefits of Vivado Logic Debug
High-level Debugging Debug Probe
HDL
entity FIR is
˃ Flexible, targeted probing of HDL design using port (clk : in
rst : in
MARK_DEBUG property din : in
Hierarchy Schematic
˃ Synthesized design probing in multiple views
˃ System-level probing inside of IP integrator
view
Vivado IP Integrator
Debug the design at the appropriate level
Hardware Debugging 17-11
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Logic Debug Cores
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Vivado Integrated Logic Analyzer System
˃ Vivado Design Suite debug cores provide
internal visibility to all soft IP VIO
Access to hard IP ports
Accesses all the internal signals, interfaces
ports and nodes within the programmable logic
(ILA v5.x)
Stimulus can be applied using the Virtual I/O
core (VIO v3.x)
˃ Debugging occurs at, or near, system
speeds
Debug on-chip using the system clock
˃ Minimize pins needed for debugging
Access via the JTAG interface
(debug_core_hub)
Hardware Debugging 17-13
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Vivado Logic Debug IP
˃ ILA 6.2 ILA 6.2 and VIO 3.0 ILA 6.2
Vivado native Integrated Logic HDL Instantiation Netlist Insertion
Analyzer debug IP core
Netlist insertion support Mark Debug Nets
HDL instantiation support
˃ VIO 3.0
Vivado native Virtual Input / Output
debug IP core
HDL instantiation
Hardware Debugging 17-14
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ILA Core
˃ Used for monitoring internal programmable logic signals and ports for post-analysis
˃ Multiple configurable ILA trigger units
Configurable trigger input widths and match types for use with different input signals types
˃ Separate data and trigger inputs
˃ Sequential triggering
˃ Storage qualification
˃ Trigger out signal for cross-probing
˃ Pre- and post-trigger buffering (capture data
before, during, and after trigger condition is met)
Hardware Debugging 17-15
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VIO Core
˃ Support for monitoring and driving internal programmable logic signals in "real time"
˃ Probe input unit
˃ Probe output unit
Hardware Debugging 17-16
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Mark Debug
˃ Besides the IP cores insertion, Vivado logic debugging can be done by making nets
in the HDL code using Mark Debug property
˃ VHDL syntax example
attribute mark_debug : string;
attribute mark_debug of char_fifo_dout: signal is "true";
˃ Verilog Syntax example
(* mark_debug = "true" *) wire [7:0] char_fifo_dout;
Hardware Debugging 17-17
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Logic Debug Probing Flows
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Vivado Debug Probing Flows
˃ Netlist insertion flow (Highly recommended)
Most flexible with high predictability
Probing at different design levels (HDL, synthesized design, system design)
Compatible with various tool modes (Project, Non-project)
˃ HDL instantiation flow
Traditional flow for highest predictability, moderate flexibility
‒ No longer requires ICON core instance
Probing at HDL design level only
Compatible with various tool modes (Project, Non-project)
˃ Netlist insertion and HDL instantiation flows can be mixed
Hardware Debugging 17-19
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Vivado Debug Tool Access Points
˃ Select Tools > Set up Debug to launch the Vivado Debug Wizard
˃ Debug tab appears in the Synthesized Design view
Click on the Set Up Debug icon to re-launch the wizard
‒ Set up Debug
‒ Create debug core or port
Hardware Debugging 17-20
© Copyright 2018 Xilinx
Selecting Signals to Debug
˃ Multiple ways to select nets in Vivado
Netlist view (nets folders)
‒ Each level of logic hierarchy
Schematic
Find results
˃ Right-click the net and select Mark Debug
˃ Nets added to Unassigned Nets folder in
the
Debug tab view
Placeholder for probable nets prior to
configuring cores
˃ Net name search also in the Set Up Debug
Wizard
Hardware Debugging 17-21
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Debug Tool Configuration
˃ The Vivado tool view displays core content
and configuration
CLK, PROBE
Signal count
˃ Set options for cores and signals in the
Properties view
Hardware Debugging 17-22
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Summary
© Copyright 2018 Xilinx
Summary
˃ Vivado Logic debug features integration, common wave viewer, and Tcl command
˃ Debugging is an integral and important component of embedded system
development
˃ The Vivado logic analyzer provides various cores to view the inside of a design—
from individual signals to bus-level activities
ILA core
VIO core
˃ The Debug Configuration Wizard simplifies hardware connections and logic
analyzer peripheral inclusion
˃ Three Vivado logic debug flows
HDL Instantiation
Netlist insertion
Mark Debug in netlist, schematic, and HDL
Hardware Debugging 17-24
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Adaptable.
Intelligent.
Hardware Debugging 17-25
© Copyright 2018 Xilinx