Intel 8086 microprocessor

Feature:
• The 8086, announced in 1978, was the first 16-bit microprocessor introduced by Intel Corporation.

• 8086 is 16-bit microprocessor.

• 8086 has a 20-bit address bus can access up to 220 memory locations (1 MB).

• Externally the 8086 has a 16-bit data bus 8086 has the ability to address up to 1 Mbyte of memory
and 64K of input/output port.

• The 8086 is manufactured using high-performance metal-oxide semiconductor (HMOS) technology.

• The 8086 is housed in a 40-pin dual inline package and many pins have multiple functions.

Block Diagram:

Internal architecture of 8086

The architecture of 8086 includes-

–Arithmetic Logic Unit (ALU)

– Flags

–General registers

– Instruction byte queue

– Segment registers

The 8086 CPU is divided into two independent functional units-

 [Link] Interface Unit (BIU) [Link] Unit (EU)
The BIU has to interact with memory and input EU is responsible for executing the instructions of
and output devices in fetching the instructions the programs and to carry out the required
and data required by the EU. processing.
The BIU has The Execution Unit (EU) has
– Instruction stream byte queue – Control unit
– A set of segment registers – Instruction decoder
– Instruction pointer – Arithmetic and Logical Unit (ALU)
– General registers
– Flag register
– Pointers
– Index register

Bus Interface Unit (BIU):

Parts Brief Explain
(i) Instruction stream byte A 6-byte queue that stores prefetched instruction bytes to speed up
queue execution by allowing parallel fetch and execute operations.
(ii)A set of segment registers A 6-byte queue that stores prefetched instruction bytes to speed up
execution by allowing parallel fetch and execute operations.
(iii)Instruction pointer A register that contains the offset of the next instruction in the
Code Segment (CS) and helps BIU locate the next instruction.

(i) Instruction Byte Queue:

• 8086 instructions vary from 1 to 6 bytes

• Therefore fetch and execution are taking place concurrently in order to improve the performance of
the microprocessor

• The BIU feeds the instruction stream to the execution unit through a 6 byte prefetch queue

• This prefetch queue can be considered as a form of loosely coupled pipelining.

• Execution and decoding of certain instructions do not require the use of buses

• While such instructions are executed, the BIU fetches up to six instruction bytes for the following
instructions (the subsequent instructions)

• The BIU store these prefetched bytes in a first-in-first out register by name instruction byte queue

• When the EU is ready for its next instruction, it simply reads the instruction byte(s) for the instruction
from the queue in BIU.
(ii) Segment Registers:

Segment Registers are four registers (CS, DS, SS, ES) in the BIU of 8086 that store the base addresses of
memory segments and help generate physical addresses for program instructions, data, and stack
operations.

Segment
Size Contains / Purpose Used / Referenced By Notes
Register
Address of 64 KB segment
CS (Code 16- Points to the starting address of the
containing processor Instruction Pointer (IP)
Segment) bit code segment
instructions

SS (Stack 16- Address of 64 KB stack Stack Pointer (SP) and Base Used to compute the address of the
Segment) bit segment Pointer (BP) stack location to be accessed

General registers (AX, BX, Points to beginning of data segment;

DS (Data 16- Address of 64 KB segment
CX, DX) and Index registers maximum 64 KB; starting address
Segment) bit with program data
(SI, DI) divisible by 16

Address of 64 KB extra data

ES (Extra 16- DI register (especially in Used in string manipulation
segment (usually program
Segment) bit string operations) instructions for extra data access
data)

(iii) Instruction pointer:

The Instruction Pointer (IP) is a 16-bit register in the 8086 microprocessor that holds the offset (address)
of the next instruction to be executed in the Code Segment (CS).

Execution Unit (EU)

The Execution Unit (EU) is the part of the 8086 microprocessor responsible for executing
instructions and performing operations on [Link] works in parallel with the Bus Interface
Unit (BIU), which fetches instructions from memory.

Component Function
Control Unit (CU) Coordinates and controls the operation of all parts of the processor.
Arithmetic and Logic Performs arithmetic operations (addition, subtraction, etc.) and
Unit (ALU) logical operations (AND, OR, NOT, etc.) on data.
Translates instructions fetched from memory into a series of actions
Instruction Decoder
to be executed by the EU.
EU Component Definition Function Example
Control Unit Coordinates and controls all Sends control signals to
–
(CU) operations of the processor execute instructions properly
Translates instructions Directs ALU, registers, and
Instruction
fetched from memory into a other components to perform –
Decoder
set of actions the required tasks
Executes operations on data
Performs arithmetic and
ALU such as addition, subtraction, Addition of AX and BX
logical operations
AND, OR

General Registers that store data or

Acts as operands for ALU and
Purpose intermediate results during AX, BX, CX, DX
temporary storage of results
Registers execution
Indicates results of operations
A special register that stores Zero Flag (ZF), Carry
Flag Register and controls conditional
status and control flags Flag (CF)
operations
Registers that hold memory
Access stack or reference SP (Stack Pointer), BP
Pointers addresses for specific
memory locations (Base Pointer)
purposes

Registers used to modify

Used for memory addressing SI (Source Index), DI
Index Registers addresses or operands in
and string operations (Destination Index)
memory operations

Registers
o Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a
16-bit register BX

o BX register usually contains a data pointer used for based, based indexed or register indirect
addressing

o Count register consists of two 8-bit registers CL and CH, which can be combined together and used as
a 16-bit register CX

o Count register can be used as a counter in string manipulation and shift/rotate instructions.

Functions

o The functions of execution unit are:

• To tell BIU where to fetch the instructions or data from.

• To decode the instructions.

• To execute the instructions.

• The EU contains the control circuitry to perform various internal operations.

• A decoder in EU decodes the instruction fetched memory to generate different internal or external
control signals required to perform the operation.

• EU has 16-bit ALU, which can perform arithmetic and logical operations on 8-bit as well as 16-bit.

Structure:
Comparison Table: 8086 Registers

Type of
Definition Purpose / Function Examples Key Notes
Register

16-bit registers used AX (Accumulator), BX

Perform arithmetic, Often divided into high
for temporary (Base), CX (Count), DX
General logic, data transfer, and low bytes (e.g., AX
storage of data and (Data), SI (Source Index),
Purpose and I/O operations; = AH + AL); used in
intermediate results DI (Destination Index),
Registers can also be used in computations, loops,
during program BP (Base Pointer), SP
memory addressing and string operations
execution (Stack Pointer)

Maintain program IP points to the next

Registers that
control, indicate instruction; FLAGS
Special control the
results of IP (Instruction Pointer), indicate CPU status like
Purpose operation of the
operations, and FLAGS Zero, Carry, Sign,
Registers CPU and store the
manage instruction Overflow, Direction,
status of operations
execution etc.

Used to form the Physical Address =

physical memory CS (Code Segment), DS Segment × 16 + Offset;
Registers that hold
address by (Data Segment), SS separate code, data,
Segment the starting
combining with (Stack Segment), ES stack, and extra
Registers addresses of
offset registers; (Extra Segment), FS, GS segments for
memory segments
enable segmented (80386+) organization and
memory addressing memory protection
General Purpose Registers:

Register Composition Definition / Role Function / Usage Key Notes / Examples

Arithmetic, logic, data Shortest machine code
AX Main arithmetic
AH + AL transfer, I/O operations, generation; used in MUL,
(Accumulator) and logic register
string manipulation DIV; IN AL, 60H
Holds base Used in based,
BX (Base MOV DX, [BX+SI]; can
BH + BL address for based+index, or register
Register) hold memory offset
memory access indirect addressing
Used as counter in Looping (LOOP), repeated
CX (Count Shift/rotate uses CL; LOOP
CH + CL loops and string string instructions (REP),
Register) LABEL; REP MOVS
operations shift/rotate instructions
DX:AX = 32-bit result in
DX (Data Holds data for I/O
DH + DL MUL/DIV; used as port MUL DX; OUT DX, AL
Register) and arithmetic
number in I/O
 Register Composition Definition / Role Function / Usage Key Notes / Examples

SI (Source Pointer to source Source in string operations; MOV AX, [SI]

16-bit
Index) data offset relative to DS
Destination in string
DI (Destination Pointer to MOV [DI], AX
16-bit operations; offset relative to
Index) destination data
ES
Access stack-passed
BP (Base Points to stack- MOV AX, [BP+4]
16-bit parameters; offset relative
Pointer) based parameters
to SS
Maintains LIFO stack
Empty stack → SP =
SP (Stack Points to top of operations; offset relative to
16-bit FFFEh; PUSH/POP
Pointer) stack SS; points to word
operations
boundary

Special Purpose Registers

Register Bits Definition / Role Function / Usage Key Notes / Examples

Points to the next Provides offset address
IP (Instruction 16- Modified by JMP, CALL, or
instruction to be relative to CS; works with
Pointer) bit RET; in real mode
executed CS to fetch instructions
EIP (Extended Points to next Offset within a code Can be changed with
32-
Instruction instruction in segment; controls execution jumps/calls; replaces IP in
bit
Pointer, 80386+) protected mode flow 32-bit mode
SP always points to word
16- Points to top of stack Stack operations: PUSH,
SP (Stack Pointer) boundary; empty stack →
bit memory (LIFO) POP; offset relative to SS
SP = FFFEh

ESP (Extended Points to top of stack

32- Maintains stack operations in Replaces SP in 32-bit
Stack Pointer, in protected/32-bit
bit 32-bit systems protected mode
80386+) mode

Indicates processor Arithmetic/logic results,

16- Includes CF, PF, AF, ZF,
FLAGS status and controls interrupt control, direction,
bit SF, TF, IF, DF, OF
operations trap, overflow, etc.

32- Extended version of Same as FLAGS but with Upward compatible; used
EFLAGS (80386+)
bit FLAGS additional control/status bits in protected/32-bit mode
Segment Registers

Segment
Definition / Purpose Size / Notes
Register
Holds the starting address of the memory segment containing
CS (Code 64 KB in 8086–80286; 4 GB
program instructions. Used together with IP to fetch
Segment) in 80386 and above
instructions.
Contains the starting address of the segment holding most
DS (Data 64 KB in 8086–80286; 4 GB
program data. General-purpose registers access data here by
Segment) in 80386 and above
default.
ES (Extra An additional data segment, often used for destination data in 64 KB in 8086–80286; 4 GB
Segment) string operations. in 80386 and above

SS (Stack Defines the starting address of the stack segment. Stack 64 KB in 8086–80286; 4 GB
Segment) operations (PUSH/POP) reference this segment by default. in 80386 and above

Supplemental segment registers introduced in 80386 and 4 GB each in 80386 and

FS / GS
above for additional memory segment access. above
programming model
The programming model describes the registers and memory organization as seen by a programmer. It
shows how the 8086 CPU interacts with data, addresses, and instructions.

Addressing Modes
• MOV instruction is a common and flexible instruction.

– provides a basis for explanation of data-addressing modes

• Figure 1 illustrates the MOV instruction and defines the direction of data flow.
• Source is to the right and destination the left, next to the opcode MOV

.– an opcode, or operation code, tells the microprocessor which operation to perform