VAISH COLLEGE OF ENGINEERING, ROHTAK
Sessional - 2
Session: 2025-2026
Sem: Ist Program: Course Code: Total Marks: 40 Time:
BCA 25BCA401DS02 1.30 hrs
Course Name: CC102 (Computer Architecture)
PART A
Answer all questions (2.5 Marks Each)
Qn.
CO Level
No.
CO2 Explain the function of the accumulator register in the basic computer
L2 1(a)
design.
CO2 L2 1(b) Explain how pipelining improves CPU performance in RISC processors.
Demonstrate how accumulator logic can be used to perform arithmetic and
CO3 L3 2(a)
logical operations in a basic computer design.
Explain how priority interrupt helps manage multiple interrupt requests
CO3 L3 2(b)
efficiently.
PART B
Attempt any one (15 Marks Each)
Qn.
CO Level No.
Demonstrate how pipelining and parallel execution can enhance CPU
performance, especially in RISC-based systems.
CO3 L3 3 Design and explain the architecture of a basic computer. Discuss in detail
the functions of the accumulator, program counter, instruction register,
control unit, and timing control circuits with neat block diagram.
PART C
Attempt any one (15 Marks Each)
Qn.
CO Level No.
Evaluate how parallel processing improves overall computational
CO4 L4 4 performance. Compare different architectures such as SIMD, MIMD, and
vector processors with appropriate examples.
Evaluate the performance of cache memory in improving CPU
efficiency. Analyze different cache mapping techniques (direct,
associative, and set-associative) with examples.