Module 3

Syllabus
Adders, Subtractors, Comparators, Multiplexers, De-Multiplexers, Encoders, De-coders, Code converters,
Magnitude comparators, Parity generators, parity checkers

Combinational Circuits
Logic circuits for digital systems may be combinational or sequential.
A combinational circuit is the digital logic circuit in which the output depends on the combination of
inputs at that point of time with total disregard to the past state of the inputs. The digital logic gate is the
building block of combinational circuits. The function implemented by combinational circuit depend
upon the Boolean expressions.

Some of the characteristics of combinational circuits are following −

• The output of combinational circuit at any instant of time depends only on the levels present at
input terminals.
• The combinational circuit does not use any memory. The previous state of input does not have any
effect on the present state of the circuit.
• A combinational circuit can have an n number of inputs and m number of outputs.

Some examples of the combinational circuits are adders, subtractors, Multiplexers, demultiplexers,
encoders, decoders etc.

Adders
In electronics, an adder is a digital circuit that performs addition of numbers. In modern computers
and other kinds of processors, adders are used in the arithmetic logic unit (ALU), but also in other
parts of the processor. Adders are combinational circuits. The output of combinational circuits
depends on its present inputs [Link] are two types of Adders:

• Half Adders
• Full Adders
Half Adder
Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit
is designed to add two single bit binary number A and B. It is the basic building block for addition of two
single bit numbers. This circuit has two outputs carry and sum.

 The simplified Boolean functions for the two outputs can be obtained directly from the truth
table. The simplified sum of products expressions are:
S = x’y + xy’
C = xy

Drawbacks of half adder

The major drawback of HALF ADDER circuit is that it can only add two inputs and if there is any carry it
is neglected. Thus, the process is incomplete. To overcome this drawback Full Adder is designed.
Applications of half adders
➢ Half adder is used in ALU (Arithmetic Logic Unit) of computer processors to add binary bits.
➢ Half adder is used to realize full adder circuit.
➢ Half adder is used in calculators.

Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit
A combinational logic circuit that can add two binary digits (bits) and a carry bit, and produces a sum bit
and a carry bit as output is known as a full-adder.
In other words, a combinational circuit which is designed to add three binary digits and produces two
outputs (sum and carry) is known as a full adder. Thus, a full adder circuit adds three binary digits, where
two are the inputs and one is the carry forwarded from the previous addition.
Block Diagram

Truth Table
Applications of full adder
➢ Full adders are used in ALUs (arithmetic logic units) of CPUs of computers.
➢ Full adders are used in calculators.
➢ Full adders also help in carrying out multiplication of binary numbers.
➢ Full adders are also used to realize critic digital circuits like multiplexers.
➢ Full adders are used to generate memory addresses.
➢ Full adders are also used in generation of program counterpoints.
➢ Full adders are also used in GPU (Graphical Processing Unit).
Subtractors
Subtractors are of two types:
➢ Half-subtractor
➢ Full-subtractor

Half- Subtractor
Half subtractor is a combination circuit with two inputs and two outputs that are difference and borrow.
The DIFFERENCE output is the difference between the two input bits, while the BORROW output
indicates the borrow bit. In the subtraction (A-B), A is called a Minuend bit and B is called
a Subtrahend bit.
Block Diagram

Truth Table
Logic Circuit

Full Subtractor
A full subtractor is a combinational circuit that performs subtraction of two bits, one is minuend and other
is subtrahend, considering borrow of the previous adjacent lower minuend bit. This circuit has three inputs
and two outputs. The three inputs A, B and Bin, denote the minuend, subtrahend, and previous borrow,
respectively. The two outputs, D and Bout represent the difference and output borrow, respectively.
Block Diagram

Truth Table
Circuit Diagram

Magnitude Comparators

A magnitude digital Comparator is a combinational circuit that compares two digital or binary numbers to
find out whether one binary number is equal, less than, or greater than the other binary number. We
logically design a circuit for which we will have two inputs one for A and the other for B and have three
output terminals, one for A > B condition, one for A = B condition, and one for A < B condition.
Comparators are used in central processing unit s (CPUs) and microcontrollers (MCUs). Magnitude
Comparator is a combinational circuit capable of comparing the relative magnitude of two binary
numbers.
Figure shows the block diagram of n-bit magnitude comparator. It accepts two n-bit binary numbers, say A
and B as inputs and produces one of the outputs: A>B, A=B and A<B.
One of the outputs will be high depending upon the relative magnitude. That is, output A>B will be high if
A is greater than B, output A=B will be high if A and B are equal, and output A.
Its logic behaviour is same as adder. It does not return sum or carry. Magnitude comparators are used in
central processing units and microcontrollers. This basic circuit for a magnitude comparator can be
extended for any number of bits.
1 bit magnitude comparator
A comparator used to compare two bits is called a single-bit comparator. It consists of two inputs each for
two single-bit numbers and three outputs to generate less than, equal to, and greater than between two
binary numbers.
2-bit Magnitude Comparator
(for your better understanding)
A comparator used to compare two binary numbers each of two bits is called a 2-bit Magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to, and greater than
between two binary numbers.
MULTIPLEXERS
A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line. The selection of a particular input line is controlled by a set of selection
lines. Normally, there are 2 power n input lines and n selection lines whose bit combinations determine
which input is selected.
2:1 Multiplexer
 A 2×1 multiplexer is a combinational logic circuit that has only two inputs, i.e, A0 and A1, 1
selection line, i.e., S0, and single outputs, i.e., Y.
 Based on the combination of inputs that are present at the selection line S0, one of these 2 inputs
forwards to the output line.
 It is the simplest type of multiplexer in digital electronics.
 The 2:1 multiplexer’s block diagram and truth table are shown below.
 4:1 Multiplexer
A 4:1 multiplexer is a combinational logic circuit that selects one input from four inputs, i.e., A0, A1, A2,
and A3 forwards it to the output line, i.e., Y based on the two control signal or selection lines, i.e., S0 and
S1.
Applications of Mux

• Multiplexer is used as data selector device.

• Multiplexers are used in communication systems to increase the efficiency of the system.
• Multiplexers are used in telephone networks for integration of several audio signals on a
single transmission line.
• To maintain large amount of data, multiplexers are also used in computer memory
systems.
• Multiplexers are also employed in TV broadcasting systems.
• Multiplexers are used in satellite communication and GPS (Global Positioning System).
• Multiplexers are also used in PLC (Programmable Logic Control) systems, etc.

Questions
1. Design a 4:1 Multiplexer using 2:1 Multiplexers. Draw the logic diagram, truth table, Boolean
expression and explain the operation.
2. Implement the given Boolean function F(A,B,C) = ∑ (1,3,5,6) using 4:1 multiplexer.
(Refer your class notes for the answers of above questions).
DEMULTIPLEXERS
 A Demultiplexer is a combinational circuit that has only 1 input line and 2N output lines.
 Demux can be thought of as a ‘distributor’.
 Simply, the multiplexer is a single-input and multi-output combinational circuit.
 The information is received from the single input lines and directed to the output line.
  De-multiplexer is opposite to the multiplexer.

1×2 De-multiplexer:
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y0, and Y1, 1 selection lines, i.e., S0, and
single input, i.e., A.
Based on the selection value, the input will be connected to one of the outputs. The block diagram and the
truth table of the 1×2 multiplexer are given below.

Fig:Logic Diagram
 1:4 Demux
 In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y0, Y1, Y2, and Y3, 2 selection lines,
i.e., S0 and S1 and single input, i.e., A.
 On the basis of the combination of inputs which are present at the selection lines S0 and S1, the
input be connected to one of the outputs.
 The block diagram and the truth table of the 1×4 multiplexer is given below.

Fig: Logic Diagram

Applications of Demultiplexer:
1. Demultiplexer is used to connect a single source to multiple destinations. The main application area
of demultiplexer is communication systems where multiplexer are used. Most of the communication
systems are bidirectional i.e. they function in both ways (transmitting and receiving signals). Hence, for
most of the applications, the multiplexer and demultiplexer work in sync. Demultiplexer are also used for
reconstruction of parallel data and ALU circuits.
2. Communication System – Communication systems use multiplexers to carry multiplexers like audio,
video and other forms of data using a single line for transmission. This process makes the transmission
easier. The demultiplexer receives the output signals of the multiplexer and converts them back to the
original form of the Function implementation using 8x1 MUX data at the receiving end. The multiplexer
and demultiplexer work together to carry out the process of transmission and reception of data in
communication system.
3. ALU (Arithmetic Logic Unit) – In an ALU circuit, the output of ALU can be stored in multiple registers
or storage units with the help of demultiplexer. The output of ALU is fed as the data input to the
demultiplexer. Each output of demultiplexer is connected to multiple registers which can be stored in the
registers.
4. Serial to parallel converter – A serial to parallel converter is used for reconstructing parallel data from
incoming serial data stream. In this technique, serial data from the incoming serial data stream is given as
data input to the demultiplexer at regular intervals. A counter is attached to the control input of the
demultiplexer. This counter directs the data signal to the output of the demultiplexer where these data
signals are stored. When all data signals have been stored, the output of the demultiplexer can be retrieved
and read out in parallel.

Encoders
 An encoder is a digital circuit(combinational) that converts a set of binary inputs into a unique
binary code.
 The binary code represents the position of the input and is used to identify the specific input that
is active.
 Encoders are commonly used in digital systems to convert a parallel set of inputs into a serial
code.
 It accepts 2 power n input lines out of which one input line is active at a given time and
produces n output lines.
Block Diagram
Types of Encoders
 The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0, and two outputs A1 & A0. At any
time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the output.

Truth Table
 Fig: Logic Circuit
Octal to Binary Encoder (8 to 3 Encoder)
Practice Question
 Design a decimal to BCD enocoder
 Decoders
 The combinational circuit that change the binary information into 2N output lines is known
as Decoders.
 The binary information is passed in the form of N input lines.
 The output lines define the 2N-bit code for the binary information.
 In simple words, the Decoder performs the reverse operation of the Encoder.
 At a time, only one input line is activated for simplicity.
 The produced 2N-bit output code is equivalent to the binary information.

2 to 4 line decoder:
 In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E and four outputs,
i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set to 1, one of
these four outputs will be 1.
Logic Circuit

3 to 8 line decoder:
 The 3 to 8 line decoder is also known as Binary to Octal Decoder.
 In a 3 to 8 line decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and
three outputs, i.e., A0, A1, and A2.
 This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of
these four outputs will be 1.
Logic Circuit

Parity Generator and Parity Checker

 In digital electronic systems, during data transmission and processing, data gets distorted.
 This is due to the noises added to it.
 Such noises change 0s to 1s and 1s to 0s.
 Annoying, right? It is necessary to identify and remove these errors.
  One of the most widely used error detection techniques for transmission of data for sharing
information between devices is Parity checking.
What is a Parity Bit?
 A parity bit is an extra bit in any binary message to make the total number of 1’s either odd or
even.
 We need to add the parity bit to a signal.
 This is done by the Parity generator.
 This parity inclusive binary message then transmits from transmitter to receiver end.
 The Parity Checker matches the number of 1’s at the receiver’s end with that of the transmitter’s
end to check for errors.
 If there is a change in the number of 1s at the receiving end, then that detects the presence of an
error.
What is even parity and odd parity?
 Even parity is the case when the total number of 1s in the sum of data bits and parity bits is even
whereas, in odd parity, it is odd.
Types of Parity
1. odd parity
Here, the target is the make the total number of 1s odd. For example, consider the same message signal
from above. “010”. The parity bit here will be 0.
2. Even Parity
The target is to make the total number of 1s even. For example, if you have a message signal “010”, you
can clearly see that it has just one 1. So we add a parity bit to make it two 1s. Now the number of 1s is
even.
What is the difference between a Parity Generator and a Parity Checker?
 The primary difference between parity generator and a parity checker is that a parity generator is
a combinational logic circuit we use in the generation of the parity bit.
 On the other hand, a parity checker is a circuit that checks the parity (number of 1s) of the
message signal.
 Both these circuits are located at different sites based on their working.
 A parity generator is present at the transmitter end to generate the parity bit. Later it combines
with the message signal.
 The Parity checker is present at the receiver end for error detection through parity bit count.
How does a Parity Generator work?
 Assume that your final message is an n-bit stream of digital data.
  One of the bits is the parity bit.
 To transmit this bitstream containing n-1 data (message signal) plus one additional parity bit, we
require a special circuit known as parity bit generator.
 The parity generator is a combinational logic circuit.
 The parity generators can create two parities. Even parity generates a final message with an even
number of 1s. So the parity bit for an even number of 1s is 0.
 On the other hand, an odd parity bit generates when the total number of 1s in the bitstream is odd.
Even parity Generator
3 bit Even Parity Generator:
 Suppose at the transmitting end, and we have a 3-bit message signal that we wish to transmit
using an even parity bit.
 Let A, B, and C be input bits and P be output that is even parity bit.
 Even parity generates as a result of the calculation of the number of ones in the message bit.
 If the number of 1s is even P gets the value as 0, and if it is odd, then the parity bit P gets the
value 1.
Truth Table
Logic Diagram

Odd Parity Generator

3-bit Odd Parity Generator
 Suppose at the transmitting end now we have a 3-bit message signal, and we wish to transmit it
using odd parity.
 Then, the parity bit generated, P, would be as a result of odd parity generation.
 The total number of 1s in the input bits must be odd for the odd parity bit.
 If the total number of 1s in input bits is odd, then P gets the value 0, and if it is even then, P is
assigned the value 1.
Truth Table
  Solving the truth table for all the cases where P is 1 using Sum-of-Products method:
 P = A ⊕ B Ex-NOR C

Parity Checkers
 It is a logic circuit that checks for possible errors in the transmission. This circuit can be an even
parity checker or odd parity checker depending on the type of parity generated at the transmission
end. When this circuit is used as even parity checker, the number of input bits must always be
even.
Even Parity Checker
 Consider that three input message along with even parity bit is generated at the transmitting end.
These 4 bits are applied as input to the parity checker circuit, which checks the possibility of error
on the data. Since the data is transmitted with even parity, four bits received at circuit must have
an even number of 1s.
 If any error occurs, the received message consists of odd number of 1s. The output of the parity
checker is denoted by PEC (Parity Error Check).
 The below table shows the truth table for the Even Parity Checker in which PEC = 1 if the error
occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no error occurs, i.e., if
the 4-bit message has even number of 1s.
Odd Parity Checker
 Consider that a three-bit message along with odd parity bit is transmitted at the transmitting end.
Odd parity checker circuit receives these 4 bits and checks whether any error are present in the
data.
 If the total number of 1s in the data is odd, then it indicates no error, whereas if the total number of
1s is even then it indicates the error since the data is transmitted with odd parity at transmitting end.
 The below figure shows the truth table for odd parity generator where PEC =1 if the 4-bit message
received consists of even number of 1s (hence the error occurred) and PEC= 0 if the message
contains odd number of 1s (that means no error).