MODULE 3

Basic Structure of Computers: Functional Units, Basic Operational Concepts, Bus structure, Performance
– Processor Clock, Basic Performance Equation, Clock Rate, Performance [Link]
Instructions and Programs: Memory Location and Addresses, Memory Operations, Instruction and
Instruction sequencing, Addressing Modes.
 Basic Operational Concepts/
Basic operations of a computer with a simple
block diagram.

Fig1:It shows the connection between Processor and Memory

❑ PC: Program counter contains the memory address of the instruction to be executed.

❑ MAR: Memory address register holds the address of the location to or from which data are to be transferred.

❑ MDR: Memory data register contains the data to be written or read out of the address location.

❑ IR: The instruction register contains the instruction that is being executed.

❑ ALU: ALU is the part of the computer which performs different basic operation and arithmetic calculation.

❑ CONTROL UNIT

❑ GENERAL PURPOSE REGISTER

•The Program Counter (PC) is a critical component in a
CPU’s control unit. It holds the memory address of the next The Instruction Register (IR) holds the instruction that is
instruction to be fetched and executed by the processor. currently being executed by the CPU.
• Fetching: When the CPU fetches an instruction from
• Instruction Fetching: The PC points to the memory memory (addressed by the Program Counter), it places
location where the next instruction is stored. The CPU that instruction in the IR.
fetches this instruction from memory and increments • Decoding: The control unit decodes the instruction in the
the PC to point to the subsequent instruction. IR to determine what actions the CPU needs to perform,
such as arithmetic, logical operations, memory access, or
• Sequential Execution: In most cases, the PC simply control flow changes.
increments to the next memory address after an • Execution: Once decoded, the CPU executes the
instruction is executed ,allowing the processor to instruction as directed by the IR, using the necessary
execute instructions in sequence. components (like the ALU for arithmetic operations or
• Branching and Jumping: For conditional operations memory for data storage/retrieval).
(like loops or if statements), the PC can be updated to • Updating: After the instruction in the IR is executed, the
point to a different memory address, allowing for IR is updated with the next instruction fetched by the
non-linear execution flows, which is essential for Program Counter.
implementing control structures.
• Interrupt Handling: During an interrupt, the CPU
temporarily stores the current PC value so it can
return to the correct instruction after handling the
interrupt.
Memory Address Register (MAR) is essential in a
CPU for managing data transfers between the The Memory Data Register (MDR), also known as the
processor and memory. Memory Buffer Register (MBR), is crucial in managing data
transfer between the CPU and memory.
❑ Holds Memory Addresses: The MAR stores the ❑ Data Storage for Memory Operations:
memory address of the data or instruction that ▪ For Reading: When the CPU reads data from memory,
needs to be read from or written to memory. the data from the specified memory address is placed in
❑ Fetch and Store Operations: the MDR.
▪ For Reading: When the CPU needs to fetch ▪ For Writing: When the CPU writes data to memory, it
data or an instruction from memory, it places the data into the MDR, which is then transferred
places the target memory address in the to the specified memory address.
MAR. ❑ Works with the Memory Address Register (MAR):
▪ For Writing: When the CPU needs to store ▪ The MAR holds the address in memory, while the
data in memory, it puts the destination MDR holds the data associated with that address.
address in the MAR. ▪ This allows the CPU to accurately access or modify data
❑ Works with the Memory Data Register at specific memory locations.
(MDR): The MAR and Memory Data Register ❑ Data Flow Between CPU and Memory: The MDR serves
(MDR) often work in tandem, where: as an intermediary, holding data temporarily so it can flow
▪ The MAR specifies where in memory data between memory and the CPU smoothly during read/write
should be transferred. cycles.
▪ The MDR contains the actual data to be
written to or read from that location.
 Control Unit (CU) is a vital component of the CPU, as it manages and
The Arithmetic Logic Unit (ALU) is a core coordinates all operations within the computer
component of the CPU, responsible for carrying out ❑ Instruction Decoding: The CU reads instructions from memory,
arithmetic and logical operations. interprets them, and directs the CPU to execute them step-by-step. It
❑ Arithmetic Operations: The ALU performs breaks down each instruction and signals other components on what
basic mathematical calculations like addition, to do.
subtraction, multiplication, and division. ❑ Data Flow Control: The CU manages the flow of data within the
❑ Logical Operations: It also handles logical CPU and between the CPU and other parts, such as memory and
operations, including comparisons (such as input/output devices, ensuring that data moves to the correct place at
greater than, less than, equal to) and bitwise the right time.
operations (AND, OR, NOT, XOR) that are ❑ Synchronization of Components: It coordinates the activities of all
essential for decision-making in programs. parts of the CPU and the entire computer, ensuring that operations
❑ Control of Data Flow: The ALU receives data occur in the correct sequence. This prevents errors and ensures
from the accumulator or other registers and efficient processing.
processes it according to the instructions given ❑ Handling System Interrupts: When there’s an interrupt (e.g., from
by the control unit. The results are then stored an input device), the CU handles it by pausing the current process,
back in a register or memory. addressing the interrupt, and then resuming normal operation.
❑ Role in Decision Making: Based on the ❑ Managing Execution Flow: The CU directs how instructions are
outcomes of its operations, the ALU provides fetched, decoded, and executed in cycles, managing the flow of
flags (such as zero, carry, or overflow flags), control within the CPU and across the system.
which the control unit can use to determine the ❑ Enabling Complex Operations: For complex tasks, the CU handles
next steps in program execution. branching, looping, and other conditional operations by adjusting the
Program Counter (PC) and issuing the necessary commands to
continue or alter execution flow.
General Purpose Registers (GPRs) are versatile storage locations within the
CPU that are used for a variety of tasks during program execution.
Characteristics
❑ Versatility:
▪ GPRs can hold data, addresses, or intermediate results during
calculations. They can be used for various operations, such as
arithmetic, logical operations, and data movement.
❑ Fast Access:
▪ Registers provide faster access compared to memory. Since they
are located within the CPU, they allow for quicker data retrieval
and storage, significantly enhancing performance.
❑ Limited Number:
▪ Most CPUs have a limited number of GPRs (typically between 8
to 32). This limitation requires efficient use of registers, often
involving techniques like register allocation in compilers.
❑ Functionality:
▪ GPRs can be used to hold operands for instructions, store results
of operations, and sometimes even store function arguments and
return addresses in programming.
❑ Architecture-Specific:
▪ The number and specific usage of GPRs can vary depending on
the CPU architecture (e.g., x86, ARM, MIPS). Some
architectures have specific registers for particular purposes (e.g.,
stack pointers, index registers).
Eg,
ADD LOCA, R0
LOAD LOCA, R1
•Retrieve the value stored at memory address
LOCA ❑ LOAD: This is an operation code (opcode) for loading
•Add this value to the contents of register R0. data from memory into a register.
•Store the result back in R0. ❑ LOCA: This is the memory address where the data is
stored.
If the contents of: ❑ R1: This represents register 1 in the CPU, which will
•LOCA is 5. hold the data loaded from memory.
•R0 is 3.
After executing ADD LOCA, R0, the The instruction LOAD LOCA, R1 means:
new content of R0 would be 8 (3 + 5). •Retrieve the data stored at the memory address
LOCA.
•Load this data into register R1.

Example:
If the content at memory address LOCA is 10, after
executing LOAD LOCA, R1, the content of R1 will
be 10.
ADD R1, R2
❑ ADD: This is the operation code (opcode) that specifies the
addition operation.
❑ R1: This represents register 1, which contains one of the
operands for the addition.
❑ R2: This represents register 2, which contains the other
operand for the addition.

The instruction ADD R1, R2 means:

•Add the contents of R1 and R2 together.
•The result is usually stored back in R1 or in a specific
destination register (depending on the architecture).

Example:
If:
•Register R1 contains 4.
•Register R2 contains 6.
Bus structure
A bus structure is a communication system that moves data, addresses, and control signals between components
in a computer. It's made up of conductors, like wires or optical fibers, that connect the central processing unit
(CPU), memory, input/output devices, and other peripherals

The single bus structure is a foundational concept in computer architecture, offering a straight forward way
to connect various components within a system

❑ In a single bus structure, one common bus used to communicate between peripherals and microprocessors.

❑ Single Communication Path: All components share one common communication path (the bus) for data transfer. This
means that only one device can communicate on the bus at a time.

❑ Simplified Design The architecture is straightforward, making it easier to design and implement compared to more
complex multi-bus or point-to-point architectures.

❑ Cost-Effective :Fewer physical connections (wires) are required, reducing overall system costs and complexity
Fig:It shows Single Bus Structure

Disadvantages of Single Bus Structure:

❑ Slower Performance: This is because when many components in the computer
request access to the central processing unit or the RAM at the same time then
the system slows
❑ Single bus bar system is that when a breakdown occurs, the entire supply is
interrupted.
❑ Every workstation on the network "sees" all of the data on the network – this is
a security risk.
Components of a Single Bus Structure Operation of a Single Bus Structure
❑ CPU: ❑ When a device (CPU, memory, or
▪ The central processing unit, which generates addresses, I/O) wants to communicate, it sends a
sends control signals, and performs data processing. request to the bus controller.
❑ Memory: ❑ The bus controller arbitrates which
▪ Main memory (RAM) that stores data and instructions for device gets access to the bus. Only
the CPU. one device can communicate at a
❑ I/O Devices: time.
▪ Input and output devices (like keyboards, mice, printers, ❑ Once a device gains access, it places
etc.) that communicate with the CPU and memory via the the necessary address on the address
bus. lines, data on the data lines, and
❑ Bus Controller: control signals on the control lines.
▪ A component that manages bus access and ensures orderly ❑ The data is then transferred between
communication between the CPU, memory, and I/O the CPU, memory, and I/O devices.
devices. ❑ After the data transfer is complete,
the device releases the bus for other
devices to use.
 Processor clock
The processor clock, also known as the CPU clock, is a crucial component in computer architecture that provides the
timing signals necessary for coordinating the operations of the CPU and its components. The clock defines a regular
time interval is called cycle.

Clock Rate=1/P
P-length of a full cycle

Features
▪ The clock generates regular timing pulses (or cycles) that synchronize the operations of the CPU.
Each pulse indicates when the CPU should perform a specific action, such as fetching an instruction
or executing an operation.
❑ Clock Frequency:
▪ The speed of the clock is measured in Hertz (Hz), with modern processors operating in gigahertz
(GHz). For example, a 3 GHz clock means the clock produces 3 billion cycles per second.
▪ The clock frequency determines how many instructions the CPU can execute in a given time period.
Higher frequencies generally allow for more operations per second, leading to improved performance.
❑ Clock Cycles:
▪ The time interval between consecutive clock pulses is called a clock cycle. Each instruction executed
by the CPU typically takes a certain number of clock cycles to complete, depending on its complexity.
Types of Clock Signals
❑ System Clock:
▪ The primary clock that drives the timing for the entire system, including the CPU, memory, and peripheral
devices.
❑ Bus Clock:
▪ The clock that synchronizes data transfer on the system bus. It may operate at a different frequency than the
CPU clock.
Clock Rate
❑ Clock Rate=1/P
P-length of a full cycle

❑ Clock Rate refers to the frequency at which a computer's processor (CPU) executes instructions and performs
operations. It is a crucial factor in determining the performance of a CPU and is typically measured in Hertz (Hz).

❑ The clock rate indicates the number of cycles a CPU can execute per second. For example, a clock rate of 3 GHz
(gigahertz) means the CPU can perform 3 billion cycles per second.

❑ A clock cycle is the basic unit of time in which the CPU completes a task. Each cycle corresponds to a specific event,
. such as fetching an instruction or writing data to memory.

❑ A higher clock rate generally indicates that a CPU can execute more instructions per second, leading to better
performance. However, this is not the sole factor; the CPU architecture and efficiency also play significant roles.

❑ The clock rate affects how many clock cycles it takes to execute an instruction.
Some complex instructions may require multiple cycles, while simpler instructions can be executed in a single cycle.

❑ In modern CPUs, techniques like pipelining allow multiple instructions to be processed simultaneously at different
stages. The clock rate is crucial in synchronizing these stages, thereby enhancing throughput.
 Basic Performance Equation
T = (N * S) / R.

❑ T (Time):This represents the total execution time required to complete a task or process. It can be measured in seconds,
milliseconds, etc.
❑ N (Number of Instructions):This refers to the total number of instructions that need to be executed in a program or task. It
indicates the workload or the size of the program.
❑ S (Cycles per Instruction):This signifies the average number of clock cycles required to execute one instruction. It reflects the
complexity of the instructions and the efficiency of the CPU.
❑ R (Clock Rate):This is the clock frequency of the CPU, typically measured in Hertz (Hz) or its multiples (kHz, MHz, GHz).It
indicates how many cycles the CPU can perform per second.
Performance Measurement
SPECi- Rating for the program ith in the suit
Memory Location and Addresses
❑ Byte addressability
❑ Big endian and Little endian assignment
❑ Word alignment
❑ Accessing- Numbers, Characters and character string
 . Byte addressability
❑ When the data space in the cell = 8 bits then the corresponding address space is
called as Byte Address .

❑ Based on this data storage i.e. Byte wise storage , the memory chip configuration is
named as Byte Addressable Memory .

❑ Byte addressing in hardware architectures supports accessing

individual bytes
❑ In this architecture, each byte (8 bits) of memory is uniquely
addressable, meaning the system can directly access any single byte
without affecting the others.

Unit Size Example Use

Bit 1 bit Binary flag (0 or 1)
Byte 8 bits Character storage (ASCII)
Word Varies(4 or 8 bytes) Integer, floating-point values
A memory location is a specific "slot"
or cell in a computer's memory where
data can be stored.
memory address is the unique
Each memory location typically stores identifier for each memory location.
a fixed amount of data (e.g., 8 bits or 1 It serves as a reference point,
byte). allowing the CPU and software to
locate and access specific data within
When programs run, variables and data memory.
are stored in various memory locations.
Memory addresses are typically
The size and structure of each memory represented as hexadecimal numbers
location may vary depending on the for easier readability and
architecture and memory model of the compactness.
system.
A memory word refers to a fixed-sized unit of data that a computer's processor can handle or process in one operation.
•Byte Addressability is of two types
•Big-endian (BE): Stores the most significant byte (the “big end”) first. This means that the first byte (at the lowest memory
address) is the largest, which makes the most sense to people who read left to right.
•Little-endian (LE): Stores the least significant byte (the “little end”) first. This means that the first byte (at the lowest memory
address) is the smallest, which makes the most sense to people who read right to left.

Example. If the data bytes is OXA BIZCAF2 .

How this data bytes are stored in memory?
Assuming Word-length to =32- bits
Word Allignment
Alignment in computing refers to how data is arranged and accessed in memory based on the CPU's architecture.
Aligned data is stored at specific memory addresses that optimize access speed and efficiency. When data is aligned, it is
placed at memory addresses that are multiples of the data type’s size. Misaligned data, on the other hand, can lead to
slower access times or even cause hardware exceptions in some systems.

For 32-bit word length, natural word boundaries occur at 0, 4, 8

Accessing number ,character and string

❑ Accessing Numbers in Memory Space
Numbers are stored in binary format in memory, with the size and format depending on the data type (e.g., integer, float). The memory
layout for numbers varies based on factors like endianness and alignment.
•Integer Storage: An integer (e.g., int in C, usually 4 bytes) is stored in memory in a contiguous block of bytes.
•The representation can vary between big-endian and little-endian formats

❑ Accessing Characters in Memory Space

Characters are typically stored as single bytes in memory, represented by specific encodings like ASCII or UTF-8.
•Single Character (char): In most programming languages,
•a character occupies 1 byte of memory. For example, the ASCII character A has a decimal value of 65, so it’s stored as 0x41 in
hexadecimal.

❑ Accessing Strings in Memory Space

Strings are sequences of characters, so they are stored as arrays of contiguous bytes in memory. There are two common
ways strings are stored in memory
Memory Operations
❑ Load ( Reading or fetch): Move data from memory to a register

A load instruction is an instruction that tells the processor to fetch data from a specific memory location and
store it in a register.
A register is a small and fast storage unit inside the processor that can hold data temporarily for processing.

❑ Store ( Writing): Move data from a register to a memory address

A store instruction is an instruction that tells the processor to transfer data from a register to a specific
memory location.
A store instruction usually has two operands: the source operand, which specifies the register to read from,
and the destination operand, which specifies the memory address to write to
Instruction and instruction sequencing
❑ An instruction is a binary-coded operation that tells the computer's CPU what action to perform.

❑ Each instruction typically consists of an opcode (operation code) that specifies the operation to be performed and operands
that provide the necessary data or specify the addresses of the data involved.

▪ Components of an Instruction:
✔ Opcode: Specifies the operation (e.g., addition, subtraction, loading data).
✔ Operands: Specify the data to be used, which can include:
Registers (e.g., R1, R2)
Memory addresses (e.g., a specific location in RAM)
Immediate values (e.g., constant numbers)

❑ Instruction sequencing refers to the order in which instructions are executed by the [Link] CPU typically processes
instructions in a specific sequence, often controlled by a program counter (PC), which holds the address of the next
instruction to be executed.
Instructions
The instructions stored in the memory performs some operations. The four types of operation performed by
an instruction are:
❑ Data transfer between the memory and the processor registers
❑ Arithmetic and logical operations on data
❑ Program sequencing and control
❑ 1/0 transfers

The operations and operands are represented by two types of notations:

❑ Register Transfer Notation (RTN)
❑ Assembly Language Notation (ALN)

Register Transfer Notation (RTN):

The information can he transferred from one location to another in the computer, the possible location
involved in this transfer may include memory locations, processor registers or registers in I/0 systems.
- In RTN, the memory will be represented in Capital letters.
▪ Example: LOCA, LOCH, A, B etc.
▪ The processor registers are represented as RO.R1,R2...
▪ 1/0 operations can be represented as DATAIN, DATAOUT...
▪ The contents are represented using square brackets []
 Example: D=A−B

RTN (Register Transfer Notation):

D←[A]−[B]

Assembly Language Notation:

Move A, R1 ; Load the value of A into Register R1
Subtract B, R1 ; Subtract the value of B from R1
Move R1, D ; Store the result from Register R1 into D
Example
ADD R1, R2, R3

R1 ← R2 + R3
•Add the values stored in registers R2 and R3.
•Store the result in register R1
A one-address instruction is a type of machine instruction format that uses only one explicit operand in addition to an
implied accumulator

Example 1: A=B+C

LOAD B ; Accumulator ← [B]

ADD C ; Accumulator ← Accumulator + [C]
STORE A ; [A] ← Accumulator
•Here, programs and data are stored in the same memory, i.e.
von Neumann architecture.

•First instruction of a program is stored at address i. PC gives

address i and instruction stored at that address i is fetched
from the memory and then decoded and then operand NUM1
is fetched from the memory and stored in a temporary register
and then the instruction is executed(i.e. content of address A
is copied into processor register R0).

•Side by Side during decoding or execution, the PC gets

incremented by 4(i.e. it contains the address of the next
instruction) because the instruction and memory segment is
of 4 bytes. So the instruction at address i is executed.

•So every time, the PC is incremented by 4. Therefore, the

program is executing in a sequential manner. And this process
is called straight line sequencing.
 Straight line sequencing program for adding n numbers.
•The addresses of the memory locations containing the n numbers
are represented as NUM1,NUM2…..NUMn(i.e. NUM1 address
includes first number).
•The first number is stored into processor register R0. And every
other number is added to register R0. Finally, when the program
ends(i.e. n numbers are added, the result is placed in memory
location SUM

•The second way is to use a loop to add n number. But here straight line sequencing is
not used because every time loop iteration ends, PC has to load the branch address
and program execution starts from that address.
•Here the location N stores the value of n. Processor register R1 is used as a counter to
determine the number of times the loop gets executed.
•The contents of the location N are moved into R1 at the start of program execution.
•After that, register R0 is cleared.
•The address LOOP is reloaded again and again until R1 becomes 0 (this means all
numbers are added).Every time a number is added, then the R1 value is decremented.
•When R1 becomes 0, we come out of the loop and the result which is stored at R1 is
copied into memory location SUM.
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