Memory Hierarchy

 Memory is an essential component in any digital computer which is

need for storing programs and data.
 A computer run more efficiently if it has additional storage beyond
the capacity of main memory.
 The memory unit that communicates directly with the CPU is called
the main memory.
 Devices that provide backup storage are called auxiliary memory.
o Example : Magnetic discs , Magnetic tapes…etc.
 Only program and data needed by the processor reside in the main
memory. And the remaining are stored in auxiliary memory.
 The memory hierarchy system consists of all storage devices
employed in a computer system.

Magnetic Tapes
I/O Processor Main Memory

Magnetic Discs

CPU Cache Memory

Fig: Memory Hierarchy in a Computer System

 Main memory able to communicate directly with the CPU and with
auxiliary memory devices through I/O processor.
 A special very high speed memory called a cache is sometimes used
to increase the speed of processing by making current programs and
data available to the CPU at a rapid rate.
  The cache memory is employed in computer system to compensate
for the speed differential between the main memory access time and
processor logic.
 The cache is used for storing segments of program currently being
executed in the CPU and temporary data frequently need in the
present calculation.
 The main goal of using a memory hierarchy to obtain the highest
possible average access speed while minimizing the total cost of the
entire memory system.
 The part of the computer system that supervises the flow of
information between auxiliary memory and main memory is called
the memory management system.
 So memory hierarchy contains:
o Cache Memory
o Primary Memory: RAM, ROM.
o Auxiliary Memory: Magnetic Discs, Magnetic Tapes, Optical
Semiconductor devices…etc
Cache Memory
 A special very high speed memory called a cache is sometimes used
to increase the speed of processing by making current programs and
data available to the CPU at a rapid rate.
 The cache memory is employed in computer systems to compensate
for the speed differential between main memory access time and
processor logic.
 The CPU logic is usually faster than main memory access time, with
the result that processing speed is limited primarily by the speed of
main memory.
 A technique used to compensate for the mismatch in operating
speeds is to employ an extremely fast, small cache between the CPU
and main memory whose access time is close to processor logic
clock cycle time.
  The cache is used for storing segments of programs currently being
executed in the CPU and temporary data frequently needed in the
present calculations.
 By making programs and data available at a rapid rate, it is possible
to increase the performance rate of the computer.
 The cache organization is concerned with the transfer of information
between main memory and CPU.
Organization of Hard Disk:
 SELF
Instruction Code:
Stored Program Organization
The simplest way to organize a computer
 One processor register: AC (accumulator)
o The operation is performed with the memory
operand and the content of AC.
 Instruction code format with two parts: Opcode and
Address
o Opcode: specify 16 possible operations (4-bit)
o Address: specify the address of an operand (12-bit)
o If an operation in an instruction code does not need
an operand from memory, the rest of the bits in the
instruction (Address field) can be used for other
purpose.
 Memory: 12-bit = 4096 location = 4096 word
(instruction and data are stored)
o Store each instruction code (program) and operand
(data) in 16-bit memory word.
 Addressing Mode:
 Immediate operand address (Immediate Addressing mode)
 1. The second part of instruction code (address field)
specifies operand.
 Direct operand address (Direct Addressing mode)
1. The second part of instruction code specifies the
address of operand. (i.e. the given address is effective
address).
 Indirect operand address (Indirect Addressing mode)
1. The bits in the second part of the instruction
designate an address of a memory word in which the
address of the operand is found (pointer).
 One bit of the instruction code is used to distinguish between
direct and indirect address.
 Effective address: Address where an operand is physically
located.
 Direct Address
 Occurs when the operand part contains the address of needed
data.
1. Address part of IR (Instruction Register) is placed
on the bus and loaded back into the AR (Address
Register).
2. Address is selected in memory and its data placed
on the bus to be loaded into the data register (DR) to be
used for requested instruction.
 Indirect Address
 Occurs when the operand contains the address of the address
of needed data.
1. Address part of IR is placed on the bus and loaded
back into the AR.
2. Address is selected in memory and placed on the
bus to be loaded back into the AR.
3. New address is selected in memory and placed on
the bus to be loaded into the DR to use later.
 

Computer Registers
 Computer instructions are normally stored in consecutive memory locations
and are executed sequentially one at a time.
 Control reads an instruction from a specific address in memory and execute
it and similarly continue this process one by one.
 Counter needed to calculate the address of next instruction after execution of
current instruction.
 Need register to store instruction code after read from memory.
 Computer need processor registers for manipulating data and a register for
holding a memory address.
 Some of the registers used in computer system are:
1. Data Register (DR): it holds the operand (data) read from memory.
2. Accumulator Register (AC): it is general purpose processing register.
 3. Instruction Register (IR): to hold the instruction read from memory.
4. Temporary Register (TR): to hold a temporary data during processing.
5. Address Register (AR): hold a memory address, 12-bit width address.
6. Program Counter (PC):
 hold the address of the next instruction to be read from memory
after the current instruction is executed.
 Instruction words are read and executed in sequence unless a
branch instruction is encountered.
 A branch instruction calls for a transfer to a nonconsecutive
instruction in the program.
 The address part of a branch instruction is transferred to PC to
become the address of the next instruction.
 To read instruction, memory read cycle is initiated, and PC is
incremented by one (next instruction fetch)
7. Input Register (INPR): receive an 8-bit character from an input
device.
8. Output Register (OUTR): hold an 8-bit character for an output device.

Register Symbol No. of bits Register Name Register Function

DR 16 Data Register Hold memory operand
AR 12 Address Register Hold address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Hold instruction code
PC 12 Program Counter Hold address of next instruction
TR 16 Temporary Register Hold temporary data
INPR 8 Input Register Hold input character
OUTR 8 Output Register Hold output character

Common Bus System

 The basic computer has eight registers, a memory unit, and a control unit.
 Paths must be provided to transfer information from one register to another
register and between memory and register.
 A more efficient scheme for transferring information in a system with many
registers is to use a common bus.
 The connection of the registers and memory of the basic computer to a
common bus system.
o The output of seven registers and memory are connected to the
common bus.
o The specific output is selected by MUX (S0, S1, S2)
 Memory (7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6).
 When LD (load input) is enable, the particular register receives
the data from the bus.
 Control inputs: LD, INC, CLR, Write, Read
o Control Variables:
 Various control variables are used to select:
 The path of information; and
 The operation of the registers.
o Selection Variables:
 Used to specify a register whose output is connected to the
common bus at any given time.
 To select one register out of 8, we need 3 selection variables.
 For example, if S2S1S0 = 011, the output of DR is directed to the
common bus.
o Load Input:
 Enables the input of a register connected to the common bus.
 When LD = 1 for a register, the data on the common bus is
write into the register during the next clock pulse transition.
o Increment Input (INR):
 Increments the content of the register.
o Clear Input (CLR):
 Clear the content of a register to zero.
o When the contents of AR or PC (12-bit) are applied to the 16-bit
common bus, the four most significant bits are set to zero.
o When AR, or PC receives information from the bus, only the 12 least
significant bits are transferred to the register.
o Both INPR and OUTR use only 8 least significant bit of the bus.
 Fig: Common Bus System

Computer Instruction
 The basic computer has three instruction code format and each have
16-bits.
 The opcode contains 3-bit and remaining 13-bits meaning depends
on the opcode encountered.
 If opcode contains 3-bit 111 then instruction format is register
reference instruction if left most bit is 0 and is input-output
instruction if left most bit is 1.
 If opcode contains other than 111 then it called memory reference
instruction, which use 12-bits for address and one left most bit (I)
for addressing mode.
 In memory reference instruction if I = 0 then called direct addressing
mode and if I = 1 then called indirect addressing mode.
 A register reference instruction specifies an operation on or a test of
the AC register. An operand from memory is not needed; therefore,
other 12 bits are used to specify the operation or test to be execute.
 Similarly, an Input Output instruction does not need a reference to
memory. The remaining 12-bits are used to specify the type of input-
output operation or test performed.

15 14 12 11 0
I Opcode(3-bit) Address (12-bits)
(a) Memory Reference Instruction (Opcode = 000 through 110)

15 14 12 11 0
0 111 Register Operation (12-bits)
(b) Register Reference Instruction (Opcode = 111 and I = 0)

15 14 12 11 0
1 111 I/O Operation (12-bits)
(c) I/O Instruction (Opcode = 111 and I = 1)

Fig: Basic computer instruction format

 Only three bits of the instruction are used for the opcode.
 It restricts maximum 8 distinct operations.
 Since, register-reference and I/O instruction use the remaining 12-
bits as part of the operation code.
 The total number of instruction can exceed eight.
 The total number of instructions chooses for the basic computer is
equal to 25.
 Instruction use three capital letters word abbreviation.
Timing and Control
 The timing for all registers is controlled by a master clock generator.
 Clock pulse applied to all flip-flop and registers.
 Clock pulse do not change state of register unless the register is enabled by a
control signal.
 After generating control, it provided to multiplexer in common bus, control
input in processor register, and micro-operations for the accumulator.
 Control organization (two types):
o Hardwired control
 Implemented with gates, flip-flops, decoders, and other digital
circuits.
 Fast most operation.
 Hard to modify (i.e. change the components and structure of
control).
o Microprogrammed Control
 Control information stored in a control memory.
 Control memory programmed to initiate the required sequence
of micro-operation.
 Easy to modify and change. (i.e. re-program according to need).
 It consists of two decoders (3x8 decoder and 4x16
decoder), and a sequence counter, and a number of
control logic gates.
 Instruction read from memory and stored in IR.
 Instruction register divide in 3-parts: I-bit, Opcode, and
bit 0 through 11.
 Opcode (12-14) decoded with 3x8 decoder.
 8-output decoder are designated by symbol D0 to D7.
 Bit 15 of the instruction is transferred to flip-flop I.
 Bits 0 through 11 are applied to the control logic gates.
 4-bit sequence counter can count in binary from 0 to 15.
 Output of the counter are decoded into 16-timing signals
T0 to T15.
 The sequence counter SC can be incremented or cleared
synchronously.
 Incremented from T0 to T15, and once it cleared next
active timing signal to be T0. Initially it is cleared.
 Example:

 Let SC incremented to provide timing signal. T0, T1, T2, T3, T4, ….. in
sequence.
 At T4, SC is cleared to 0; if decoder D3 is active.
i.e. D3T4: SC  0.

 Example explanation:
o D3T4 = 1, SC  0.
o D3 active at end of T2.
o When T4 active, output of AND gate implements control function
D3T4 become active.
o Applied CLR input of SC.
o On the next positive clock transition of the counter is cleared to 0.
 SC responds to the positive transition of the clock.
 Initially CLR input of SC is active.
 The first positive transition of the clock clear SC to 0; and activate T0.
 At T0 only trigger those registers whose control connected to T0.
 SC is incremented with every positive clock transition, unless its CLR input
is active.
 If CLR is not active, then SC increase from T0 to T15 and back to T0.