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VLSI Winter Training Schedule 2025-2026

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0% found this document useful (0 votes)
5 views3 pages

VLSI Winter Training Schedule 2025-2026

Uploaded by

rezafahim81
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

WINTER TRAINING (VLSI) ROUTINE (JU)

8TH DECEMBER 2025

Date 11am - 1.00 Pm 1 pm to 2pm to 4pm


2 pm
08-12-25 Introduction to VLSI Tiffin Analog VLSI
Monday SC JB
Date 11am - 2.00 Pm 2 pm to 2.30pm to 4.30pm
2.30 pm
09-12-25 G1 - ME Tiffin Analog VLSI
Tuesday G2 - Verilog JB
G3 - EDA (Digital)
G4 - EDA (Analog)
10-12-25 G5 - ME -do- Digital VLSI
Wednesday G6 - Verilog AB
G7 - EDA (Digital)
G8 - EDA (Analog)
11-12-25 G1 - ME -do- Digital VLSI
Thursday G2 - Verilog AB
G3 - EDA (Digital)
G4 - EDA (Analog)
Date 11am - 1.00 Pm 1 pm to 2 pm to 5 pm
2 pm
12-12-25 Nano Materials & Sensors Tiffin G5 - ME
Friday SR G6 - Verilog
G7 - EDA (Digital)
G8 - EDA (Analog)
Date 11am - 1.00 Pm 1pm to 1.30pm to 4.30pm
1.30pm
13-12-25 Digital VLSI Tiffin
Saturday AB
Date 11am - 2.00 Pm 2 pm to 2.30pm to 5.30pm
2.30 pm
15-12-25 G1 - ME Tiffin G5 - ME
Monday G2 - Verilog G6 - Verilog
G3 - EDA (Digital) G7 - EDA (Digital)
G4 - EDA (Analog) G8 - EDA (Analog)
Date 11am - 1.00 Pm 1 pm to 2 pm to 4 pm
2 pm
16-12-25 Timing Analysis Tiffin VLSI Architecture System Design
Tuesday SC CKM
Date 11am - 2pm 2pm 0 2.30pm - 4.30pm
2.30pm
17-12-25 G1 - ME -do- Digital VLSI
Wednesday G2 - FPGA AB
G3 - EDA (Analog)
G4 - EDA (Digital)
Date 11am - 1.00 Pm 1 pm to 2pm to 4pm
2 pm
18-12-25 MOS Physics Tiffin VLSI Architecture System Design
Thursday CM CKM
19-12-25 MOS Physics -do- VLSI Architecture System Design
Friday CM CKM
Date 11am - 1.00 Pm 1 pm to 2pm to 4pm
2 pm
20-12-25 MOS Physics -do- Nano Materials & Sensors
Saturday CM SR
Date 11am - 1.00 Pm 1 pm to 2pm to 4pm
2 pm
22-12-25 MOS Physics Tiffin VLSI Architecture System Design
Monday CM CKM
Date 11am - 1.00 Pm 1 pm to 2pm to 4pm
2 pm
23-12-25 Analog Circuit Tiffin Analog Circuit
Tuesday A. Bor A. Bor
Date 11am - 2.00 Pm 2 pm to 2.30pm to 5.30pm
2.30 pm
29-12-25 G1 - ME Tiffin G5 - ME
Monday G2 - FPGA G6 - FPGA
G3 - EDA (Aanalog) G7 - EDA (Analog)
G4 - EDA (Digital) G8 - EDA (Digital)
30-12-25 G5 - ME -do- G1 - ME
Tuesday G6 - FPGA G2 - FPGA
G7 - EDA (Analog) G3 - EDA (Aanalog)
G8 - EDA (Digital) G4 - EDA (Digital)
31-12-25 G1 - EDA (Digital) -do- G5 - ME
Wednesday G2 - EDA (Analog) G6 - FPGA
G3 - ME G7 - EDA (Analog)
G4 - Verilog G8 - EDA (Digital)
02-01-26 G5 - EDA (Digital) -do- G1 - EDA (Digital)
Friday G6 - EDA (Analog) G2 - EDA (Analog)
G7 - ME G3 - ME
G8 - Verilog G4 - Verilog
05-01-26 G1 - EDA (Digital) -do- G5 - EDA (Digital)
Monday G2 - EDA (Analog) G6 - EDA (Analog)
G3 - ME G7 - ME
G4 - Verilog G8 - Verilog
06-01-26 G5 - EDA (Digital) -do- G1 - EDA (Analog)
Tuesday G6 - EDA (Analog) G2 - EDA (Digital)
G7 - ME G3 - ME
G8 - Verilog G4 - FPGA
07-01-26 G1 - EDA (Analog) -do- G5 - EDA (Analog)
Wednesday G2 - EDA (Digital) G6 - EDA (Digital)
G3 - ME G7 - ME
G4 - FPGA G8 - FPGA
08-01-26 G5 - EDA (Analog) -do- G1 - EDA (Analog)
Thursday G6 - EDA (Digital) G2 - EDA (Digital)
G7 - ME G3 - ME
G8 - FPGA G4 - FPGA
09-01-26 G1 - Verilog -do- G5 - EDA (Analog)
Friday G2 - ME G6 - EDA (Digital)
G3 - Synopsys G7 - ME
G8 - FPGA
13-01-26 G5 - Verilog -do- G1 - Verilog
Tuesday G6 - ME G2 - ME
G7 - Synopsys G3 - Synopsys
14-1-26 G1 - Verilog -do- G5 - Verilog
Wednesday G2 - ME G6 - ME
G4 - Synopsys G7 - Synopsys
15-01-26 G5 - Verilog -do- G1 - FPGA
Thursday G6 - ME G2 - ME
G8 - Synopsys G4 - Synopsys
16-01-26 G1 - FPGA -do- G5 - FPGA
Friday G2 - ME G6 - ME
G8 - Synopsys
19-01-26 G5 - FPGA -do- G1 - FPGA
Monday G6 - ME G2 - ME
20-01-26 G3 - Verilog -do- G5 - FPGA
Tuesday G4 - ME G6 - ME
G1 - Synopsys
21-01-26 G7 - Verilog -do- G3 - Verilog
Wednesday G8 - ME G4 - ME
G5 - Synopsys G1 - Synopsys
22-01-26 G3 - Verilog -do- G7 - Verilog
Thursday G4 - ME G8 - ME
G2 - Synopsys G5 - Synopsys
27-01-26 G7 - Verilog -do- G3 - FPGA
Tuesday G8 - ME G4 - ME
G6 - Synopsys G2 - Synopsys
28-01-26 G3 - FPGA -do- G7 - Verilog
Wednesday G4 - ME G8 - ME
G6 - Synopsys
29-01-26 G7 - Verilog -do- G3 - FPGA
Thursday G8 - ME G4 - ME
G6 - Synopsys
30-01-26 G7 - Verilog
Friday G8 - ME

Examination date: 2nd February 2026 12 noon to 1pm.

SC - Prof. Sayan Chatterjee


CM - Dr. Chandrima Mondal
JB - Dr. Joydeep Basu
AB - Dr. Amrita Banerjee
SR - Prof. Sunipa Roy
CKM - Prof. Chintan Kumar Mondal
A. Bor - Mr. Amit Bor

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