LNK623-626

LinkSwitch-CV Family
Energy-Efficient, Off-line Switcher with Accurate
Primary-side Constant-Voltage (CV) Control

Product Highlights *

Dramatically Simplifies CV Converters

• Eliminates optocoupler and all secondary CV control circuitry
• Eliminates bias winding supply – IC is self biasing

Advanced Performance Features

• Compensates for external component temperature variations Wide Range
• Very tight IC parameter tolerances using proprietary trimming High-Voltage
DC Input D
technology FB
• Continuous and/or discontinuous mode operation for design LinkSwitch-CV BP
flexibility
S
• Frequency jittering greatly reduces EMI filter cost
• Even tighter output tolerances achievable with external resistor
selection/trimming
PI-5195-012915
Advanced Protection/Safety Features (a) Typical Application Schematic
• Auto-restart protection reduces delivered power by >95% for
output short-circuit and all control loop faults (open and shorted VO ±5%
components)
• Hysteretic thermal shutdown – automatic recovery reduces power
supply returns from the field
• Meets HV creepage requirements between Drain and all other pins,
both on the PCB and at the package

EcoSmart™– Energy Efficient start

Re
• No-load consumption <200 mW at 230 VAC and down to below to-
Au
70 mW with optional external bias PI-5196-012315 IO
• Easily meets all global energy efficiency regulations with no added
(b) Output Characteristic
components
• ON/OFF control provides constant efficiency down to very light Figure 1. Typical Application Schematic (a) and Output Characteristic Envelope
(b). *Optional with LNK623-624PG/DG. (see Key Application Consider-
loads – ideal for mandatory EISA and ENERGY STAR 2.0 regulations ations section for clamp and other external circuit design considerations).
• No primary or secondary current sense resistors – maximizes
efficiency
Output Power Table
Green Package 230 VAC ±15% 85-265 VAC
• Halogen free and RoHS compliant package
Product 3 Peak or Peak or
Applications Adapter1 Open Adapter1 Open
• DVD/STB Frame2 Frame2
• Adapters LNK623PG/DG 6.5 W 9W 5.0 W 6W
• Standby and auxiliary supplies LNK624PG/DG 7W 11 W 5.5 W 6.5 W
• Home appliances, white goods and consumer electronics
LNK625PG/DG 8W 13.5 W 6.5 W 8W
• Industrial controls
LNK626PG/DG 10.5 W 17 W 8.5 W 10 W
Description
Table 1. Output Power Table. Based on 5 V Output.
The LinkSwitchTM-CV dramatically simplifies low power, constant voltage Notes:
(CV) converter design through a revolutionary control technique which 1. Minimum continuous power in a typical non-ventilated enclosed adapter
eliminates the need for both an optocoupler and secondary CV control measured at +50 °C ambient.
circuitry while providing very tight output voltage regulation. The 2. Maximum practical continuous power in an open frame design with adequate
heat sinking, measured at 50 °C ambient (see Key Application Considerations
combination of proprietary IC trimming and E-Shield™ transformer section for more information).
construction techniques enables Clampless™ designs with the 3. Packages: P: PDIP-8C, D: SO-8C.
LinkSwitch-CV LNK623/4.

LinkSwitch-CV provides excellent cross-regulation for multiple-output

flyback applications such as DVDs and STBs. A 725 V power MOSFET
and ON/OFF control state machine, self-biasing, frequency jittering,
cycle-by-cycle current limit, and hysteretic thermal shutdown circuitry
are all incorporated onto one IC.
Figure 2. PDIP-8C and SO-8C Packages.
 LNK623-626

DRAIN
(D)
REGULATOR
BYPASS 6V
(BP)
+
FB 6V -
+ OUT Reset 5V
FEEDBACK D Q STATE
VTH - MACHINE
(FB) VILIMIT
tSAMPLE-OUT
ILIM Drive
DCMAX

FAULT
6.5 V FB Auto-Restart
Open-Loop
THERMAL
SHUTDOWN
DCMAX
SAMPLE
tSAMPLE-OUT DELAY

OSCILLATOR
SOURCE
+ (S)
SOURCE ILIM - VILIMIT
(S)
Current Limit
Comparator LEADING
EDGE
BLANKING

PI-5197-012915

Figure 3 Functional Block Diagram.

Pin Functional Description

DRAIN (D) Pin:
This pin is the power MOSFET drain connection. It provides internal
operating current for both start-up and steady-state operation. P Package (DIP-8C) D Package (SO-8C)
BYPASS (BP) Pin:
This pin is the connection point for an external bypass capacitor for FB 1 8 S 1 8
FB S
the internally generated 6 V supply.
2 7
BP 2 7 S BP S
FEEDBACK (FB) Pin:
6
During normal operation, switching of the power MOSFET is 6 S S
controlled by this pin. This pin senses the AC voltage on the bias 4 5
D S
winding. This control input regulates the output voltage based on the D 4 5 S
flyback voltage of the bias winding.

SOURCE (S) Pin:

This pin is internally connected to the output MOSFET source for
PI-5198-012315
high-voltage power and control circuit common returns.
Figure 4. Pin Configuration.
 LNK623-626

LinkSwitch-CV Functional Description divider is open or missing) and reduces the auto-restart time from
200 ms to approximately 6 clock cycles (90 ms), whilst keeping the
The LinkSwitch-CV combines a high-voltage power MOSFET switch disable period of 2.5 seconds. This effectively reduces the auto-
with a power supply controller in one device. Similar to the restart duty cycle to less than 0.01%.
LinkSwitch-LP and TinySwitch-III it uses ON/OFF control to regulate
the output voltage. The LinkSwitch-CV controller consists of an Over-Temperature Protection
oscillator, feedback (sense and logic) circuit, 6 V regulator, over- The thermal shutdown circuitry senses the die temperature. The
temperature protection, frequency jittering, current limit circuit, threshold is set at 142 °C typical with a 60 °C hysteresis. When the
leading-edge blanking, and ON/OFF state machine for CV control. die temperature rises above this threshold (142 °C) the power
MOSFET is disabled and remains disabled until the die temperature
Constant Voltage (CV) Operation falls by 60 °C, at which point the MOSFET is re-enabled.
The controller regulates the FEEDBACK pin voltage to remain at VFBth
using an ON/OFF state-machine. The FEEDBACK pin voltage is Current Limit
sampled 2.5 ms after the turn-off of the high-voltage switch. At light The current limit circuit senses the current in the power MOSFET.
loads the current limit is also reduced to decrease the transformer When this current exceeds the internal threshold (ILIMIT), the power
flux density. MOSFET is turned off for the remainder of that cycle. The leading
edge blanking circuit inhibits the current limit comparator for a short
Auto-Restart and Open-Loop Protection time (tLEB) after the power MOSFET is turned on. This leading edge
In the event of a fault condition such as an output short or an open blanking time has been set so that current spikes caused by
loop condition the LinkSwitch-CV enters into an appropriate capacitance and rectifier reverse recovery time will not cause
protection mode as described below. premature termination of the MOSFET conduction.
In the event the FEEDBACK pin voltage during the Flyback period falls 6.0 V Regulator
below VFBth-0.3 V before the FEEDBACK pin sampling delay (~2.5 ms) The 6 V regulator charges the bypass capacitor connected to the
for a duration in excess of 200 ms (auto-restart on-time (t AR-ON) the BYPASS pin to 6 V by drawing a current from the voltage on the
converter enters into auto-restart, wherein the power MOSFET is DRAIN, whenever the MOSFET is off. The BYPASS pin is the internal
disabled for 2.5 seconds (~8% auto-restart duty cycle). The auto-restart supply voltage node. When the MOSFET is on, the device runs off of
alternately enables and disables the switching of the power MOSFET the energy stored in the bypass capacitor. Extremely low power
until the fault condition is removed. consumption of the internal circuitry allows the LinkSwitch-CV to
In addition to the conditions for auto-restart described above, if the operate continuously from the current drawn from the DRAIN pin.
sensed FEEDBACK pin current during the Forward period of the A bypass capacitor value of 1 mF is sufficient for both high frequency
conduction cycle (switch “on” time) falls below 120 mA, the converter decoupling and energy storage.
annunciates this as an open-loop condition (top resistor in potential
 LNK623-626

Applications Example

L1
3.5 × 7.6 mm T1 D8
Ferrite Bead EEL19 UF4003 12 V, 0.1 A
1 6

R1 C9 R8
5.1 kΩ 47 µF 24 kΩ
3 7 L3
1/8 W 25 V 1/8 W
C3 D7 SB540 10 µH
820 pF 5 V, 1.7 A
11
D1 D2 VR1 1 kV
C8 C10 R7
FR106 FR106 1N5272B 1000 µF 470 µF 510 Ω
R10 C13
8,9,10 47 Ω 270 pF 10 V 10 V 1/8 W

D9 C11 R9 RTN
UF4003 47 µF 39 kΩ
R2 12 50 V 1/8 W
390 Ω
F1 RV1 -22 V, 15 mA
L 3.15 A 275 V 5
D5
1N4007 D6
85 - 265 C1 C2 1N4148
VAC 22 µF 22 µF 4
400 V 400 V
N RT1
2
10 Ω R3
6.34 kΩ
LinkSwitch-CV 1%
U1
D3 D4 LNK626PG
1N4007 1N4007 D
FB

BP

S R4 R5
6.2 kΩ 47 kΩ
C4 1/8 W R6 C6
1 µF 4.02 kΩ 10 µF
50 V C5 1% 50 V
L2 680 pF
680 µH 50 V
PI-5205-033116

Figure 5. 7 W (10 W peak) Multiple Output Flyback Converter for DVD Applications with Primary Sensed Feedback.

Circuit Description The rectified and filtered input voltage is applied to one side of the
This circuit is configured as a three output, primary-side regulated primary winding of T1. The other side of the transformer’s primary
flyback power supply utilizing the LNK626PG. It can deliver 7 W winding is driven by the integrated MOSFET in U1. The leakage
continuously and 10 W peak (thermally limited) from an universal inductance drain voltage spike is limited by the clamp circuit D5, R1,
input voltage range (85 – 265 VAC). Efficiency is >67% at 115 R2, C3 and VR1. The Zener bleed clamp arrangement was selected
VAC/230 VAC and no-load input power is <140 mW at 230 VAC. for lowest no-load input power but in applications where higher
no-load input power is acceptable VR1 may be omitted and the value
Input Filter of R1 increased to form a standard RCD clamp.
AC input power is rectified by diodes D1 through D4. The rectified
DC is filtered by the bulk storage capacitors C1 and C2. Inductor L1, Output Rectification
L2, C1 and C2 form a pi (π) filter, which attenuates conducted The secondaries of the transformer are rectified by D7, D8 and D9.
differential-mode EMI noise. This configuration along with Power A Schottky barrier type was used for the main 5 V output for higher
Integrations transformer E-shield technology allow this design to efficiency. The +12 V and -22 V outputs use an ultrafast rectifier
meet EMI standard EN55022 class B with good margin without diode. The main output is post filtered by L3 and C10 to remove
requiring a Y capacitor. Fuse F1 provides protection against switching frequency ripple. Resistors R7, R8 and R9 provide a
catastrophic failure. Negative temperature coefficient thermistor RT1 preload to maintain the output voltages within their respective limits
limits the inrush current when AC is first applied to below the when unloaded. To reduce high frequency ringing and associated
maximum rating of diodes D1 through D4. Metal oxide varistor RV1 radiated EMI an RC snubber formed by R10 and C13 was added
clamps the AC input during differential line transients, protecting the across D7.
input components and maintaining the peak drain voltage of U1
Output Regulation
below its 725 V BVDSS rating. For differential surge levels at or below
The LNK626 regulates the output using ON/OFF control, enabling or
2 kV this component may be omitted.
disabling switching cycles based on the sampled voltage on the
LNK626 Primary FEEDBACK pin. The output voltage is sensed using a primary
The LNK626PG device (U1) incorporates the power switching device, referenced winding on transformer T1 eliminating the need for an
oscillator, CV control engine, startup, and protection functions. The optocoupler and a secondary sense circuit. The resistor divider formed
integrated 725 V MOSFET provides a large drain voltage margin in by R3 and R6 feeds the winding voltage into U1. Standard 1% resistor
universal input AC applications, increasing reliability and also reducing values were used to center the nominal output voltages. Resistor R5
the output diode voltage stress by allowing a greater transformer and C5 reduce pulse grouping by creating an offset voltage that is
turns ratio. The device can be completely self-powered from the proportional to the number of consecutive enabled switching cycles.
BYPASS pin and decoupling capacitor C4. In this design a bias circuit
(D6, C6 and R4) was added to reduce no load input power below
140 mW.

4
 LNK623-626

Key Application Considerations Single Point Grounding

Use a single point (Kelvin) connection at the negative terminal of the
Output Power Table input filter capacitor for the LinkSwitch-CV SOURCE pin and bias
The data sheet maximum output power table (Table 1) represents the winding return. This improves surge capabilities by returning surge
maximum practical continuous output power level that can be obtained currents from the bias winding directly to the input filter capacitor.
in a flyback converter under the following assumed conditions:
Bypass Capacitor
1. The minimum DC input voltage is 100 V or higher at 90 VAC input. The BYPASS pin capacitor should be located as close as possible to
The value of the input capacitance should be large enough to the SOURCE and BYPASS pins.
meet these criteria for AC input designs.
2. Secondary output of 5 V with a Schottky rectifier diode. Feedback Resistors
3. Assumed efficiency of 80%. Place the feedback resistors directly at the FEEDBACK pin of the
4. Continuous conduction mode operation (KP = 0.4). LinkSwitch-CV device. This minimizes noise coupling.
5. Reflected Output Voltage (VOR) of 110 V.
Thermal Considerations
6. The part is board mounted with SOURCE pins soldered to a
The copper area connected to the SOURCE pins provide the
sufficient area of copper to keep the SOURCE pin temperature at
LinkSwitch-CV heat sink. A rule of thumb estimate is that the
or below 110 °C for P package and 100 °C for D packaged
LinkSwitch-CV will dissipate 10% of the output power. Provide
devices.
enough copper area to keep the SOURCE pin temperature below
7. Ambient temperature of 50 °C for open frame designs and an
110° C to provide margin for part to part RDS(ON) variation.
internal enclosure temperature of 60 °C for adapter designs.
Secondary Loop Area
Note: Higher output power are achievable if the efficiency is higher
To minimize leakage inductance and EMI, the area of the loop
than 80%, typically for high output voltage designs.
connecting the secondary winding, the output diode and the output
BYPASS Pin Capacitor filter capacitor should be minimized. In addition, sufficient copper
A 1 mF BYPASS pin capacitor (C4) is recommended. The capacitor area should be provided at the anode and cathode terminal of the
voltage rating should be equal to or greater than 6.8 V. The diode for heat sinking. A larger area is preferred at the quiet cathode
terminal. A large anode area can increase high frequency radiated EMI.
capacitor’s dielectric material is not important. The capacitor must be
physically located close to the LinkSwitch-CV BYPASS pin. Electrostatic Discharge Spark Gap
In chargers and adapters ESD discharges may be applied to the
Circuit board layout
output of the supply. In these applications the addition of a spark
LinkSwitch-CV is a highly integrated power supply solution that
gap is recommended. A trace is placed along the isolation barrier to
integrates on a single die, both the controller and the high-voltage
form one electrode of a spark gap. The other electrode, on the
MOSFET. The presence of high switching currents and voltages
secondary-side, is formed by the output return node. The arrange-
together with analog signals makes it especially important to follow
ment directs ESD energy from the secondary to the primary side AC
good PCB design practice to ensure stable and trouble free operation
input. A 10 mil gap is placed near the AC input. The gap decouples
of the power supply.
any noise picked up on the spark gap trace to the AC input. The
When designing a board for the LinkSwitch-CV based power supply, it trace from the AC input to the spark gap electrode should be spaced
is important to follow the following guidelines: away from other traces to prevent unwanted arcing occurring and
possible circuit damage.
 LNK623-626

Primary Side Secondary Side

Drain trace area
miniminzed Output Filter
Input Filter Clamp Output
Rectifiers Capacitor
Capacitor Components Isolation Barrier

VR1 R2 C11
C1 Y1
Copper area C3 Capacitor C12
L1 (optional)
maximized for T1 D9
heat sinking R10 C13

D7
R1
D5 L3
C2 U1
D1 D3 S D
L2 Transformer C8
S BP R3
S
D4
D2 S JP1
R4 C10
FB
C4 C9
D8 R8 R9
F1 RV1 C5 R7
R5 D6
R6 C6 J2
RT1
J1 1 6
ESD
spark gap
10 mil Bypass Feedback DC Outputs
AC
+
IN
- gap Capacitor Resistors close
close to device to device PI-5269-012315

Figure 6. PCB Layout Example.

B+ B+

CLAMP
CLAMP

Small FEEDBACK
pin node area
D
D FB
FB
BP
BP
S Bias resistor
S Minimize
FEEDBACK
pin node PRI RTN
PRI RTN area
Bias currents Kelvin connection at PI-5266-012315
Bias currents Kelvin connection at PI-5265-012315 return to bulk SOURCE pin, no power
return to bulk SOURCE pin, no power capacitor currents in signal traces
capacitor currents in signal traces

Figure 7. Schematic Representation of Recommended Layout without Figure 8. Schematic Representation of Recommended Layout with
External Bias. External Bias.
 LNK623-626

B+

CLAMP
Drain trace in close
proximity of feedback trace
will couple noise into
feedback signal

Power currents
flow in signal
source trace D FB

BP

Trace S
impedance Isource
PRI RTN Line surge
Bias winding currents can
currents flow in flow through
∆VS signal source traces device

Voltage drops across trace impedance PI-5267-012615

may cause degraded performance

Figure 9. Schematic Representation of Electrical Impact of Improper Layout.

7
 LNK623-626

Drain Clamp
Recommended Clamp Circuits

RC2 CC1 RC2

CC1
DC2

RC1
RC1
DC1
DC1

PI-5107-012615 PI-5108-110308

Figure 10. RCD Clamp, Low Power or Low Leakage Inductance Designs. RCD Clamp With Zener Bleed. High Power or High Leakage Inductance Designs.

Components R1, R2, C3, VR1 and D5 in Figure 5 comprise the clamp.
This circuit is preferred when the primary leakage inductance is greater
than 125 mH to reduce drain voltage overshoot or ringing present on
the feedback winding. For best output regulation, the feedback RC2 CC1
voltage must settle to within 1% at 2.1 ms from the turn off of the
primary MOSFET. This requires careful selection of the clamp circuit
components. The voltage of VR1 is selected to be ~20% above the RC1
reflected output voltage (VOR). This is to clip any turn off spike on the
drain but avoid conduction during the flyback voltage interval when the DC1
output diode is conducting. The value of R1 should be the largest
value that results in acceptable settling of the FEEDBACK pin voltage
and peak drain voltage. Making R1 too large will increase the discharge
time of C3 and degrade regulation. Resistor R2 dampens the leakage
inductance ring. The value must be large enough to dampen the ring
in the required time but must not be too large to cause the drain PI-5107-012615
voltage to exceed 680 V.

If the primary leakage inductance is less than 125 mH, VR1 can be
eliminated and the value of R1 increased. A value of 470 kW with an
820 pF capacitor is a recommended starting point. Verify that the
peak drain voltage is less than 680 V under all line and load conditions.
Verify the feedback winding settles to an acceptable limit for good
line and load regulation.

Effect of Fast (500 ns) versus Slow (2 ms) Recovery Diodes in

Clamp Circuit on Pulse Grouping and Output Ripple.

A slow reverse recovery diode reduces the feedback voltage ringing.

The amplitude of ringing with a fast diode represents 8% error in
Figure 11.

Black Trace: DC1 is a FR107 (fast type, trr = 500 ns)

Gray Trace: DC1 is a 1N4007G (standard recovery, trr = 2 us)

Figure 11. Effect of Clamp Diode on FEEDBACK Pin Settling. Clamp Circuit (top).
FEEDBACK Pin Voltage (bottom).

8
 LNK623-626

Clampless Designs To eliminate group pulsing verify that the feedback signal settles
Clampless designs rely solely on the drain node capacitance to limit within 2.1 ms from the turn off of the internal MOSFET. A Zener diode
the leakage inductance induced peak drain-to-source voltage. in the clamp circuit may be needed to achieve the desired settling
Therefore the maximum AC input line voltage, the value of VOR, the time. If the settling time is satisfactory, then a RC network across
leakage inductance energy, (a function of leakage inductance and RLOWER (R6) of the feedback resistors is necessary.
peak primary current), and the primary winding capacitance determine
The value of R (R5 in the Figure 13) should be an order of magnitude
the peak drain voltage. With no significant dissipative element
greater than RLOWER and selected such that R×C = 32 ms where C is
present, as is the case with an external clamp, the longer duration of
C5 in Figure 13.
the leakage inductance ringing can increase EMI.
Quick Design Checklist
The following requirements are recommended for a universal input or
230 VAC only Clampless design: As with any power supply design, all LinkSwitch-CV designs should be
verified on the bench to make sure that component specifications are
1. Clampless designs should only be used for PO ≤5 W using a VOR
not exceeded under worst-case conditions. The following minimum
of ≤90 V
set of tests is strongly recommended:
2. For designs with PO ≤5 W, a two-layer primary must be used to
ensure adequate primary intra-winding capacitance in the range 1. Maximum drain voltage – Verify that peak VDS does not exceed
of 25 pF to 50 pF. A bias winding must be added to the trans- 680 V at highest input voltage and maximum output power.
former using a standard recovery rectifier diode (1N4003–
1N4007) to act as a clamp. This bias winding may also be used
to externally power the device by connecting a resistor from the 5
bias winding capacitor to the BYPASS pin. This inhibits the
D6
internal high-voltage current source, reducing device dissipation 1N4148
and no-load consumption. 4
3. For designs with PO >5 W, Clampless designs are not practical and
an external RCD or Zener clamp should be used.
2
4. Ensure that worst-case, high line, peak drain voltage is below the R3
LinkSwitch-CV 6.34 kΩ
BVDSS specification of the internal MOSFET and ideally ≤650 V to 1%
U1
allow margin for design variation. LNK626PG
D
FB
VOR (Reflected Output Voltage), is the secondary output plus output
diode forward voltage drop that is reflected to the primary via the BP
turns ratio of the transformer during the diode conduction time. The S R4 R5
VOR adds to the DC bus voltage and the leakage spike to determine the 6.2 kΩ 47 kΩ
C4 1/8 W R6 C6
peak drain voltage. 1 µF 4.02 kΩ 10 µF
50 V C5 1% 50 V
680 pF
Pulse Grouping 50 V
Pulse grouping is defined as 6 or more consecutive pulses followed by
two or more timing state changes. The effect of pulse grouping is PI-5268-110608
increased output voltage ripple. This is shown on the right of Figure
12 where pulse grouping has caused an increase in the output ripple.
Figure 13. RC Network Across RBOTTOM (R6) to Reduce Pulse Grouping.

Top Trace: Drain Waveform (200 V/div) Split Screen with Bottom Screen Zoom
Bottom Trace: Output Ripple Voltage (50 mV/div) Top Trace: Drain Waveform (200 V/div)
Bottom Trace: Output Ripple Voltage (50 mV/div)

Figure 12. Not Pulse Grouping (<5 Consecutive Switching Cycles). Pulse Grouping (>5 Consecutive Switching Cycles).

9
 LNK623-626

2. Maximum drain current – At maximum ambient temperature, LinkSwitch-CV, transformer, output diodes and output capacitors.
maximum input voltage and maximum output load, verify drain Enough thermal margin should be allowed for the part-to-part
current waveforms at start-up for any signs of transformer variation of the RDS(ON) of LinkSwitch-CV, as specified in the data
saturation and excessive leading edge current spikes. LinkSwitch-CV sheet. It is recommended that the maximum SOURCE pin
has a leading edge blanking time of 215 ns to prevent premature temperature does not exceed 110 °C.
termination of the ON-cycle. Verify that the leading edge current
spike is below the allowed current limit envelope for the drain Design Tools
current waveform at the end of the 215 ns blanking period. Up-to-date information on design tools can be found at the Power
3. Thermal check – At maximum output power, both minimum and Integrations web site: [Link]
maximum input voltage and maximum ambient temperature;
verify that temperature specifications are not exceeded for

10
 LNK623-626

Absolute Maximum Ratings1,5

DRAIN Voltage .........................................................-0.3 V to 725 V Notes:
DRAIN Peak Current: LNK623..................................400 (600) mA4 1. All voltages referenced to SOURCE, TA = 25 °C.
LNK624..................................400 (600) mA4 2. Duration not to exceed 2 msec.
LNK625..................................528 (790) mA4 3. 1/16 in. from case for 5 seconds.
LNK626................................ 720 (1080) mA4 4. The higher peak DRAIN current is allowed while the DRAIN
Peak Negative Pulsed DRAIN Current ..................................-100 mA2 voltage is simultaneously less than 400 V.
Feedback Pin Voltage ................................................... -0.3 V to 9 V 5. Maximum ratings specified may be applied, one at a time
Feedback Pin Current ...........................................................100 mA without causing permanent damage to the product.
BYPASS Pin Voltage ..................................................... -0.3 V to 9 V Exposure to Absolute Maximum ratings for extended
BYPASS Pin Current................................................................10 mA periods of time may affect product reliability.
Storage Temperature .................................................-65 °C to 150 °C
Operating Junction Temperature...............................-40 °C to 150 °C
Lead Temperature(3) ............................................................... 260 °C

Thermal Resistance
Thermal Resistance: P Package: Notes:
(qJA) ......................................... 70 °C/W2; 60 °C/W3 1. Measured on pin 8 (SOURCE) close to plastic interface.
(qJC)1 ....................................................... 11 °C/W 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
D Package: 3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
(qJA) ......................................100 °C/W2; 80 °C/W3
(qJC)1........................................................ 30 °C/W

Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
Control Functions
Output Frequency fOSC TJ = 25 °C, VFB = VFBth LNK623/6 93 100 106 kHz

Peak-Peak Jitter Compared to

Frequency Jitter ±7 %
Average Frequency, TJ = 25 °C

Ratio of Output
TJ = 25 °C
Frequency at Auto- fOSC(AR) 80 %
Relative to fOSC , See Note C
Restart

TJ = 25 °C
Maximum Duty Cycle DCMAX 54 %
See Notes B, C

LNK623-624P 1.815 1.840 1.865

TJ = 25 °C
LNK623-624D 1.855 1.880 1.905
See Figure 15
FEEDBACK Pin Voltage VFBth V
CBP = 1 mF LNK625P, LNK625D 1.835 1.860 1.885
See Note D
LNK626P, LNK626D 1.775 1.800 1.825

FEEDBACK Pin
Voltage Temperature TC VFB -0.01 %/°C
Coefficient

FEEDBACK Pin Voltage

VFB(AR) 1.45 V
at Turn-Off Threshold

LNK623/6P
I2f = I2LIMIT(TYP) × fOSC(TYP) 0.9 × I2f I2f 1.17 × I2f
TJ = 25 °C
Power Coefficient I2f A2Hz
LNK623/6D
If=I
2 2
× fOSC(TYP) 0.9 × I f2
If
2
1.21 × I f2
LIMIT(TYP)
TJ = 25 °C

11
 LNK623-626

Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)

Control Functions (cont.)

Minimum Switch
tON(min) See Note C 700 ns
“On”-Time

FEEDBACK Pin
tFB 2.35 2.55 2.75 ms
Sampling Delay
IS1 FB Voltage > VFBth 280 330

DRAIN Supply LNK623/4 440 520

FB Voltage = VFBth -0.1, mA
Current
IS2 Switch ON-Time = tON (MOSFET LNK625 480 560
Switching at fOSC)
LNK626 520 600

LNK623/4 -5.0 -3.4 -1.8

ICH1 VBP = 0 V
BYPASS Pin LNK625/6 -7.0 -4.5 -2.0
mA
Charge Current
LNK623/4 -4.0 -2.3 -1.0
ICH2 VBP = 4 V
LNK625/6 -5.6 -3.2 -1.4

BYPASS Pin Voltage VBP 5.65 6.00 6.25 V

BYPASS Pin
VBPH 0.70 1.00 1.20 V
Voltage Hysteresis

BYPASS Pin
VSHUNT 6.2 6.5 6.8 V
Shunt Voltage
Circuit Protection
LNK623
196 210 225
di/dt = 50 mA/ms , TJ = 25 °C

LNK624
233 250 268
di/dt = 60 mA/ms , TJ = 25 °C
Current Limit ILIMIT mA
LNK625
307 330 353
di/dt = 80 mA/ms , TJ = 25 °C

LNK626
419 450 482
di/dt = 110 mA/ms , TJ = 25 °C

Leading Edge TJ = 25 °C
tLEB 170 215 ns
Blanking Time See Note C

Thermal Shutdown
TSD 135 142 150 °C
Temperature

Thermal Shutdown
TSDH 60 °C
Hysteresis

12
 LNK623-626

Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)

Output
TJ = 25 °C 24 28
LNK623
ID = 50 mA TJ = 100 °C 36 42

TJ = 25 °C 24 28
LNK624
ID = 50 mA TJ = 100 °C 36 42
ON-State
RDS(ON) W
Resistance TJ = 25 °C 16 19
LNK625
ID = 62 mA TJ = 100 °C 24 28

TJ = 25 °C 9.6 11
LNK626
ID = 82 mA TJ = 100 °C 14 17

VDS = 560 V, See Figure 20

IDSS1 50
TJ = 125 °C, See Note A
OFF-State
mA
Leakage
VDS = 375 V, See Figure 20
IDSS2 15
TJ = 50 °C

Breakdown TJ = 25 °C
BVDSS 725 V
Voltage See Figure 20

DRAIN Supply
50 V
Voltage

Auto-Restart VFB = 0
t AR-ON 200 ms
ON-Time See Note C

LNK623/624/626 2 s
Auto-Restart
t AR-OFF
OFF-Time LNK625 1

Open-Loop
FEEDBACK Pin IOL See Note C -120 mA
Current Threshold

Open-Loop
See Note C 90 ms
ON-Time

NOTES:
A. IDSS1 is the worst-case OFF-state leakage specification at 80% of BVDSS and maximum operating junction temperature. IDSS2 is a typical
specification under worst-case application conditions (rectified 265 VAC) for no-load consumption calculations.
B. When the duty cycle exceeds DCMAX the LinkSwitch-CV operates in on-time extension mode.
C. This parameter is derived from characterization.
D. Mechanical stress induced during the assembly may cause shift in this parameter. This shift has not impact on the ability of LinkSwitch-CV
to meet CV = ±5% in mass production given the design follows recommendation in AN-45 and good manufacturing practice.

13
 LNK623-626

Typical Performance Characteristics

1.200 1.200

PI-5089-012315
PI-5086-012315
1.000 1.000

(Normalized to 25 °C)
(Normalized to 25 °C)

Feedback Voltage
0.800 0.800
Frequency

0.600 0.600

0.400 0.400

0.200 0.200

0.000 0.000
-40 -15 10 35 60 85 110 135 -40 -15 10 35 60 85 110 135
Temperature (°C) Temperature (°C)
Figure 14. Output Frequency vs. Temperature. Figure 15. Feedback Voltage vs. Temperature.

1.1 300

PI-5211-080708
PI-2213-012315

TCASE=25 °C
TCASE=100 °C
250
(Normalized to 25 °C)

Drain Current (mA)

Breakdown Voltage

200

1.0 150

100
Scaling Factors:
LNK623 1.0
50 LNK624 1.0
LNK625 1.5
LNK626 2.5
0.9 0
-50 -25 0 25 50 75 100 125 150 0 2 4 6 8 10
Junction Temperature (°C) DRAIN Voltage (V)
Figure 16. Breakdown vs. Temperature. Figure 17. Output Characteristic.

1000 50 PI-5212-012615
PI-5201-012615

Scaling Factors: Scaling Factors:

LNK623 1.0 LNK623 1.0
LNK624 1.0 LNK624 1.0
Drain Capacitance (pF)

LNK625 1.5 40 LNK625 1.5

LNK626 2.5 LNK626 2.5
100
Power (mW)

30

20
10

10

1 0
0 100 200 300 400 500 600 0 200 400 600
Drain Voltage (V) DRAIN Voltage (V)
Figure 18. COSS vs. Drain Voltage. Figure 19. Drain Capacitance Power.

14
 LNK623-626

LinkSwitch-CV
FB S
1 µF BP S
5 µF 50 kΩ 10 kΩ
.1 µF S

D S
4 kΩ S1 S2
VIN
+
16 V
Curve
Tracer

To measure BVDSS, IDSS1, and IDSS2 follow these steps:

1) Close S1, open S2
2) Power-up VIN source (16 V)
3) Open S1, close S2
4) Measure I/V characteristics of DRAIN pin using the curve tracer PI-5203-012615

Figure 20. Test Set-up for Leakage and Breakdown Tests.

15
 LNK623-626

PDIP-8C (P Package)
⊕ D S .004 (.10) Notes:
-E- 1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
.240 (6.10) 3. Dimensions shown do not include mold flash or other
.260 (6.60) protrusions. Mold flash or protrusions shall not exceed
.006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-
wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 3 is omitted.
Pin 1 5. Minimum metal to metal spacing at the package body for
the omitted lead location is .137 inch (3.48 mm).
.356 (9.05) 6. Lead width measured at package body.
-D-
.387 (9.83)
7. Lead spacing measured with the leads constrained to be
.057 (1.45) perpendicular to plane T.
.068 (1.73)
(NOTE 6)
.125 (3.18) .015 (.38)
.145 (3.68) MINIMUM

-T-
SEATING .008 (.20)
PLANE .118 (3.00) .015 (.38)
.140 (3.56)

.300 (7.62) BSC

.100 (2.54) BSC .048 (1.22) .137 (3.48) (NOTE 7)
.014 (.36)
.053 (1.35) MINIMUM .300 (7.62) P08C
.022 (.56) ⊕T E D S .010 (.25) M .390 (9.91) PI-3933-081716

16
 LNK623-626

SO-8C (D Package)
0.10 (0.004) C A-B 2X
2 DETAIL A
4 B
4.90 (0.193) BSC

A 4
D
8 5

GAUGE
PLANE
SEATING
PLANE
2 3.90 (0.154) BSC 6.00 (0.236) BSC o
C 0-8
0.25 (0.010)
1.04 (0.041) REF
BSC
0.10 (0.004) C D
0.40 (0.016)
2X 1
Pin 1 ID 4 0.20 (0.008) C 1.27 (0.050)
1.27 (0.050) BSC 2X
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D

1.35 (0.053) 1.25 - 1.65

1.75 (0.069) DETAIL A
(0.049 - 0.065)

0.10 (0.004) 0.10 (0.004) C H

0.25 (0.010) 7X
SEATING PLANE

C 0.17 (0.007)
0.25 (0.010)

Reference
Solder Pad +
Dimensions
Notes:
1. JEDEC reference: MS-012.
2.00 (0.079) 4.90 (0.193) 2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
+ + + 5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
1.27 (0.050) 0.60 (0.024)
D07C PI-4526-012315

Part Ordering Information

• LinkSwitch Product Family
• CV Series Number
• Package Identifier
P Plastic PDIP-8C
D Plastic SO-8C
• Package Material
G GREEN: Halogen Free and RoHS Compliant
• Tape & Reel and Other Options
Blank Standard Configurations
LNK 625 D G - TL TL Tape & Reel, 2.5 k pcs for D Package. Not available for P Package.

17