CMOS VLSI
Design
CMOS Processing
Peter Kogge
University of Notre Dame
Fall 2015, 2018
Based on material from
Prof. Jay Brockman, Joseph Nahas, University of Notre Dam
Prof. David Harris, Harvey Mudd College
[Link]
Outline
CMOS Physical Structure
Photolithography (Using light to define objects)
Positive
Negative
Fabrication Overview
Fabrication Step-by-Step
Etching (Removal of material)
Doping of Semiconductor (Adding donor and acceptors)
Deposition (Adding material on top of wafer)
Newer Processes
CMOS Processing CMOS VLSI Design Slide 2
CMOS Cross Sections
CMOS Processing CMOS VLSI Design Slide 3
MOS Transistor Cross-section
Width
GATE
Thickness
SOURCE CHANNEL DRAIN
Length
Key Controlling Physical Parameters
Length (L) of channel
Width (W) of Channel
Thickness (tox)of gate insulator
Material types
N-type: Phosphorous doped to provide “free” electrons
P-type: Boron doped to provide “free” positive holes
Circuits-A CMOS VLSI Design Slide 4
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
nMOS transistor pMOS transistor
CMOS Processing CMOS VLSI Design Slide 5
CMOS Technology Cross Section
SiN
CMOS Processing CMOS VLSI Design Slide 6
TSMC 0.18 CMOS Cross Section
Al Metal 3
W Via 2
Al Metal 2
W Via 1
Al Metal 1
W Contact
Shallow Source SiO2
Trench Poly Drain
Isolation
(STI) Gate
CMOS Processing CMOS VLSI Design Slide 7
130 nm transistor
TiN
Spacer
Poly Si
Gate Source/Drain
CMOS Processing CMOS VLSI Design Slide 8
Photolithography
CMOS Processing CMOS VLSI Design Slide 9
Photolithography
Aka "optical lithography“
Selectively remove parts of a
thin film on top of a substrate
or the bulk of a substrate.
Uses light to transfer geometric pattern
from photo mask
to light-sensitive chemical photo resist, ("resist”), on
the substrate.
Series of chemical treatments engraves
exposure pattern into material underneath the
photo resist.
CMOS Processing CMOS VLSI Design Slide 10
Exposure
Light
Quartz
Chrome Pattern
Lens
Photosensitive Polymer Image
Substrate
CMOS Processing CMOS VLSI Design Slide 11
Photolithography Light
CMOS Processing CMOS VLSI Design Slide 12
Photolithography
Process of transferring geometric shapes on a
mask (quartz glass plate) to the surface of a
silicon wafer.
Mask is created using a photolithographic
process with an electron beam to scan the
images on the plate.
CMOS Processing CMOS VLSI Design Slide 13
Photolithography
Feature on mask Feature on mask
results in feature on silicon results in negative feature on silicon
CMOS Processing CMOS VLSI Design Slide 14
Fabrication Overview
CMOS Processing CMOS VLSI Design Slide 15
CMOS Fabrication
CMOS transistors fabricated on silicon wafer
One wafer contains tens to thousands of chips
Today wafers are up to 300 mm across
Photolithography process “prints” patterns on
the wafer.
On each step, different materials are deposited
or etched
Easiest to understand: view both top and cross-
section of wafer in a simplified manufacturing
process, circa 1980.
CMOS Processing CMOS VLSI Design Slide 16
CMOS Chips In Cross Section
[Link]
[Link]
Introduction CMOS VLSI Design Slide 17
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
nMOS transistor pMOS transistor
CMOS Processing CMOS VLSI Design Slide 18
Well and Substrate Taps
Process circa 1980
Modern processes much more complicated but more robust.
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor connection called
Schottky Diode
Very low threshold voltage
Use heavily doped well and substrate contacts / taps
A
GND VDD
Y
p+ n+ n+ p+ p+ n+
n well
p substrate
substrate tap well tap
CMOS Processing CMOS VLSI Design Slide 19
Inverter 6 Mask Set
Transistors and wires are defined by sets of masks
2D pattern selectively allows/blocks access to chip surface
Each mask controls one kind of structure
Two views will be shown in the following slides
Mask view
Vertical cross-section taken along dashed line (see previous slide)
GND VDD
nMOS transistor pMOS transistor
substrate tap well tap
CMOS Processing CMOS VLSI Design Slide 20
Mask Views
Six masks for a very simple process
n-well
n well
Polysilicon
Polysilicon
n+ diffusion
n+ Diffusion
p+ diffusion p+ Diffusion
Contact
Contact
Metal
Metal
CMOS Processing CMOS VLSI Design Slide 21
Fabrication Step by Step
CMOS Processing CMOS VLSI Design Slide 22
Silicon Growth
Single
Crystal of
Silicon
CMOS Processing CMOS VLSI Design Slide 23
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
p substrate
CMOS Processing CMOS VLSI Design Slide 24
n-well: Oxidation
Grow SiO2 on top of Si wafer
900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
CMOS Processing CMOS VLSI Design Slide 25
n-well: Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens (positive) or hardens (negative) where exposed to
light
Photoresist
SiO2
p substrate
CMOS Processing CMOS VLSI Design Slide 26
n-well: Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
Mask
Light
Photoresist
SiO2
p substrate
CMOS Processing CMOS VLSI Design Slide 27
n-well: Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Dry etch using plasma etch (CF4)
Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
CMOS Processing CMOS VLSI Design Slide 28
Plasma Etching
CMOS Processing CMOS VLSI Design Slide 29
Plasma Etcher
CMOS Processing CMOS VLSI Design Slide 30
n-well: Diffusion
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic (As) gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2
n well
CMOS Processing CMOS VLSI Design Slide 31
Ion Implantation
CMOS Processing CMOS VLSI Design Slide 32
Ion Implantation
Parameters
Acceleration Voltage
• Determines depth of implant
Integrated Current – Charge
• Determines amount of implant
CMOS Processing CMOS VLSI Design Slide 33
n-well: Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
n well
p substrate
CMOS Processing CMOS VLSI Design Slide 34
Forming the Gates
Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
When the acronym “MOS” was invented, Al was used for
the gate, instead of polysilicon.
In 45 nm technology, metal gates and hafnium oxide are
used.
Polysilicon
Thin gate oxide
n well
p substrate
CMOS Processing CMOS VLSI Design Slide 35
Batch CVD
CMOS Processing CMOS VLSI Design Slide 36
Plasma Assisted CVD
CMOS Processing CMOS VLSI Design Slide 37
CVD Reactions
Silicon
SiH4 → Si + 2 H2
Silicon Dioxide
SiH4 + O2 → SiO2 + 2 H2
Silicon Nitride
3 SiH4 + 4 NH3 → Si3N4 + 12 H2
Metal
2 MCl5 + 5 H2 → 2 M + 10 HCl
CMOS Processing CMOS VLSI Design Slide 38
Gate: Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
CMOS Processing CMOS VLSI Design Slide 39
Transistor formation:
Self-Aligned Process
Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well contact
n well
p substrate
CMOS Processing CMOS VLSI Design Slide 40
Transistor: N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
n well
p substrate
CMOS Processing CMOS VLSI Design Slide 41
Transistor: N-diffusion cont.
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
n+ n+ n+
n well
p substrate
CMOS Processing CMOS VLSI Design Slide 42
Transistor: N-diffusion cont.
Strip off oxide to complete patterning step
n+ n+ n+
n well
p substrate
CMOS Processing CMOS VLSI Design Slide 43
Transistor: P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS
source and drain and substrate contact
p+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
CMOS Processing CMOS VLSI Design Slide 44
Forming Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
CMOS Processing CMOS VLSI Design Slide 45
Metalization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
M e ta l
Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
CMOS Processing CMOS VLSI Design Slide 46
Sputter Deposition
CMOS Processing CMOS VLSI Design Slide 47
Advanced Processes
CMOS Processing CMOS VLSI Design Slide 48
Twin Tub CMOS w/STI & Al-W metal
Circa 1997
CMP Oxide
metal (Al)
TiSi TiSi
n-poly p-poly
Source NMOS Drain Drain PMOS Source
STI
P- Epitaxial Layer
P+ Substrate
contact (W)
CMOS Processing CMOS VLSI Design Slide 49
Why Changes?
CMP Oxide
Chemical Mechanical Polishing (CMP)
Flatten surface to enable multiple levels of metal
Tungsten (W) contacts and Vias
Enable use of CMP
P+ Substrate
Reduce substrate resistance and thus reduce latch-up.
P- Epi
Needed to enable p and n transistor tub doping with P+
Substrate
Shallow Trench Isolation (STI)
Reduce source and drain capacitance
Reduce source and drain spacing
Tungsten-Silicide
Reduce gate resistance
CMOS Processing CMOS VLSI Design Slide 50
Twin Tub CMOS w/STI & Al-W metal
CMP Oxide
metal (Al)
WSi WSi
n-poly p-poly
STI
P- Epitaxial Layer
P+ Substrate
Deep Tub Implant VT Adjust
(Shallow Implant)
CMOS Processing CMOS VLSI Design Slide 51
Dual Damascene Cu Process
CMOS Processing CMOS VLSI Design Slide 52
TSMC 0.18 CMOS Cross Section
Al Metal 3
W Via 2
Al Metal 2
W Via 1
Al Metal 1
W Contact
Shallow Source SiO2
Trench Poly Drain
Isolation
(STI) Gate
CMOS Processing CMOS VLSI Design Slide 53
130 nm transistor
WSi
Spacer
Poly Si
Gate Source/Drain
CMOS Processing CMOS VLSI Design Slide 54
Deep Sub Micron Progress
[Link]
CMOS Processing CMOS VLSI Design Slide 55
Intel 45 nm Transistor
[Link]
CMOS Processing CMOS VLSI Design Slide 56
TriGate or FinFET Transistor
[Link]
CMOS Processing CMOS VLSI Design Slide 57
32 and 28 nm Transistors
[Link]
CMOS Processing CMOS VLSI Design Slide 58
Intel 22 nm Tri-gate Transistor
[Link]
CMOS Processing CMOS VLSI Design Slide 59
10nm FINFET
[Link]
CMOS Processing CMOS VLSI Design Slide 60
A 10nm Protein Transistor
[Link]
CMOS Processing CMOS VLSI Design Slide 61
Carbon Nanotube Transistor
[Link]
CMOS Processing CMOS VLSI Design Slide 62