Exam-Ready Notes: Comparator, Schmitt Trigger, Wave Generators, PWM, DAC & ADC
1. Comparator
Definition: Compares two voltages and outputs HIGH or LOW depending on which is greater.
Circuit Diagram:
Vcc
|
|
Vin(+) o--|
| >---- Vout
Vin(-) o--|/
|
GND
Operation: 1. Compare V+ and V-. 2. If V+ > V-, output = VCC (HIGH). 3. If V+ < V-, output = 0V (LOW). 4.
Output is digital (saturation only).
Merits: Simple, fast. Demerits: Noise-sensitive, no hysteresis.
2. Schmitt Trigger
Definition: Comparator with hysteresis to clean noisy input signals.
Circuit Diagram (Inverting):
Vin ----R1----+----> Vout
|
|
Op-Amp
+ -
|
GND
Operation: 1. Two thresholds: Upper (VUT) and Lower (VLT). 2. Vin > VUT -> Output HIGH. 3. Vin < VLT ->
Output LOW. 4. Between VUT and VLT, output does not change (hysteresis).
Formulas: VUT = (R1/(R1 + Rf)) * VOH VLT = (R1/(R1 + Rf)) * VOL
1
Merits: Noise immunity. Demerits: Slightly complex.
3. Square & Triangular Wave Generator
A. Square Wave Generator
Circuit Diagram:
+Vcc
|
R
Vin ->+-----/\/\-----+
| |
--- |
--- C |
| |
GND Vout
Operation: Capacitor charges/discharges through R -> output flips -> continuous square wave. Frequency: f
= 1/(2RC)
B. Triangular Wave Generator
Block Diagram:
Schmitt Trigger ---> Integrator ---> Triangular Output
Operation: Square wave from Schmitt trigger -> Integrator produces linear rise/fall -> Triangular waveform.
4. PWM Generator
Circuit Diagram:
Triangle Wave
|
v
+--------------+
Vin ----| Comparator |----> PWM Output
+--------------+
2
Operation: 1. Compare Vin with triangle wave. 2. Vin > Vtriangle -> Output HIGH. 3. Vin < Vtriangle ->
Output LOW. 4. Output pulse width varies with Vin.
5. DAC
A. Resistor-Weighted DAC
Circuit Diagram:
D3--R
D2--2R
D1--4R
D0--8R
All connected to summing op-amp --> Vout
Operation: Each bit contributes current -> summing op-amp converts to output voltage.
Merits: Simple. Demerits: Resistor matching critical.
B. R-2R Ladder DAC
Circuit Diagram:
Digital Input ---- R-2R Ladder ----> Op-amp ---> Vout
Operation: Binary-weighted currents summed by op-amp -> Vout. Merits: Easy fabrication, accurate.
Demerits: Limited by op-amp accuracy.
6. ADC
A. SAR ADC
Block Diagram:
Vin --> Sample & Hold --> Comparator --> SAR Logic --> DAC --> Digital Output
Operation: 1. Sample Vin. 2. Comparator checks MSB with DAC output. 3. SAR logic sets/clears bits -> final
digital output.
3
Merits: Medium speed, high resolution. Demerits: Complexity increases with resolution.
B. Flash ADC
Block Diagram:
Vin --> Comparator Array --> Encoder --> Digital Output
Operation: Vin compared simultaneously with reference voltages -> comparator outputs encoded -> digital
output.
Merits: Very fast. Demerits: High cost (many comparators).
C. Dual Slope ADC
Block Diagram:
Vin --> Integrator --> Comparator --> Counter --> Digital Output
Operation: 1. Integrate Vin over fixed time. 2. De-integrate with reference voltage, count time -> digital
output.
Merits: High accuracy, noise immune. Demerits: Slow conversion.
ADC Comparison Table
Feature SAR ADC Flash ADC Dual Slope ADC
Speed Medium Very High Slow
Accuracy High Medium Very High
Complexity Medium High Medium
Cost Medium High Low
Noise Immunity Medium Low High