1(A). What do you mean by unconditional jump? Give example.

ANS. In assembly language programming for microprocessors, an unconditional jump (or simply JMP) is a control
flow instruction that immediately and permanently alters the sequence of program execution to a new, specified
memory address or label. Unlike conditional jumps (which only execute if a certain condition flag is set), an
unconditional jump always changes the program flow, continuing execution from the new location regardless of the
CPU's status or register values.

Example (Assembly Language Syntax)

The most common instruction used is JMP. The following example demonstrates moving a value into a register and
then immediately jumping to a different section of code, skipping the instruction immediately following the jump:

Assembly

MOV AX, 10 ; Instruction 1: Move value 10 into AX register

JMP SkipToHere ; Instruction 2: Unconditional Jump to 'SkipToHere' label

MOV BX, 20 ; Instruction 3: THIS INSTRUCTION IS SKIPPED

SkipToHere: ; The target label

MOV CX, 30 ; Execution continues here: Move value 30 into CX register

1(B). Show the use of DAD instruction.

ANS: The DAD instruction (Double ADd) in microprocessors like the 8085 is used to perform 16-bit addition, a
crucial function in an 8-bit processor.

Purpose and Use of DAD instruction

• Function: The DAD rp instruction adds the 16-bit contents of a specified register pair (rp, which can be BC, DE, HL,
or SP) to the contents of the HL register pair. The 16-bit sum is then stored back in the HL register pair.

• Syntax: DAD rp (e.g., DAD B, DAD D, DAD H, DAD SP).

• Key Feature: It is an efficient single-byte, single-instruction way to perform 16-bit arithmetic operations, especially
useful for memory addressing calculations and handling 16-bit data. Only the Carry Flag (CY) is affected by the
operation, indicating an overflow if the result exceeds 16 bits; no other flags are modified.

1(C). What is PSW?

ANS: In microprocessors, the PSW (Program Status Word) is a 16-bit register (in the 8085, it is implicitly a 16-bit
pair consisting of the Accumulator and the Flag register) that holds essential information about the current state of
the CPU and the results of recent arithmetic or logical operations.

It typically comprises:

1. Flag Register: Contains individual bits (flags) that indicate conditions such as whether the last result was zero,
negative, or if a carry occurred.

2. Accumulator (A Register): Often grouped with the flags in the 8085 architecture when treated as a 16-bit word
pair.
 The PSW is crucial for decision-making processes in the program flow (conditional jumps) as it provides the CPU
with feedback on the status of executed instructions.

1(D). State the function of XTHL instruction.

ANS: The XTHL instruction in the 8085 microprocessor performs an exchange operation between the contents of
the HL register pair and the top two bytes of the stack.

Specifically:

• The content of the L register is exchanged with the byte at the memory location pointed to by the stack pointer
(SP).

• The content of the H register is exchanged with the byte at the next memory location (SP + 1).

1(E). What do you mean by 8-bit microprocessor?

ANS: An 8-bit microprocessor is a Central Processing Unit (CPU) where the internal registers, data bus, and
Arithmetic Logic Unit (ALU) are designed to process 8 bits of data simultaneously in a single clock cycle.

This design determines the chunk size of data it can manipulate at once and typically allows it to use a 16-bit
address bus to access up to 64 KB of memory (e.g., the Intel 8085).

1(F). What is non-maskable interrupt? Give example.

ANS. A Non-Maskable Interrupt (NMI) is a hardware interrupt signal sent to the microprocessor that cannot be
ignored or blocked (masked) by the CPU's software, unlike standard maskable interrupts (IRQs). It is reserved for
critical, high-priority system events that require immediate attention to prevent data loss or system failure.

Example:

A common example is a memory parity error or a hardware failure signal from a watchdog timer. When a critical
RAM error is detected, the NMI forces the system to halt immediately to prevent the use of corrupted data, often
resulting in an unrecoverable system error message.

1(G) State the use of parity flag in 8085 PP.

ANS: The parity flag (P) in the 8085 microprocessor indicates the parity of the result of the last arithmetic or logical
operation, specifically the number of '1' bits in the accumulator.

• Set (P=1): If the result in the accumulator contains an even number of '1' bits, the parity flag is
set to 1. This indicates even parity.

• Reset (P=0): If the result in the accumulator contains an odd number of '1' bits, the parity flag is
reset to 0. This indicates odd parity.

Its primary use is in data integrity checking, particularly in communication systems, where parity bits can be used
to detect single-bit errors during data transmission.

1(H). What is tri-state buffer?

ANS: A tri-state buffer is a logic circuit that can output one of three states: high (1), low (0), or high impedance
(Z) [1]. In microprocessors, these buffers are essential for allowing multiple devices (like memory chips,
input/output ports, and the CPU itself) to share a single set of wires, known as a bus, without interfering with each
other [1].
 • Three States: The key feature is the third, high-impedance state, which electrically disconnects
the output from the circuit [1].

• Purpose: This allows a single bus line to be driven by only one device at a time, effectively acting
as an electronically controlled switch that manages data flow on the bus [1].

1(I). State the function of RIM instruction.

ANS: The RIM (Read Interrupt Mask) instruction is a multi-purpose input instruction used in the 8085
microprocessor to read and load various system status bits into the accumulator register.

Its primary functions include:

1. Reading Interrupt Masks: It allows the program to read the current masking status of the
hardware interrupts (RST 7.5, RST 6.5, and RST 5.5) to determine which ones are currently
enabled or disabled.

2. Checking Pending Interrupts: It reads the status of pending hardware interrupts to see which
ones are waiting to be serviced.

3. Serial Data Input: It reads data from the Serial Input Data (SID) pin of the 8085 CPU.

1(J). Define Assembler.

ANS: An assembler is a program that translates assembly language into machine code, which is the binary code
that a microprocessor can directly execute. It converts human-readable instructions and mnemonics into a
sequence of 0s and 1s that the processor understands and can process.

• Function: An assembler's primary job is to convert a program written in low-level assembly

language into a form that the microprocessor can execute.

• Process: It performs a one-to-one mapping from assembly instructions to the processor's

specific machine code instructions.

• Execution: The output of the assembler is a binary file or "object code" that the CPU can then
read and run.

1(K). Why is data bus bidirectional in 8085 microprocessors?

ANS: The 8085 data bus is bidirectional because data must flow in both directions: it carries data from the
microprocessor to memory or I/O devices (a write operation) and from memory or I/O devices to the
microprocessor (a read operation). This two-way communication is necessary for all fundamental operations like
reading data or instructions from memory and writing results to output devices.

• Writing data: The microprocessor sends data from its internal registers to an external device or
memory.

• Reading data: The microprocessor receives data from an external source like memory or an
input device.

2(A). Discuss all the interrupts in 8085 up.

ANS:
The 8085 microprocessor utilizes a sophisticated interrupt system comprising both hardware and software
mechanisms to handle real-time events and asynchronous processing requirements. There are five hardware
interrupt pins and eight software interrupts available to the programmer.

The system is designed with a specific priority hierarchy, where certain interrupts can be selectively enabled or
disabled (masked) by the programmer.

Hardware Interrupts (Pins)

The 8085 has five interrupt pins that external devices use to signal the CPU.
Interrupt Type Maskable? Vector Priority Triggering
Address
TRAP Vectored No 0024H Highest Edge &
Level
RST 7.5 Vectored Yes 003CH High Edge

RST 6.5 Vectored Yes 0034H Medium Level

RST 5.5 Vectored Yes 002CH Low Level

INTR Non- Yes Varies Lowest Level

Vectored
TRAP

• Characteristics: TRAP is the only non-maskable interrupt. The CPU must acknowledge this
request immediately regardless of any software instruction. It has the highest priority.

• Triggering: It requires a signal that is both positive edge-triggered and level-sensitive to prevent
false activation from electrical noise.

• Function: It is reserved for catastrophic, non-recoverable system errors like imminent power
failure or memory failures that demand immediate system attention to prevent data loss or
corruption.

2. RST 7.5, RST 6.5, RST 5.5 (Restart Interrupts)

These three interrupts are maskable and vectored.

• Masking: They can be enabled (EI instruction) or globally disabled (DI instruction), and
individually masked (selectively turned on/off) using the SIM (Set Interrupt Mask) instruction.

• Vectoring: Each interrupt automatically forces the program counter (PC) to a unique, predefined
16-bit memory address (the vector address) where the specific Interrupt Service Routine (ISR) is
located.
 • Triggering:

o RST 7.5 is edge-triggered (positive edge), capturing a single pulse to internally register
the request.

o RST 6.5 and 5.5 are level-triggered, meaning the signal line must remain high until the
CPU acknowledges the interrupt.

3. INTR (Interrupt Request)

• Characteristics: INTR is the lowest priority interrupt and is the only non-vectored hardware
interrupt. It is maskable.

• Handling: When the CPU accepts an INTR, it asserts the INTA (Interrupt Acknowledge) signal.
External hardware must then place the opcode for an instruction (usually one of the software
RST instructions) onto the data bus. The CPU reads this instruction to find out where to jump for
the ISR.

• Function: This is a general-purpose interrupt typically used with a programmable interrupt

controller (PIC) chip (like the 8259A) to manage interrupts from multiple peripheral devices.

II. Software Interrupts (RST n)

The 8085 supports eight software interrupts: RST 0 through RST 7. These are not triggered by external pins but are
executed by including the specific RST instruction directly within the program code.

• Function: They are effectively single-byte CALL instructions that jump to predefined memory
locations (vectors). They are useful for quickly accessing common subroutines or for use within
the hardware INTR acknowledgment process.

The vector address for each software interrupt is calculated as 8× N where N is the interrupt number:

Instruction Vector
Address
RST 0 0000H

RST 1 0008H

RST 2 0010H

RST 3 0018H

RST 4 0020H

RST 5 0028H

RST 6 0030H

RST 7 0038H

2(B). Write an assembly language program to count number of 1 's in one 8-bit number.

ANS: An assembly language program for the 8085 microprocessor to count the number of '1's in an 8-bit number is
provided below. This program assumes the 8-bit number is present in memory location 3000H and stores the count
of '1's in memory location 3001H.

ORG 2000H ; Set origin to 2000H

START:
 MVI B, 00H ; Initialize B register (count of 1s) to 00H

MVI C, 08H ; Initialize C register (bit counter) to 08H (for 8 bits)

LDA 3000H ; Load the 8-bit number from memory location 3000H into Accumulator (A)

LOOP:

RAR ; Rotate Accumulator right with Carry flag.

; The Least Significant Bit (LSB) moves to the Carry flag.

JNC SKIP ; If Carry flag is 0 (LSB was 0), jump to SKIP

INR B ; If Carry flag is 1 (LSB was 1), increment B (count of 1s)

SKIP:

DCR C ; Decrement C (bit counter)

JNZ LOOP ; If C is not zero, jump back to LOOP to check the next bit

MOV A, B ; Move the final count from B to Accumulator (A)

STA 3001H ; Store the count of 1s in memory location 3001H

HLT ; Halt the program execution

3(A). Explain the following: (i) Instruction cycle

ANS: The instruction cycle is the process by which a microprocessor fetches, decodes, and executes a single
instruction from memory. It consists of three main stages: fetch, decode, and execute, and is the fundamental
operation of a CPU to run programs.

Instruction cycle stages

• Fetch: The CPU retrieves the instruction from memory, with the Program Counter (PC) holding
the address of the next instruction.

• Decode: The CPU interprets the fetched instruction to determine what action to perform.

• Execute: The CPU carries out the operation described by the instruction, which could involve
calculations or data manipulation.

(ii). Machine cycle

ANS: A machine cycle is the time required to complete one operation, such as accessing memory or an I/O device,
and it is a sub-part of an instruction cycle. Each machine cycle consists of a sequence of clock pulses called T-states,
which can range from three to six, depending on the operation. Examples include fetching an opcode, reading from
memory, or writing to an I/O port.

• Definition: A machine cycle is the fundamental operation of a microprocessor for accessing

memory, reading/writing I/O, or performing other basic functions.
 • T-states: Each machine cycle is made up of several T-states, where a T-state is a single clock
period.

• Instruction Cycle: A single instruction cycle is composed of one or more machine cycles.

• Examples: Specific machine cycles include the opcode fetch cycle, memory read cycle, memory
write cycle, and I/O read/write cycles.

(iii). T-state

ANS: A T-state is one clock period of the microprocessor, which is the fundamental unit of time for any operation.
It's the time it takes to perform a single subdivision of a machine cycle. For example, fetching an instruction's
opcode typically takes four T-states.

• Definition: A T-state is the time required for one clock pulse in the microprocessor, meaning a T-
state is one clock period.

• Function: A processor performs a part of its operations, such as fetching an instruction or

reading data, in each T-state.

• Relation to machine cycles: A machine cycle, like an opcode fetch, is made up of multiple T-
states and is the time to complete a single bus operation. For example, an opcode fetch in the
8085 is a 4 T-state machine cycle.

4(A). Discuss the purpose of' Collowing pins in 8()85 kip

(I). READY

(II) RESET IN

(III) RESET OUT

(IV) HOLD

(V) HLDA

ANS: The following pins on the 8085 microprocessor serve specific control and synchronization purposes for
effective system operation and interfacing with external devices:

• (I) READY (Input): This pin is used to synchronize the microprocessor with slower peripheral
devices or memory. If the READY signal is low during a data transfer cycle, the CPU enters a wait
state and holds its current operation until the signal goes high, indicating the external device is
ready to send or accept data.

• (II) RESET IN (Input): This active-low input signal is used to reset the microprocessor to its initial
state. When held low for at least three clock cycles, it clears the Program Counter (PC) to 0000H,
disables all interrupts (except TRAP), disables the SOD pin, and tri-states the address, data, and
control buses.

• (III) RESET OUT (Output): This active-high output signal indicates that the CPU is currently being
reset. It is typically used to provide a synchronized reset signal to other peripheral devices and
ICs connected to the system, ensuring the entire system resets together.

• (IV) HOLD (Input): This pin is used by an external device, such as a Direct Memory Access (DMA)
controller, to request control of the address and data buses. A high signal on this pin indicates
the request to the CPU.
• (V) HLDA (Hold Acknowledge) (Output): This active-high signal is the microprocessor's acknowledgment of
a HOLD request. Upon receiving the HOLD request, the CPU finishes its current machine cycle and then
asserts HLDA high, relinquishing control of the buses (address, data, and control) to the external DMA controller.

4(B). Discuss briefly the following addressing modes in 8085:

(i) Implied addressing mode

(ii) Immediate addressing mode

(iii) Direct addressing mode

ANS: (i) Implied addressing mode

• Description: The instruction implicitly specifies the operands, so no operand address or data is needed in the
instruction. The source and/or destination registers are fixed as part of the operation.

• Example: CMA (Complement Accumulator) uses the accumulator as both the source and destination, without
needing to specify it.

(ii) Immediate addressing mode

• Description: The operand is provided directly in the instruction itself as part of the instruction's code. This is useful
for loading a constant value into a register.

• Example: MVI A, 05H moves the immediate data 05H into the accumulator.

(iii) Direct addressing mode

• Description: The instruction contains the 16-bit memory address of the operand. The processor fetches the data
from that specific memory location.

• Example: LDA 4050H loads the content of the memory address 4050H directly into the accumulator.

5(A). Discuss different rotate instructions in 8085 up, with suitable example.

ANS: The 8085 microprocessor provides four specific instructions to perform bit-wise rotation operations exclusively on
the Accumulator register (Register A). Rotation operations shift the bits within the accumulator to the left or right, with
bits shifted off one end wrapping around to the other end.

These instructions manipulate the Accumulator and typically involve the Carry Flag as part of the rotation path.

Rotate Instructions in 8085

1. RLC (Rotate Accumulator Left)

This instruction rotates the contents of the accumulator one bit position to the left.

• The 7th bit (MSB) is moved to the 0th bit (LSB) position.

• The 7th bit also simultaneously copies itself into the Carry Flag.

• The Carry Flag is not part of the rotation loop; it merely captures the bit that was moved
around.

Example: RLC
 Register/Flag Before RLC After RLC

Accumulator A 0100 1000

0011 (43H) 0110 (86H)
Carry Flag (CY) 0 0

If A was 1000 0000 (80H) and CY was 0, after RLC, A becomes 0000 0001 (01H) and CY becomes 1.

2. RAL (Rotate Accumulator Left through Carry)

This instruction rotates the contents of the accumulator one bit position to the left, but the rotation path includes the
Carry Flag.

• The 7th bit (MSB) moves into the Carry Flag.

• The original value of the Carry Flag moves into the 0th bit (LSB) position.

Example: RAL
Register/Flag Before RAL After RAL
Accumulator A 0100 1000
0011 (43H) 0110 (86H)
Carry Flag 1 0
(CY)
The 1 in the original Carry Flag was moved into the new LSB.

3. RRC (Rotate Accumulator Right)

This instruction rotates the contents of the accumulator one bit position to the right.

• The 0th bit (LSB) is moved to the 7th bit (MSB) position.

• The 0th bit also simultaneously copies itself into the Carry Flag.

• Again, the Carry Flag is not part of the rotation loop.

Example: RRC
Register/Flag Before RRC After RRC
Accumulator A 0100 1010
0011 (43H) 0001 (A1H)
Carry Flag (CY) 0 1

4. RAR (Rotate Accumulator Right through Carry)

This instruction rotates the contents of the accumulator one bit position to the right, including the Carry Flag in the
rotation path.

• The 0th bit (LSB) moves into the Carry Flag.

• The original value of the Carry Flag moves into the 7th bit (MSB) position.

Example: RAR
Register/Flag Before RAR After RAR
Accumulator A 0100 1010
0011 (43H) 0001 (A1H)
Carry Flag 1 1
(CY)
The original 1 in the Carry Flag was moved into the new MSB.

5(B). State the role of all flags in 8085 µp.

ANS: The five flags in the 8085 microprocessor indicate the result of arithmetic and logical operations and are used for
decision-making: the Sign flag (S), which indicates a negative result; the Zero flag (Z), which is set if the result is zero;
the Auxiliary Carry flag (AC), used for BCD operations; the Parity flag (P), which indicates if the result has an even
number of set bits (1s); and the Carry flag (CY), which is set if a carry or borrow is generated.

The role of each flag

• Sign Flag (S): Sets the D7 bit of the flag register to 1 if the result of an operation is negative. It is
used for signed arithmetic.

• Zero Flag (Z): Sets the D6 bit to 1 if the result of an operation is zero. If the result is non-zero, it
is reset to 0.

• Auxiliary Carry Flag (AC): Sets the D4 bit to 1 if a carry is generated from bit 3 to bit 4 during an
arithmetic operation. This is primarily used for binary-coded decimal (BCD) arithmetic.

• Parity Flag (P): Sets the D2 bit to 1 if the result of an operation has an even number of 1s. If
there is an odd number of 1s, it is reset to 0.

• Carry Flag (CY): Sets the D0 bit to 1 if a carry is generated out of the most significant bit (MSB)
after an addition, or if a borrow is required after a subtraction. It indicates that the operation
resulted in an overflow and is used in unsigned arithmetic and for multiple-precision arithmetic.

6(A). Briefly explain the role of ALE Signal in demultiplexing AD7-ADO in 8085 µp.

ANS: The Address Latch Enable (ALE) signal in the 8085 microprocessor is a control signal that acts as a gate for an
external address latch, which demultiplexes the AD7-AD0 bus. When ALE is high, the AD7-AD0 lines carry the low-order
address, and the latch stores this address; when ALE goes low, the same lines switch to function as a data bus for data
transfer, while the latched address remains available for memory or I/O access. This process separates the shared
address and data lines, which is essential for the microprocessor to communicate with external memory and I/O
devices.

• Multiplexing: The 8085 uses the AD7-AD0 pins for both the lower 8 bits of the address and for
the 8-bit data bus to reduce the number of pins on the chip.

• Demultiplexing: To separate these two functions, an external latch is required.

• Role of ALE:

o When ALE is high: The AD7-AD0 lines carry the low-order address (A0-A7). The ALE
signal is sent to the enable pin of the external latch, which captures and holds this
address.

o When ALE is low: The AD7-AD0 lines are now available to function as the data bus (D0-
D7) for transferring data. The latched address remains on the output of the latch,
providing a separate, stable 8-bit address for memory or I/O devices.

6(B). Write an assembly language program to transfer a memory block of 10 bytes from 2000H to 3000H in reverse
order.

ANS: Here is an assembly language program for the 8085 microprocessor to transfer a memory block of 10 bytes from
starting address 2000H to starting address 3000H in reverse order.

8085 Assembly Language Program

; Program to transfer a block of 10 bytes from 2000H to 3000H in reverse order

ORG 2000H ; Set the origin to 2000H for the source block (for simulation/assembly)

START: LXI H, 2009H ; Initialize H-L pair to point to the LAST source memory location (2000H + 10 bytes - 1)

LXI D, 3000H ; Initialize D-E pair to point to the starting destination memory location

MVI C, 0AH ; Initialize register C with the byte count (10 in decimal, 0A in hex)

NEXT_BYTE:

MOV A, M ; Move the byte from the source (M, pointed by H-L) to the accumulator

STAX D ; Store the byte from the accumulator to the destination (pointed by D-E)

DCX H ; Decrement the source pointer (H-L pair) to move backward in the source block

INX D ; Increment the destination pointer (D-E pair) to move forward in the destination block

DCR C ; Decrement the byte counter (register C)

JNZ NEXT_BYTE ; Jump to NEXT_BYTE if the counter is not zero

HLT ; Halt the program execution

6(C) Compare 8085 and 8086 microprocessor.

7(A). Write short notes on any two:

(a) I/O Interfacing

ANS: I/O interfacing in a microprocessor system is the method for enabling communication between the CPU and
peripheral devices (like keyboards, printers, etc.). It resolves the differences in operational speeds, data formats, and
control requirements between the fast electronic CPU and slower electro-mechanical peripherals.

The primary I/O interfacing techniques are:

1. Programmed I/O

In this method, the CPU is entirely responsible for managing data transfers.

• Mechanism: The CPU uses dedicated I/O instructions (like IN and OUT in the 8085
microprocessor) or memory-access instructions (in memory-mapped I/O) to check the status of
the I/O device and transfer each data item individually.

• Disadvantage: The CPU must constantly poll (repeatedly check) the device's status, which is
inefficient and wastes CPU time, especially with slow peripherals.
 • Use Case: Suitable for simple, low-speed devices where the overhead of more complex
techniques isn't necessary.

2. Interrupt-Driven I/O

This technique improves efficiency by allowing the CPU to perform other tasks while the I/O device is preparing data.

• Mechanism: When a peripheral device is ready to transfer data or complete an operation, it

sends an interrupt signal to the CPU. The CPU then suspends its current task, saves its state, and
executes a special routine called an Interrupt Service Routine (ISR) to handle the I/O transfer.
Afterward, it returns to its original task.

• Advantage: This reduces CPU idle time significantly compared to programmed I/O, as the CPU
doesn't have to wait or constantly poll the device.

• Use Case: Commonly used for devices like keyboards, mice, and network interfaces where data
transfer is unpredictable or sporadic.

3. Direct Memory Access (DMA)

DMA is used for high-speed, high-volume data transfers and aims to minimize CPU involvement.

• Mechanism: A specialized hardware component called a DMA controller manages the transfer
of data directly between the peripheral device and the main memory (RAM). The CPU only
initiates the transfer by providing the DMA controller with the source address, destination
address, and the amount of data to be transferred. The DMA controller then takes control of the
system buses and performs the transfer without the CPU's intervention.

• Advantage: Significantly increases system performance by offloading data transfer tasks from
the CPU, allowing the CPU to focus on processing.

• Use Case: Ideal for devices such as disk drives, magnetic tapes, and network cards that transfer
large blocks of data quickly.

I/O Addressing Schemes

Microprocessors use two primary ways to address I/O devices:

• Memory-Mapped I/O: The I/O devices are treated as memory locations and assigned a unique
address within the main memory address space. Any memory-related instruction
(like MOV, LOAD, STORE) can be used to communicate with the I/O device, simplifying
programming.

• I/O-Mapped I/O (Isolated I/O): The I/O devices are assigned a separate address space from the
memory. Special I/O instructions (IN, OUT) are required to communicate with these devices.
This approach allows the full memory address space to be available for memory, but requires
dedicated I/O instructions.

(B) BUS Structure of microprocessor.

ANS: The bus structure of a microprocessor consists of three main groups of conducting lines that facilitate
communication between the CPU, memory, and input/output (I/O) devices. These are the address bus, data bus,
and control bus
1. Address Bus

The address bus is a unidirectional group of wires used by the microprocessor to specify the memory location or I/O
device it wants to access.

• Function: It carries the address of the location to or from which data is to be transferred.

• Direction: Information flows only in one direction: from the CPU to memory or I/O devices.

Width: The width of the address bus determines the maximum amount of memory the system can address. For
example, a 16-bit address bus (like in the 8085 microprocessor) can address 216(64 KB) unique memory locations.

2. Data Bus

The data bus is a bidirectional group of wires used to transfer the actual data between the microprocessor and other
components.

• Function: It carries the data that is being read from or written to a specific memory location or
I/O port.

• Direction: Data flows in both directions: to the CPU (during a read operation) and from the CPU
(during a write operation).

• Width: The width of the data bus determines how much data can be transferred at one time
(e.g., 8-bit, 16-bit, 32-bit, or 64-bit). A wider bus allows for faster data transfer and better
system performance.

3. Control Bus

The control bus is a group of lines that carry control and timing signals to manage and coordinate the operations of the
entire computer system.

• Function: It transmits commands from the CPU to other components to ensure operations
happen at the correct time and without conflict. Signals include:

o Memory Read/Write: Signals to the memory whether the operation is a read or a write.

o I/O Read/Write: Signals to peripheral devices whether the operation is a read or write.

o Interrupt Requests: Signals from I/O devices to the CPU indicating a need for attention.

o Clock Signals: Provides the timing pulses to synchronize all components of the system.
 • Direction: The control bus is typically bidirectional, as control commands are sent out from the
CPU, and status signals or acknowledgments are received back.

(C). Interrupt in 8085 microprocessor.

ANS: An interrupt is a signal from an external device that requests the microprocessor to temporarily halt its current
task to service the request. The 8085 microprocessor has five hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5, and
INTR, each with a different priority, and eight software interrupts (RST 0 to RST 7). The microprocessor finishes its
current instruction, saves the program counter on the stack, and then jumps to the interrupt service routine (ISR) to
perform the task. After the ISR is complete, the processor returns to the main program by restoring the program
counter from the stack.

Hardware Interrupts

• TRAP: This is a non-maskable interrupt with the highest priority. It is both edge- and level-
sensitive.

• RST 7.5: The second highest priority interrupt, it is edge-triggered.

• RST 6.5: A level-triggered interrupt.

• RST 5.5: A level-triggered interrupt.

• INTR: This is the lowest priority hardware interrupt. It is level-sensitive and requires the external
device to provide the instruction for the service routine.

Software Interrupts

• RST 0 - RST 7: These are instructions that can be embedded in a program. When executed, they
act as interrupts and vector to specific memory locations to run their associated ISR.

Interrupt Handling Process

1. An external device sends an interrupt signal to the microprocessor.

2. The microprocessor checks the interrupt pins at the end of each machine cycle.

3. If an enabled and unmasked interrupt is detected, the processor completes its current
instruction.

4. The current value of the program counter (PC) is pushed onto the stack.

5. The interrupt flag is reset to prevent immediate interruption.

 6. The processor jumps to the address of the interrupt service routine (ISR). For non-vectored
interrupts like INTR, the external device provides the jump instruction.

7. After the ISR is executed, the saved PC value is popped from the stack, and the processor
resumes the main program.

(D). Subroutine in 8085 microprocessor.

ANS: A subroutine in the 8085 microprocessor is a self-contained block of instructions that performs a specific,
repeatedly needed task. It is written separately from the main program and is "called" from different points in the main
program to avoid code repetition and improve modularity.

How Subroutines Work

The execution of a subroutine involves the use of the stack, a Last-In-First-Out (LIFO) memory area, and specific
instructions to manage program flow:

1. Calling the Subroutine: When a CALL instruction is executed in the main program, the 8085
automatically performs the following sequence:

• The address of the instruction immediately following the CALL (the return address) is
pushed onto the stack. This is a 16-bit address, so it takes two memory locations on the
stack.

• The 16-bit Stack Pointer (SP) register is decremented by two.

• The Program Counter (PC) is loaded with the starting address of the subroutine
specified in the CALL instruction's operand. This transfers program execution to the
subroutine.

2. Executing the Subroutine: The instructions within the subroutine are executed sequentially.

3. Returning from the Subroutine: The last instruction in a subroutine must be a RET (Return)
instruction:

• The return address is popped from the top two locations of the stack into the Program
Counter (PC).

• The Stack Pointer (SP) register is incremented by two.

• Program execution then resumes at the instruction in the main program immediately
following the original CALL instruction.

4. Subroutine Instructions
5. The 8085 instruction set includes both unconditional and conditional
instructions for handling subroutines:
Instruction Comment
CALL Unconditional call to the subroutine at the specified 16-bit address.
address
CC address Call if the Carry flag (CY) is set (CY=1).

CNC Call if the Carry flag (CY) is not set (CY=0).

address
CZ address Call if the Zero flag (Z) is set (Z=1).
 CNZ Call if the Zero flag (Z) is not set (Z=0).
address
RET Unconditional return from a subroutine.

RC Return if the Carry flag (CY) is set (CY=1).

RNC Return if the Carry flag (CY) is not set (CY=0).

RZ Return if the Zero flag (Z) is set (Z=1).

RNZ Return if the Zero flag (Z) is not set (Z=0).

Advantages of Using Subroutines

• Modularity: Complex tasks can be broken down into smaller, manageable subroutines.

• Code Reusability: The same code can be used multiple times in the program without having to
rewrite it.

• Reduced Program Size: By using a single copy of the instructions, subroutines save memory
space.

• Easier Debugging: Each subroutine can be tested independently, making the debugging process
simpler.