Democratic and Popular Algerian Republic

Ministry of Higher Education and Scientific Research

FACULTY OF TECHNOLOGY

DEPARTMENT OF ELECTRONICS

MICROPROCESSOR SYSTEMS
Course & Exercises

Course material intended for third-year Bachelor's degree students in Electronics

Prepared by:
Dr. Nabil BOUKHENNOUFA

2016
 Preface
A microprocessor is a programmable logic circuit. To understand its operation, this
Course support requires the third-year Bachelor's student in Electronics to have
prior knowledge in the field of digital electronics and basic concepts acquired
in algorithms. The study of a microprocessor requires concepts at two levels; some
hardware and software concepts: ranging from electronic structure to programming. The
hardware structure is the physical structure of the microprocessor, its programming makes it a
living component.
However, this course material presents the hardware and software approach of the 8-bit microprocessor.
from the company Intel known as 8085. The latter is currently an educational tool.
very simple and very useful for beginner students in the field of microprocessors.
In this course material, I tried to build a set of introductions that include a
major part on the 8085 microprocessor and its interfaces and their programming in assembly.
I wanted to clarify what I believe constitutes the minimum knowledge that one must possess.
a university student '3rd year Bachelor's in Electronics'.
All the points mentioned are far from encompassing the list of knowledge to be possessed in this field.
They seem to me, however, useful for providing a solid background for students who would be
brought to address microprocessor-based designs.
This course material provides in the first part a historical overview and definitions of
some basic concepts in the field of microprocessor systems.
In the second part, a study was conducted on the types of memories, their technologies and
their addressing. Also, a detailed description was provided regarding the mode of operation
of the 8085 microprocessor system. The management of interrupts and input/output interfaces
(Parallel interfaces 8255A, serial interface 8250, Timer 8254 and PIC interrupt controllers
8259) is a task that is more or less complex, it requires more concentration especially during the
configuration of the interface registers.
This manuscript contains examples to thoroughly understand the application of the microprocessor.
8085 in electronic systems.
At the end of this course material, I tried to create a foundation of a minimum number of exercises.
resolved by allowing students the spirit of initiative in order to carry out the design and analysis of
systems based on 8085 microprocessors.
Dr Nabil BOUKHENNOUFA
 TABLE OF CONTENTS

CHAPTER I: THE REGISTERS

I. Generalities 1
II. Memorization Register 1
II.1. Parallel Input Parallel Output Register (PIPO)........ 1
II.2. Serial In Serial Out Register (SISO).......................... 2
II.3. Serial Input Parallel Output Register (SIPO) 2
II.4. Parallel In Serial Out Register (PISO)................. 2
III. Shift registers 3
III.1. Shift to the right 3
III.2. Left Shift 3
III.3. Shift register or circular shift register (rotation)............... 4
III.4. Bidirectional universal shift register 4 bits '74194'..................................... 4
IV. Counters 6
IV.1. Classification of meters 6
IV.2. Counting Methods 6
IV.3. Example of a synchronous 3-bit binary counter with a complete cycle.........................7

CHAPTER II: SEMICONDUCTOR MEMORY

I. Identification of the function9

II. Architecture of a memory9
III. Types of integrated memories9
III.1. Dead Memories ROM (Read Only Memory)9
III.2. Active Memories (RAM: Random Access Memory)..................................................11
IV. Structure of a direct access memory12
V. Characteristics of a memory12
V.1.Capacity12
V.2.Format12
V.3. Speed13
V.4.Consumption13

I
 V.5. Connections and power supply of the housing13
[Link].............................................................................................13
VI. Assembly of memory cases14
VI.1. Increase in the size of words15
VI.2. Increase in the number of words15

CHAPTER III: HISTORY AND EVOLUTION OF COMPUTERS

I. History of computers 16
II. Categories of computers 17
II.1. Supercomputers 17
II.2. Mainframes 17
II.3. Mini-computers 17
II.4. Microcomputers 18
III. Organization of a computer 18
III.1. Central Processing Unit (CPU).................................. 18
III.2. Memory 19
III.3. Input/Output Units................................................................................................... 19
III.4. Bus of the system 19
III.4.1. Data bus 20
III.4.2. Address Bus 20
III.4.3. Command and control bus 20
IV. Peripherals 20
IV.1. Input Devices 20
IV.2. Output Devices 21
[Link] 21
VI. Notion of program 22
VII. Structures Von Neumann and Harvard 22
VII.1. DeVon Neumann Structure 22
VII.2. Harvard Structure 23

CHAPTER IV: ARCHITECTURE AND FUNCTIONING OF A MICROPROCESSOR

I. History 24

II
 II. Definition of a microprocessor 25
III. Operating frequency 25
IV. CISC and RISC Architectures 26
[Link] of a microprocessor. 26
[Link] 26
V.1.1. Accumulator 26
[Link](Flags).......................................................................................... 27
[Link] 27
[Link] 27
V.1.5. Instruction decoder 27
[Link] 28
[Link] 28
[Link](ALU) 28
[Link] 29
VI. Operation of a microprocessor-based system 29
VI.1. Writing to memory (WRITE) 29
VI.2. Memory Reading (READ)............................................................. 29
VI.3. Communication with inputs/outputs 30
VI.4. Interruptions 30
VI.5. Direct Memory Access (DMA)................................................................. 31

CHAPTER V: STUDY OF A MICROPROCESSOR

I. History 32
II. Role of the microprocessor 32
III. Study of the 8085 microprocessor 33
IV. External architecture of the 8085 33
IV.1. Address bus and data bus 33
IV.2. Control and status signals 35
IV.3. Power supply and frequency generator 35
IV.4. Interrupt signals 35
IV.5. Serial I/O Ports 36
-AD
7se
sAbeht fogni0xe....................................................................................
uD lpi tm
D
leu.V 36
VI. Internal architecture of the 8085 37

III
 VI.1. Basic registers of the 8085 37
VI.2. Format of an instruction 38
VI.3. Opcode format..................................................................................................... 40
VI.4. Addressing Modes 40
VI.4.1. Register Addressing 41
VI.4.2. Immediate addressing 41
VI.4.3. Direct addressing 42
VI.4.4. Indirect addressing 42
VII. Instruction set of the 8085 43
VII.1. Transfer instructions 43
VII.2. Arithmetic Instructions 45
VII.3. Logical instructions 49
VII.4. Logical rotation instructions 51
VII.5. Comparison instructions 52
VII.6. Connection instructions 53
VII.6.1. Unconditional jump 53
VII.6.2. Conditional jumps 54
VII.6.3. Boucles en assembleur...................................................................................... 55
VII.6.3.1. Infinite loops 55
VII.6.3.2. Conditional loops 56
VII.7. Implementation of the stack 56
VII.8. Subprograms 58
VII.9. Conditional calls and return instructions 59
VIII. Instruction execution cycle 60
IX. Generation of deadlines 61
IX.1. Generation of a delay using an 8-bit register. 62
IX.2. Generation of a delay using a pair register 62
IX.3. Generation of a delay using two loops 63
X. Example of an assembly program for a square wave generator............................. 63
XI. Series transmission lines of the 8085 microprocessor SOD and SID............................... 64
XI.1. SOD transmission line 64
XI.2. SID Reception Line 65

IV
 CHAPTER VI: INPUT OUTPUT INTERFACES

I. Generalities 67
II. Microprocessor and interface circuits 67
III. Different types of interfaces 68
III.1. Programmable peripheral interface 8255A 68
III.1.1. Broaching of the 8255A68
III.1.2. Programming of the 8255A71
III.1.3. Example of application of the 8255A77
III.2. Serial interface 80
III.2.1. Principle of a serial interface81
III.2.2. Connecting two devices via a RS232 serial link...........................81
III.2.3. Implementation of a serial interface, the UART 825082
III.2.4. USB (Universal Serial Bus) Ports84
III.3. Timer (Timer), Intel 8254 85

CHAPTER VII: INTERRUPTIONS

I. Definition of an interruption89
II. Handling an interruption by the microprocessor89
III. Interruptions of the 808590
III.1. Software Interruptions (RST Instruction 'Restart')91
III.2. Material Interruptions91
III.2.1. Non-vectored Interrupt INTR91
III.2.2. Vectorized interrupts91
III.2.2.1. TRAP 91
III.2.2.2. RST 7.5, 6.5, and 5.5 91
IV. Programmable Interrupt Controller, PIC 8259 93
IV.1. Initialization of the PIC 8259 97
IV.2. Order Registers 99

EXERCISE SERIES

BIBLIOGRAPHY

V
Chapter I Microprocessor systems

CHAPTER I
THE RECORDS

I. Generalities
A register is a set of elementary memory (flip-flops) used to record or to
modify binary combinations called words or binary words.
There are two types of registers: Memory registers or recordings and the
shift registers.

II. Memory register [1,2]

Memory registers can be classified according to the data writing method or
of reading.

II.1. Parallel Input / Parallel Output Register:

PIPO
All the bits are transmitted and stored at the same time in this type of register (figure I.1).
a0 a1 a2 a3

D0Q0 D1Q1 D2Q2 D3Q3

Q0 Q1 Q2 Q3

Q0 Q1 Q2 Q3
Figure I.1: PIPO Register
Example:
Before the front: A0=D0 a1=D1 a2=D2 a3=D3
1 0 0 1
Q0 Q1 Q2 Q3
0 0 0 0

After the front: Q0 Q1 Q2 Q3

1 0 0 1

1
Chapter I Microprocessor Systems

II.2. Serial In Serial Out register (SISO)

It is a type of register in which the data arrives in a series and is transmitted in series.
(on a single output). It is a delay circuit.

Entry D0Q0 D1Q1 D2Q2 D3Q3 Exit

Q0 Q1 Q2 Q3

H
Figure I.2: SISO Register

II.3. Serial In Parallel Out Register

It is a type of register in which data comes in series and exits in parallel.

Entrance D0Q0 D1Q1 D2Q2 D3Q3

Q0 Q1 Q2 Q3

A0 Q1 Q2 Q3

Exit

Figure I.3: SIPO Register

The parallel transmission of information from one register to another is the easiest.
Serial transmission uses few elements, therefore it is less expensive.

II.4. Parallel In Serial Out Register (PISO)

The loading in this type of register is done in a parallel manner and the retrieval of
The information is serial. In this type of register, we need a loading signal and/or
of shift.

2
 Chapter I Microprocessor Systems
a0 a1 a2 a3
Offset
or
Loading

D0Q0 D1Q1 D2Q2 D3Q3

Q0 Q1 Q2 Q3

H Exit

Figure I.4: PISO Register

III. Shift registers [1,2]

These are circuits that transfer data from one flip-flop to another, bit by bit (1 bit at a time)
times).

III.1. Right Shift

It consists of moving the information to the right.
Example:

Before the shift 1 0 1 0 0 1 1 1

After adjustment 0 1 0 1 0 0 1 1

III.2. Left Shift

It consists of moving the information to the left.
Example:

Before shifting 1 0 1 0 0 1 1 1

After delay 0 1 0 0 1 1 1 0

3
Chapter I Microprocessor systems
III.3. Ring shift register or circular shift register (rotation)
Right rotation:

Before shift 1 0 1 0 0 1 1 1

After shift 1 1 0 1 0 0 1 1

Left rotation:

Before shift 1 0 1 0 0 1 1 1

After delay 0 1 0 0 1 1 1 1

III.4. Bidirectional universal shift register 4 bits '74194' [3]

The pinout of the integrated circuit 74194 is shown in figure I.5.

CLR 1 16 VCC
DSR 2 15 QA
A 3 14 QB
B 13 QC
4 74194
C 5 12 QD
D 6 11 CLK
DSL 7 10 S1
GND 8 9 S0

Figure I.5 : Wiring of the 74194

Specificities of the 74194

Amplified clock and control inputs
Possibility of shifting left or right
Synchronous data transfer in parallel or series
General asynchronous update
Output maintenance mode

4
Chapter I Microprocessor systems
Mode de fonctionnement CLK /CLR S1 S0 DSR DSL QA QB QC QD
1 Reset X 0 X X X X 0 0 0 0
2 Maintenance of outputs X 1 0 0 X X QA QB QC QD
3 Shift to the left 1 1 0 X 0 QB QC QD 0
4 Left shift 1 1 0 X 1 QB QC QD 1
5 Right shift 1 0 1 0 X 0 QA QB QC
6 Right shift 1 0 1 1 X 1 QA QB QC
7 Parallel loading 1 1 1 X X A B C D

Table I.1: Operation of the 74194

It is noted that the RAZ / CLR input is active at level 0 and is a priority.
2: When S0=S1=0, the state of the outputs does not change.
3 and 4: In left shift mode, S1 must be set to 1 and S0 to 0, the states of the outputs will
shift (for example, QA takes the current state from QB before the rising edge (FM) on
(CLK). It is important to note that QD takes the present state on the DSL input.
5 and 6: Right shift mode.
7: Parallel loading mode (S0=S1=1 and (FM) on (CLK)). This mode allows loading the
logical states of the outputs that will be shifted. For example, the output QA takes the logical state
present at the entrance (A).

Other registers with offset

74164: 8-input shift register
74165: 8-input shift register, inverted output
74166: 8-input shift register with serial input
74299: Bidirectional 8-bit shift register, 3-state output

Application of shift registers

The shift register function is mainly encountered in applications of:
Transmission of digital data over long distances,
• Generation of delay on logical or digital signals,
Binary numerical calculation
Stepper motor control
• ...

5
Chapter I Microprocessor systems
IV. Meters [4]
A flip-flop can have two different states at its output (0 and 1), and can thus allow for
Count from 0 to 1. With two flip-flops, you can have up to four different states: 00, 01, 10
and 11, which allows counting from 0 to 3 in natural binary. With three flip-flops, we have eight states.
(from 000 to 111), and in general with n flip-flops we have 2nstates: we can therefore count from 0 to 2n-1.

It remains to find how the n flip-flops should be connected to each other to achieve a
meter, knowing that there are several types of meters, and therefore several techniques of
realization.

IV.1. Classification of meters

In sequential logic, counters can be described by citing five characteristics:

1–The meaning of counting. It allows to differentiate:

❋The counters (increasing evolution of output value over time)
The countdown timers (decreasing evolution of the output value over time)

2–The code in which the output value is expressed. It allows to differentiate:

Natural binary counters

❋BCD counters
❋ The meters in Code Gray
Etc...

3–The type of meter switching. It allows to differentiate:

Asynchronous counters
Synchronous counters

4 - The number of bits at output, or the range of the output value. It allows to know
the set of values that the output value of the counter can take. Examples: counter
4 bits; counter from 25 to 3 (implied 5-bit counter).

IV.2. Counting Methods

The meters are differentiated by:
Complete cycle counters

❋Incomplete cycle meters

6
Chapter I Microprocessor Systems
Examples:
A 4-bit counter that counts from 0 to 15 in natural binary is a complete cycle counter.
the car's output value uses all possible combinations of its outputs.
A 4-bit counter that counts from 0 to 9 only (also called a BCD counter) is a
incomplete cycle counter, as the 16 combinations of its 4 outputs are not all
used.
A 6-bit downcounter that counts down from 53 to 12 is an incomplete cycle downcounter.
If we talk about a natural 7-bit binary counter with a complete cycle, we know that it counts
necessarily from 0 to 127.

IV.3. Example of a 3-bit synchronous binary counter with full cycle

To synthesize a 3-bit full cycle binary counter

Counter transition table

Current state Future state Entries

+
Q2 Q1 Q0 Q2 A1 + Q0 + D2 D1 D0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 0 1 1 0 1 one
0 1 1 1 0 0 1 0 0
1 0 0 1 0 1 1 0 1
1 0 1 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1
1 1 1 0 0 0 0 0 0
Table I.2: Transition table of a complete 3-bit counter

Chronogram of the meter

Q0

Q1

Q2

Figure I.6: Chronogram of the complete 3-bit counter

7
Chapter I Microprocessor systems

Implementation with D flip-flops

D2=Q2 (Q1.0)
D1=1 Q0
D0=/Q0

Flowchart

D2Q2 D1Q1 D0Q0

Q2 Q1 Q0

Q2 Q1 Q0

Figure I.7: Logigram of the complete 3-bit counter

8
Chapter II Microprocessor systems

CHAPTER II
SEMICONDUCTOR MEMORIES

I. Identification of the function

The operation of automated systems and information processing systems
requires the storage of information that can be:
instructions related to programs,
relative numerical values to data.
These systems must be equipped with a "memory" function that can receive, store, and
to provide information.

II. Architecture of a memory

Memory addressing is the way in which data is accessedstored datais inmemory.
Amemory address eGive a namenatural numberwhich designates a particular area of the
memory, or just the beginning of a zone. Most often, a data can be read or written.
(figure II.1).

Control
memory selection
sense of the data (writing/reading)
...

Address Memory Data

from the data input (writing) or output (reading)

Figure II.1: Architecture of a memory

III. Types of memories [5-9]

III.1. Dead memories ROM (Read Only Memory)

Dead memories are read-only: the data is only available for reading (output).
Data inscription in memory is possible, this is called programming. The

9
Chapter II Microprocessor Systems
content is permanent and does not depend on power supply, this type of memory is called
non-volatile. In this category of memories we find:
Masked ROM: it is programmed once, by the manufacturer, during production.
Fuse PROM or FPROM: only one programming is possible, it
is done by "burning" fuses. It is programmed using specialized equipment
called programmer.
OTP (One Time Prom): the content can be modified once by the user using a
programmer.
UVPROM: it is erasable with ultraviolet light. It takes 10 to 20 minutes to erase it.
(erasure of all memory capacity). It is then reprogrammable.
EEPROM or E2PROM: It is electrically erasable (address erasure by
address). It is then reprogrammable.
EPROM FLASH: It is electrically erasable more quickly (erasure of all
the capacity of the memory). Its programming time is faster, and its cost of
fabrication is weaker than the EEPROM.
The dead memory being immutable once it has been built, there is no question of going
and write afterwards.
The creation of a dead memory is child's play: it is enough, in the circuit of the
RAM, that each address line is connected (through a diode) or not to each line of
data (according to the value that the manufacturer wanted to write in this bit at this address), this
the last being connected to the ground via a resistor. In practice, we will have figure II.2.

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Data

Selection
A0

A1
Address

A255

0V
Figure II.2: Internal structure of a ROM memory

10
Chapter II Microprocessor Systems
III.2. Live Memory (RAM: Random Access Memory)
The volatile memories are for reading and writing: the data is available for reading (output) or
in writing (input). A written value can be read at any time thereafter. The
content is lost if the power is cut, this type of memory is called volatile. In
in this category of memories we find:
Static RAM (SRAM) in which information is stored by
a toggle and retained as long as the power is present, it is made using technology
MOS (4 or 6 transistors for a flip-flop).
Dynamic Random Access Memory (DRAM) which uses a capacitor as a cell
memory (a stored bit) of information. This information tends to degrade due to
leak currents, which requires periodic refreshing (on the order of milli
second).
Advantage: greater integration and lower cost.
Disadvantage: use of additional memory refresh logic
(integrated for some in the case, therefore transparent to the user). With the SDRAM
(used particularly in PCs) access times are lower (virtually equivalent)
to those of the SRAM).
The assembly of figure II.3 constitutes a memory of 256 bytes. Each bit is designated by
a square (tipping).

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Lecture
or Writing

Ready

Selection
A0

A1
Address

A255

Data
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Figure II.3: Internal structure of a RAM memory

11
Chapter II Microprocessor Systems
IV. Structure of a direct access memory
Memory (figure II.4) can be viewed as a large vector (array) of words or bytes.
A memory word stores information on D bits.
A memory word contains several memory cells.
A memory cell stores a single bit.
Each word has its own address.
An address is a unique number that allows access to a memory word.
The addresses are sequential (consecutive).
The size of the address (the number of bits) depends on the capacity of the memory.

D bits of data A bit of addresses

01.........011 00.......00
11.........001 00.......01
00.........110 00.......10
. 2Acombinations with
. A bits of addresses
.
.
11..........100 11.......11
Figure II.4: Structure of a direct access memory

V. Characteristics of a memory

V.1. Capacity
The capacity of a memory represents the number of bits that can be addressed, it is
expressed in bits.

Addressing capacity in bits = 2AxD bits

Example: EPROM _ M 27C512: memory of 512 Kbits or:

512 x 1024 = 524288 bits

V.2. Format
It is the arrangement of bits in memory, corresponding to the format of the data bus.
For example, for the EPROM M 27C512, the format is 8 bits (1 Byte).
Reminders: 1ko = 1 Kilobyte = 210Octets = 1024 Octets,
1Mo = 1 Mega Byte = 210KO = 220Octets,
1Go = 1 Gigabyte = 210MO = 230Octets.
12
Chapter II Microprocessor Systems
V.3. Speed
Two main parameters characterize the speed of a memory:
the access time: it is the time that separates the moment when the addresses are positioned and
stable and the moment when the data is available on the output bus (100ns for the
EPROM M 27C512
The cycle time: it is the minimum time interval that must separate two requests.
of writing or reading.

V.4. Consumption
It varies according to the state of the memory.

Active state: at the moment when a read or write operation is requested, the
consumption is more important (30mA for the EPROM M 27C512).
Passive state: when the memory is not in use, the consumption is lower.
(100μA for the EPROM M 27C512).
Standby mode: to reduce consumption without losing information, we power the
memory (RAM) under reduced voltage (3V instead of 5V), but the system cannot
function.

V.5. Broaching and feeding of the casing

In general, memory is powered at +5V.
Characteristic brooches:
Address lines (Address Inputs).
I/O: input / output data.
VDD and GND: power supply (Power and GrouND).
R /W: control of read/write input for RAM (Read / Write control input).
CE: validation of the circuit (Chip Enable). If the circuit is not validated, the outputs are high.
impedance.
OE: output validation (Output Enable). If the outputs are not validated, they are in
high impedance.

V.6. Operating cycle

The exchanges of a memory with the outside take place according to a well-defined procedure.
given by the state of memory management signals.
Example: Read cycle of a SRAM
To read the contents of a memory, one must:

13
Chapter II Microprocessor systems
present an address on the address bus
select the case through the 'Chip Enable (CE)' or 'Chip Select'
(CS) »,
validate the memory in read position (R/W in read position _ read),
after a certain access time, the data is available at the output on the bus of
data. The output pins switch from high impedance state to active state.

Chronograms:

CE circuit validation

Validation lecture R/W

Data bus
Valid data
Access time

Figure II.5: Memory Access Chronograms

VI. Assembly of memory boxes [9]

Integration techniques do not allow for the manufacture of enclosures with capabilities or
sufficient formats for all applications. It is then necessary to associate several
boxes to increase the length of words or the number of words. On the other hand, the association
multiple blocks can help improve the temporal performance of memory by
running several blocks in parallel.
To obtain large memory sizes, several memory modules are combined. These
blocks are assembled:
to increase the size of the words in memory
to increase the number of words in memory

14
 Chapter II Microprocessor Systems
VI.1. Increase in the size of words
Figure II.6 shows that it is easy to associate two boxes of 2kn bits words to achieve a
block of 2kwords of 2n bits. Addressing must be applied simultaneously to both circuits.
one providing the n least significant bits and the other the n most significant bits.

Address
2kx n bits 2Kx n bits
k k k

n n

Heavyweight Low weight

Figure II.6: Increase in memory size

VI.2. Increase in the number of words

Similarly, figure II.7 shows the realization of a block of 4 x [Link] of n bits using 4
boxes of 2kx n bits. We need k+2 address lines. The k least significant bits of the address
are applied simultaneously on the 4 cases. The two high-weight bits attack a
four-output decoder. Each of these four lines allows for the selection of a case
(validation input of the box: CS). Only one box is then connected to the output lines.

Address: k bits k
of low weight k k k k

2kx n bits 2kx n bits 2kx n bits 2kx n bits

n n n n

Address: 2 bits Decoder

of heavy weight

Figure II.7: Increase in the number of words

15
Chapter III Microprocessor Systems

CHAPTER III
HISTORY AND EVOLUTION OF COMPUTERS

I. History of computers [10]

The computer, a name given in 1955 by J. Perret, is a machine for processing data.
(the information). It mainly contains a processor, memory, and mechanisms. It
is composed of a screen, a central unit, a keyboard, a mouse, and a video card. We
you can add multiple devices like the printer, the scanner, etc.
The history of computer development is as follows:
In 1937, Howard Aiked created the Mark 1, which is a programmable computer measuring 17 meters.

2.5 m long and 2.5 m high; its computation time is 5 times faster than that of
the man
In 1938, Konrad Zuse created the Z3, the first computer to use binary instead
of the decimal and that works thanks to electromechanical relays;
In 1947, there was the improvement of the Mark 1 (which was called Mark 2). The unique
the difference between the two was the replacement of the gears with components
electric
1942, the ABC (Atanasoff Berry Computer) is created. It represents the first computer.
to tube (light on = 1, light off = 0);
In 1946, it was the disappearance of mechanical parts in the ENIAC (Electronic
Numerical Integrator And Computer); it occupies 1500 m2and the appearance of the first
programs stored in memory. This 30-ton computer consumed 140
kilowatts and performed 330 multiplications per second;
In 1971, it is the series of microcomputers integrating transistors with the
the birth of the Kenback 1 which had a memory of 256 bytes;
In 1976, the first Apple computer with a microprocessor was created.
and a keyboard that consisted of further improving not only the capacity
storage, but also the processing time of the data;
In 1981, it marks a major turning point in the history of the computer with the emergence of the

first personal computer (Personal Computer). This period marks the point of
departure from everything we know today as a computer.

16
Chapter III Microprocessor Systems
II. Categories of Computers [11,6]

II.1. Supercomputers
This type of computer is larger than an adult human. This size is due to
to the impressive number of processors it contains. In their early days, the
supercomputers contained 4 to 16 processors. One of these processors alone can be enough to
to operate a mainframe (which was used for companies). Now, the
supercomputers use tens of thousands of micro-processors to meet the needs of
needs for the best most used computers.
Supercomputers are often used to carry out certain tasks such as
calculations for weather forecasting, for complex calculations (partly for the
scientists), to analyze the human genome as well as several other functions. These
computers are worth several tens of millions of dollars.

II.2. Mainframe Computers

These electronic devices are not as huge as supercomputers, but if we
let's compare the two types of computers from the same era, the central computer is less
more powerful than the supercomputer. These machines are very reliable, as they can continue to
function even if there is a power outage or updates to be done or if there are
repairs to be made inside and they can run for years without stopping. They are
as reliable, because they can share resources across networks. This is why this
are the banks, the ministries, the chains of stores, etc. that use it.
This type of computer costs from hundreds of thousands to a few million dollars.

II.3. Mini-computers
This category is no longer that significant today; aside from the fact that they were
almost always multi-user systems, their architecture is comparable to good ones
common microcomputers. In the beginning, they were simply devices that were less powerful than
mainframe computers and available at a more affordable price. Today, the systems that
that resemble a real "mini" serve as servers (web or network) and are often very
close to a very well-equipped micro-computer. On the other hand, their great capacity of
communication and redundancy (to avoid problems during failures) are rarely
seen in ordinary 'personal computers'. This type ofcomputerwhere a few
tens to several hundreds of thousands of dollars.

17
Chapter III Microprocessor Systems
II.4. Microcomputers
Their power continues to grow, to the point where it is often the capacity of the equipment
that can be added to differentiate them from mini-computers. Moreover, they are rarely
used as multi-user systems. Two categories can be distinguished:
desktop computers and laptops/notebooks (including pocket computers and
the personal assistants).
The main models today are either PC type (with Windows or Linux) or either
the Macintosh. Here is the classic example: IBM PC. These computers cost a few
hundreds to several thousands of dollars.

III. Organization of a computer [7,8,12-14]

A computer plays a key role in industrial societies. A computer can be
classified as a programmable circuit that allows control of industrial processes.
A computer allows reading instructions from memory, acquiring binary data.
as inputs to be processed and provide the results as outputs.
A programmable machine can be represented by four components: Central unit,
memory, input units entries and output units as shown in figure III.1. Such
system is called hardware part. A set of a sequence of instructions is called
A program and a set of programs is called software.

Memory

Central unit Entry unit

of treatment
(UCT)

Output unit

Figure III.1: Organization of a computer

III.1. Central Processing Unit (CPU)

It is the most important part of the computer. It handles processing and storage.
Information. A CPU is formed by three interconnected functional elements.
following:
Registers.

18
Chapter III Microprocessor Systems
UAL: Arithmetic and Logic Unit.
Control circuit.

III.2. Memory
This is the set of storage resources that the computer can use for
save data for later reuse.
Memory is used for storing two types of information:
Data: the information processed by the microprocessor.
Instructions: a set of coded information that manages the activity of the computer.
The use of memory is therefore mandatory in all systems using a
microprocessor, of which computers.
Note
Read-Only Memory (ROM) generally stores the program
system initialization (for example in the PC it stores the BIOS: Basic Input Output
system).
Random Access Memory (RAM) is used for storing programs.
users it is a volatile memory.

III.3. Input/Output Units

Input-output units will allow the computer to communicate with the world.
Outside, we find ports used exclusively for entry, and other ports
exclusively for output. There are also bidirectional ports. So the microprocessor
can read data from an input interface (e.g. mouse, keyboard, hard drive,
etc.). Similarly, it can return the result of its processing to the outside world by addressing
output interfaces (such as printers, keyboards, etc...) therefore the interfaces
Input/output will relieve the microprocessor for communication with the world.
outside.

III.4. System Bus [15]

The three modules are interconnected as shown in the previous figure around three
bus: data bus, address bus, and control and command bus.
Bus: This refers to several electronic tracks that are connected to the microprocessor. These buses
ensuring the internal and external communication of the microprocessor.

19
Chapter III Microprocessor Systems

III.4.1. Data bus

It is a set of bidirectional wires that will allow data transfer between the
different elements of the system. It is through this bus that the data that must be transmitted is sent.
to be processed by the microprocessor. Conversely, it is also through this bus that transit the
results output from the microprocessor. In other words, all incoming and outgoing data
The microprocessor's data is conveyed through the data bus which determines the length of the exchanged word.

with memory.

III.4.2. Address bus

This bus allows an element to be addressed by the microprocessor. It is unidirectional.
determines the maximum addressing capacity of the system, that is to say the maximum number of
memory associated words (e.g.: 16 bits 'address' 64 Kwords).

III.4.3. Command and Control Bus

It is a bus that allows the transport of control and command signals such as
the clock the Rd/Wr signals etc... This bus is used to coordinate all exchanges
information described above. It conveys data that validate memory and the
input/output ports. It introduces delays when information is sent
to a device that has a reduced processing speed. The command bus avoids
bus conflicts when two elements try to communicate at the same time.

Note:
In some cases, the data bus and the address bus are multiplexed onto a single one.
bus. An external logic must then perform the demultiplexing.

IV. Devices [15]

Devices can generally be classified into two types:input devices et
output devices:

IV.1. Périphériques d'entrée

Used to provide information (or data) to the computer system such as a keyboard
(text typing), mouse (pointing), scanner (document scanning)
paper),micro, webcam, andtc.

20
Chapter III Microprocessor Systems
IV.2. Output Devices
Used to output information from the computer system such as: screen, printer,
loudspeaker, etc.

V. Microprocessor [5-8,15,16]
The microprocessor, the most important element of any computer, gets its name from its
function. It is one of the only entities of the machine (in any case the most important), capable
to execute instructions. It is he who reads your programs and executes them, working with
memory, ...
The first microprocessor was commercialized on November 15, 1971, it is the Intel 4004.
4-bit. It was followed by the Intel 8008. This microprocessor was initially used to manufacture
text mode graphic controllers, but deemed too slow by the client who had requested it
conception, it became a general-purpose processor. These processors are the precursors of
Intel 8080, Zilog Z80, and the future family of Intel x86.
A microprocessor is characterized today by different functions. The first is the game.
of instructions that it is capable of executing, ranging from dozens to thousands
different instructions. The second is the complexity of its architecture, which is measured by
the number of transistors present: the higher this number, the more complex the tasks to
treatment can increase. The third is the speed of its clock which dictates the rhythm of
work. Finally, the microprocessor is characterized by the number of bits it can process (4 at its
beginnings, 128 in 2011). At its inception, it was capable of performing just under a million
instructions per second. Today, it processes more than 10 billion.
The components of a microprocessor are mainly composed of 3 elements which are
a control unit (CU), an arithmetic and logic unit (ALU) and registers. These
three elements are connected to each other by an internal bus, which allows for the exchanges of
data between the different parts of the microprocessor.
The microprocessor manipulates the digits '0' and '1' called bits. Each microprocessor
has its own instruction set in the form of a machine language. However, it is
difficult to manipulate the programs with this one. The instructions have
abbreviated terms that form assembly language.
In microprocessor systems, a word is a basic unit manipulated by
a [Link] also talk about machine word or deword. The size of a word is expressed
[Link] 'mainstream' hardware architectures, it is given inoctets, and is
often used to classify microprocessors (32 bits, 64 bits, etc.). Moreover, a
the microprocessor is all the faster as its words are long, because the data it processes is
21
Chapter III Microprocessor Systems
each cycle is more important. On microprocessors that can manipulate
different sizes of data, the size of words is chosen arbitrarily, with the aim of having
a naming convention (in particular, the instructions whose mnemonic does not contain
no explicit size indication applies to words). The size is usually taken
of the mainrecordsof data, or the size of thedata bus.
The nomenclature most commonly used by programming language publishers
software is standardizede1 cperson follows:
8-bit data: "octet, sometimes byte»
16-bit data: 'word'

VI. Notion of program [13]

A programcomputer sciencea set of instructions intended to be executed by
a computer.
A program is a sequence of instructions that specifies step by step, in a non-
ambiguous, data representations and calculations. The instructions are intended for
manipulate the data during the execution of the program.
A source program is code written in a programming language. It can
être compilé vers une forme binaire, ou directement interprété.
A binary program describes the instructions to be executed by a microprocessor.
digital form. These instructions define a machine language.

VII. Von Neumann and Harvard Structures [13]

This type of microprocessor mainly incorporates two basic logic units:
The Arithmetic and Logic Unit (or ALU in English), responsible for performing operations
centrals (of multiplication, addition, subtraction, rotation type, etc.)
The unit in charge of Inputs/Outputs, which manages the flow of data between the core of
microprocessor and the memories or the ports.
There are two fundamental types of structures, called 'Von Neumann' and 'Harvard'.

VII.1. Von Neumann Structure

A microprocessor based on a Von Neumann architecture stores the programs and the
data in the same memory area (figure III.2). An instruction contains the code
operating and the address of the operand.

22
Chapter III Microprocessor Systems

Address
Memory Entries Unit
Program Arithmetic
Outputs
and data and Logic
Data

Figure III.2: Von Neumann Structure

VII.2. Harvard Structure

This structure is distinguished from Von Neumann architecture solely by the fact that the
memory programs and data are separated. Access to each of the two memories is done
through a distinct path (figure III.3). This organization allows for the transfer of an instruction and
simultaneous data, which improves performance.

Address Address
Memory Entrées Unit Memory
Program Arithmetic Data
Outputs
and Logic
Data Given

Figure III.3: Harvard Structure

23
Chapter IV Microprocessor systems

CHAPTER IV
ARCHITECTURE AND FUNCTIONING
OF A MICROPROCESSOR

I. History [16]
The first microprocessor, the Intel 4004 from the computing company Intel, was created in 1971.
It is composed of 2300 transistors and executes 60000 instructions per second. In comparison,
A modern microprocessor like the Intel Pentium 4 includes several tens of
millions of transistors and executes several billion instructions per second.
In fact, the history of the microprocessor is closely linked to that of the microcomputer and that of the
micro-computing in general. The Intel 8080, created in 1974, is notably one of the first
8-bit microprocessors suited for a personal computer. It had a strong influence
the architecture of the Z80 of the company Zilog and, to a lesser extent, that of the range of
80x86 microprocessors (80186, 80286, 80386, 80486) and the various developments of
Pentium, equipping here or today the big majority of PC.
Moreover, Macintosh microcomputers are equipped with Motorola microprocessors.
(68000 family, integrated into the first commercially released Macintosh in 1984) and, since 1998, of
RISC (Reduced Instruction Set Computing) microprocessors of the Power PC series,
developed in collaboration by the American firms Apple, IBM, and Motorola.
Pioneer of micro-computing and creator of the first microprocessor, Intel dominates the
microprocessor market with about 80% market share. The company AMD follows
with nearly 20% and all other companies representing less than 1% of the market.
The situation is a little different for specialized microprocessors where other companies
are still present (notably Texas Instruments in the United States and SMT Electronic in
Europe.
It should be noted that in a computer, there is not just one processor but there are
many processors that manage independently: the sound card, the graphics card,
SCSI card, etc... But it is the microprocessor or CPU (Central Processing Unit) that is
in charge of processing all the information of these components.
The successive processors have indeed been built gradually by adding to each
instruction processor and additional features, while maintaining
each time the specifications of the previous processor.
24
Chapter IV Microprocessor Systems
The evolution of Intel microprocessors over time is summarized in Table IV.1.
This evolution mainly depends on the integration density, the frequency, the size of
address bus and the size of the data to be processed.

Year Name of Initial speed Bus Just from Memory

Microprocessor
of appearance transistors from the clock of addresses data addressable
4004 1971 2.300 108 KHz 10 bits 4 bits 640 bytes
8008 1972 3.500 200 KHz 14 Bits 8 bits 16 K
8080 1974 6.000 2 MHz 16 Bits 8 bits 64 K
8085 1976 6,500 5 MHz 16 Bits 8 bits 64 K
8086 1978 29,000 5 MHz 20 Bits 16 bits 1M
8088 1979 29,000 5 MHz 20 Bits 8 bits 1M
80286 1982 134,000 8 MHz 24 Bits 16 bits 16 M
80386 1985 275,000 16 MHz 32 bits 32 bits 4G
80486 1989 1.2 M 25 MHz 32 bits 32 bits 4G
Pentium 1993 3.1 M 60 MHz 32 bits 32/64 bits 4G
Pentium Pro 1995 5.5 M 150 MHz 36 bits 32/64 bits 64 G
Pentium II 1997 8.8 M 233 MHz 36 bits 64 bits 64 G
Pentium III 1999 9.5 M 650 MHz 36 bits 64 bits 64 G
Pentium IV 2000 42 M 1.4 GHz 36 bits 64 bits 64 G

8 external bits and 16 internal bits

Table IV.1: Evolution of microprocessors

II. Definition of a microprocessor

The microprocessor is the brain of the computer. It allows for manipulation and circulation of
information and execute the instructions stored in memory. It is the essential component
of a computer, where the main calculations are performed. All the activity of the computer is
paced by a unique clock.

III. Operating Frequency

Microprocessors arecadencedrunsignal d'horloge (signaloscillating reimposing gullet
a pace of transfer between circuits). In the middle of the1980sthis signal had a frequency
from 4 to8 [Link] the 2000s, this frequency reaches 3 GHz. The higher this frequency is
higher, the microprocessor can execute the basic instructions at a high rate.
programmes.
The increase in frequency has drawbacks:
thethermal dissipation ofA given circuit is proportional to the square of its frequency.
operation, this requires having an appropriate cooling solution for the processor;

25
Chapter IV Microprocessor systems
the frequency is notably limited by the switching times of thelogic gates:he is
necessary that between two "clock ticks", the digital signals had time to
traverse the entire route necessary to execute the expected instruction; to speed up the
treatment, it is necessary to act on many parameters (size of atransistorinteractions
electromagnetic interactions between circuits, etc.) that it becomes increasingly difficult to improve
(while ensuring the reliability of the operations).

IV. CISC and RISC Architectures

Current general-purpose processors are divided into two main categories called CISC
for Complex Instruction Set Computer and RISC for Reduced Instruction Set Computer. The
Processors in these two categories are distinguished by the design of their architectures.
CISC processors have an extensive set of complex instructions.
Each of these instructions can perform several elementary operations such as loading
a value in memory, perform an arithmetic operation and store the result in memory. At
In contrast, RISC processors have a reduced instruction set where each instruction
perform a single elementary operation. The instruction set of a RISC processor is more
uniform. All instructions are coded to the same size and all are executed in the
same time (a clock cycle in general).

V. Architecture of a microprocessor [5-8,15,16]

A microprocessor is made up of the following three interconnected functional elements:
Registers.
UAL: Arithmetic and logic unit.
Control circuit.

V.1. Registers
In aprocessora register bank is an internal memory in the processor, in which
are gathered therecords of theprocessor. In themicroprocessorsthe register benches
are generally carried out usingStatic RAM (SRAM)scules).

V.1.1. Accumulator
This is a general-purpose register receiving operands and results.
intermediaries or results coming from the arithmetic and logic unit. They avoid
frequent memory accesses, thus reducing computation times. So most of the
Arithmetic and logical operations are performed in the accumulator.

26
Chapter IV Microprocessor Systems

V.1.2. State Register (Flags)

The state register serves to hold the state of certain operations performed by the processor.
For example, when the result of an operation is zero, this triggers a specific bit (bit Zero)
"Z" of the status register to have the value "1". The status register also contains other bits: sign
of the result, retained from the addition or carried over from the subtraction, ...

V.1.3. Program counter

The program counter contains the address of the next instruction in memory that must
to be executed. In other words, it must indicate to the processor the next instruction to be executed.
Le registre compteur de programme est constamment modifié après l'exécution de chaque
instruction so that it points to the next instruction. The microprocessors of the Intel family
depend entirely on the program counter register to know the instruction
next.

V.1.4. Instruction Register

Each operation that the microprocessor must perform is encoded (that is, for each
Instruction for assigning a code that cannot be modified or changed by another code.
called "instruction code" or "operation code". To execute an instruction the
microprocessor transmits the address found in the program counter register to the
memory, the memory returns to the microprocessor the byte addressed by it (the code of
the instruction). This will be stored in a register called the instruction register. So the
The instruction register contains the next instruction to be executed by the processor.
This instruction will be sent (by a data bus) to the instruction decoder which will be
in charge of interpreting.

V.1.5. Instruction Decoder

He is the one who will interpret the instruction contained in the instruction register. That is to say
What operation needs to be performed (transfer, addition, subtraction, wiring,...) and how?
go get the required operands for this operation (for example, the numbers to
The instruction decoder then communicates with the control unit and
controls that can trigger events accordingly. For example, if the decoder
the 8085 microprocessor receives the byte 00000110 (the MVI B, 8-bit data), it knows that the
the processor must fetch another byte from memory (data) to complete
the instruction.

27
Chapter IV Microprocessor Systems
V.1.6. Address registers
These registers are used to manage memory addressing. Indeed, the processor can use a
register or a pair of registers to access a memory location, and since the
registers can be incremented or decremented so we can easily access some
data that is located in memory in an adjacent manner (such as arrays).

V.1.7. Stack Pointer

The stack pointer points to the top of the stack (TOS: Top Of Stack) in memory. A
A stack is a set of data stored in memory in such a way that only the data
The 'above' is available at a given moment. To retrieve the data under that of the
for example, we must first remove the one on top. The role of the stack pointer (and of
the stack it points to) is as follows: When a processor executes an instruction, it
It is possible that it may be interrupted by an "Interrupt" (that is to say, a call to the processor.
who is prioritized in the instructions of the program he is handling). He must then stop taking care of
of the instruction he is currently addressing to take care of the interruption. When
the interruption will be addressed, he will return to the instruction he was handling when it occurred

interrupted. But for that, he must remember this instruction as well as the state of
certain registers at the time he was processing the instruction. So as not to lose them, he
temporarily place in a stack (inside RAM for example) and
they can be retrieved once the interruption is handled. The stack pointer (SP) thus provides
the memory address of this temporary stack.
Stacks offer a new way to access data in main memory, which
is widely used to temporarily store values.

V.2. Arithmetic and Logic Unit (ALU)

As its name indicates, this unit can execute two types of operations.
Arithmetic operations: They include addition and subtraction which are
basic operations (a subtraction is an addition with the two's complement). The
processed data is considered in whole number representations.
Logical operations: These operations are performed bit by bit on the bits of the same weight.
two words, such as And, Or, Not, Exclusive Or, as well as rotation operations and
shift (arithmetic and logical).
She receives her operands (the bytes she manipulates) from the data bus. These can
coming from accumulator A and the registers or memory. At the end of an operation,
The UAL can modify certain bits of the status register.

28
Chapter IV Microprocessor systems
V.3. Control and Command Unit
Synchronized by the clock signal, it is what triggers the events in the
processor (it can be noted in this regard that it is connected to all other components
the processor). For example, when information is transmitted on a bus, this information is
destined for a single location (for example, a register). It is therefore the control unit and
control that will "unlock" the entry to this destination so that the information can circulate
on the bus can enter (and not enter elsewhere at the same time).
It is essentially an automaton executing the various sequences specific to
each instruction. This automaton can be implemented in several ways (wired or micro-
programmer and in both cases the instruction set is fixed). Most of the units of
processing is micro-programmed and therefore has fixed instruction sets.

VI. Operation of a microprocessor-based system [5-8,13,15,16]

VI.1. Writing in memory (WRITE)

To write data to memory (figure IV.1.a), the microprocessor must place
the address of the data on the address bus (its location in memory) then it places
the data on the data bus and finally generates the WRITE signal (write command in the
memory).

VI.2. Reading the memory (READ)

To read data from memory (figure IV.1.b), the microprocessor must know its
location, indeed it deposits its address on the address bus and then generates the READ signal
(it requests a memory read operation) then the data will be routed to the
microprocessor through the data bus. The data will be stored in a register in the
microprocessor.
Memory Memory
1000H 1000H
Address Address
55H 1000H 55H 1000H

Writing Lecture
CPU CPU

55H 55H
Data Data

(a) (b)
Figure IV.1: Writing and reading memory
29
Chapter IV Microprocessor systems

VI.3. Communication with inputs/outputs

It can be a flow of information from the outside to the computer (acquisition via the
keyboard, a network connection, a hard drive, etc...), or from a flow from the computer to
the outside (screen, network, disk, etc.).
The data exchanged between a device and the processor passes through the interface (or
controller) associated with this device. The interface has a buffer to store
the data exchanged (depending on the type of interface, this buffer is made of only 1
octet to a few Mega-octets). The interface also stores information to manage the
communication with the device:
command disinformation, to define the mode of operation of
the interface: transfer direction (input or output), data transfer mode (by polling
or by interruption), etc. This order information is communicated to the interface
during the initialization phase of it, before the start of the transfer.
state disinformation, which records how the transfer is made
(transmission error, reception of information, etc.). This information is intended for
processor.
During the execution of input/output instructions, the processor sets its IO/M line to 1 and
presents the E/S address on the address bus. The IO/M signal indicates to the decoding circuits.
of addresses that it is not a main memory address, but the address of a
input/output interface.
Note:
The communication between the microprocessor and the input/output interfaces can be serial.
(on a single wire bit by bit) or parallel (on several wires).

VI.4. Interruptions
Interrupts allow the hardware (device) to communicate with the processor.
In some cases, we want the processor to respond quickly to an external event:
arrival of a data packet on a network connection, keystroke on the keyboard,
modification of the hour. Interruptions are mainly used for management of
computer peripherals, indeed microprocessor-based systems can
include several physical elements such as the screen, CD players, DVD players,
the ADCs (Analog to Digital Converters) and DACs (Digital to Analog Converters) etc... But there
Most of these peripherals only need the microprocessor at certain times. If a
The device requires intervention, it generates its own interruption request.

30
Chapter IV Microprocessor systems
An interruption is signaled to the processor by an electrical signal on a special pin.
Upon receiving this signal, the processor 'handles' the interruption at the end of the instruction.
that he was executing. The interrupt handling consists of either:
–to ignore it and proceed normally to the next instruction: this is only possible for
certaines interruptions, nomméesinterruptions masquables. Il est en effet parfois nécessaire
to be able to ignore interruptions for a certain period of time, to carry out processing
very urgent for example. When the processing is done, the processor...
interruptions and takes them into account.
to execute an interrupt handler. An interrupt handler is a
program that is called automatically when an interrupt occurs. The address of
the start of the handler is given by the interrupt vector table (see chapter
interruptions).
Note:
Sometimes the microprocessor is requested by several interrupts at the same time, for
Responding to these calls, a priority order is often taken into account for their processing.
Interruptions considerably increase the efficiency of the processor.
Interruptions are of two types:
Material interruptions.
Software interruptions.

VI.5. Direct Memory Access (DMA)

When a memory transfer is necessary from RAM to an I/O port, the
the microprocessor reads the first byte in memory and loads it into one of the registers of
microprocessor. The microprocessor then writes the previously stored byte to the port
appropriate I/O.
As a result, the microprocessor performs repeated read and write operations.
Thus, a certain amount of time is lost between the processing of each byte. To remedy this
problem, a procedure is developed for direct memory access (Direct Memory
Access), which allows transferring data from RAM to the I/O port without going through
by the microprocessor. For this, a DMA controller takes on the role of
microprocessor, that is to say it manages the transfers from RAM to the I/O ports.

31
Chapter V Microprocessor Systems

CHAPTER V
STUDY OF A MICROPROCESSOR

I. History [17]
The first microprocessor was manufactured by INTEL in 1971. It was a 4-bit chip named 4004.
intended to equip desktop calculators. In 1972, INTEL produced the first
8-bit microprocessor named 8008 in reference to its predecessor. This microprocessor was
intended to fulfill a contract for the manufacture of a terminal. In reality, the 8008 turned out to be too
Ready to meet the terminal specifications, and INTEL has decided to attempt the launch.
of this product on the consumer market. The enormous success of this initiative was the origin of
the massive production of microprocessors. Following the success of the 8008, INTEL produced
As early as 1974, the 8080 would become the first element of the future family of microprocessors.
From which manufacturer. In 1974, MOTOROLA, another silicon foundry, decided to launch the 6800.
which will also mark the beginning of a great family. The 1970s then see the emergence of
small microprocessor manufacturing businesses often formed by
defectors from the two major companies. Notably, we can mention MOSTEK with its 6502.
very inspired by the 6800 and ZILOG with its Z80 which constitutes a technical improvement over the 8080

increased number of records, simplification of feeding...

Very quickly, the 8 bits begin to reach the limits of their performance and the manufacturers
are looking at new solutions. The main criticisms of the 8 bits are: - few
accessible memory space (64K bytes) - few types of information handled (1 or 2
(octets) - not suitable for multiprocessor architectures - few addressing modes for
for all these reasons, manufacturers are starting to study a new generation of
microprocessors. So we will see the emergence of 8-bit microprocessors more
powerful allowing easier manipulation of 16-bit information and providing
new addressing possibilities like the MOTOROLA 6809 or the INTEL 8085.

II. Role of the microprocessor

The microprocessor is responsible for performing the following functions:
Provide synchronization and control signals to all elements of the system,
• Handle instructions and data in memory,
Data transfer between memory and I/O devices and vice versa,

32
Chapter V Microprocessor systems
Decode the instructions,
• Perform the arithmetic and logical operations commanded by the instructions,
• React to control signals generated by inputs/outputs such as the 'Reset' signal and
the interruptions.

III. Study of the 8085 microprocessor [16]

The Intel 8085 microprocessor appeared in 1976. It is equipped with an 8-bit data bus.
and a bus of addresses with 16 address lines.
It was compatible at the binary code level with the most [Link] 8080,but required
less surrounding material, which allowed the creation ofmicrocomputers plussimple and
cheaper to build.
The "5" in the model number comes from the fact that the 8085 only required a
power supply of +5V instead of the +5V, -5V, and +12V required by the 8080. However, it was
slower than the 8080. Its speed was 1.5 million instructions per second with a
clock at 6.144 MHz and 4 cycles per instruction.
The 8085 was sold in a pack at 40 brooches, which allowed her to use abus
16-bit address and an 8-bit data bus, providing easy access to 64 KB of
memory. He is sevenregisters of8 bits (where six can be combined into three registers of 16)
bits), apointerofjust over 16 bits and oneprogram counter on16 bits. The 8085
has 256ports dinputs/outputs accessible through dedicated instructions.

IV. External architecture of the 8085 [16]

The 8085 microprocessor comes in the form of a DIP (Dual In-line Package) housing.
40 pins. Figure V.1 shows the pinout diagram of the 8085. All signals can
to be classified into six groups: (1) Address bus, (2) Data bus, (3) Control bus and
["status signals","Power supply and frequency generator","Interrupt signals"]
Serial I/O ports.

IV.1. Address bus and data bus

The number of address lines of the 8085 is 16 lines A15-A0whose low weight is
time-multiplexed with the data bus AD 7-AD0. Hence the necessity of a
demultiplexing to separately obtain the address and data buses:
8 bits of data (8-bit microprocessor);
16 bits of addresses, hence 21664 KB of addressable memory space by the 8085.

33
Chapter V Microprocessor Systems

Demultiplexing of AD signals7to AD0is done by memorizing the address when it is

present on the bus Addresses/Data, using a latch, a set of D flip-flops.
The address memory command is generated by the microprocessor: it is the
signalALE(Address Latch Enable).

+5V GND

1 2 40 20
SID 5 X1 X2 Vcc Vss
A1528
SOD 4
Address bus of
heavyweight
A821

TRAP 6 AD719
Multiplexed bus
RST 7.5 7 Addresses/Data
RST 6.5 8 AD012
RST 5.5 9
INTR 10 8085A 30 ALE
29 S0
33 S1
READY 35
34 I/O
HOLD 39
32 RD
RESET IN 36
31 WR
INTA 11
HLDA 38

3 37

RESET CLK
OUT OUT

Figure V.1: External architecture of the 8085

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Chapter V Microprocessor systems

IV.2. Control and status signals

ALE: In the high state, it implies that the bits present on the A/D bus are the address lines.
circuit 74373 memorizes these bits at its output.
RD: Read, low level active data read signal.
WR: Write, write signal of a data, active low.
IO/M: Input-Output / Memory, indicates if the 8085 addresses the memory (IO/M = 0) or the
input/output (IO/M = 1).
S1etS0State signals indicating the type of operation currently occurring on the bus. Rarely used.
in small systems.

IV.3. Power Supply and Frequency Generator

Vcc: Power supply +5V
GND: Reference mass
X1etX2 A Quartz is connected to the two pins to generate a periodic square wave signal. For
To generate a frequency of 3MHz, the crystal must have a frequency of 6MHz.
CLK (OUT): This pin can be used as a clock signal for other circuits.

IV.4. Interrupt Signals

The 8085 has five interrupt signals.
INTR (Interrupt Request): It is the signal sent by an interface indicating a request.
of interruption.
INTA: The 8085 responds to INTR by sending 0 on the INTA (Interrupt Acknowledge) line.
RST7.5 RST6.5 and RST5.5: Restart interruptions. These are interruptions
vectorized that transfer control to a specific memory location. These lines are
priority over INTR. The priorities are ranked in descending order from 7.5, 6.5 to 5.5.
TRAP: (Non Maskable Interrupt): priority interruption over INTR.
HOLDetHLDA: demand signals for direct memory access (DMA) agreement.
READY: synchronization entry with memory.
RESET IN: When this signal is at 0, the program counter is reset to 0, the buses are in
high impedance and the microprocessor restarts.
RESET OUT: This signal indicates that the microprocessor has just been restarted, this signal
may be used by other circuits.

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Chapter V Microprocessor Systems
IV.5. Serial I/O ports
The 8085 has two signals for the implementation of serial transmission: SID (Serial
and SOD (Serial Output Data). In serial transmission, the data bits are
transmitted on a single line one after the other as in the case of a telephone line.

V. Demultiplexing of AD buses7-AD0
Figure IV.2 shows the usefulness of latches for bus demultiplexing. The AD bus7-AD0is
connected to the inputs of the 74LS373 latches. ALE is connected to the enable (G) pin of the
latches. When ALE is high, the latches are transparent; this means that the outputs of
latches change depending on the inputs. When the microprocessor sends a 0 on ALE,
The address is stored until the next ALE and the output of the latches represents the bus.
lightweight address A7-A0The diagram in figure V.2 indicates a memory read of
the value 4FH from address 2005H.
0 A15
A15
0 A14
1
A13
0
A12Address bus
20H 0
A11 of strong weight
Microprocessor
0
A10
8085 0
A9
0
A8 A8
ALE Validation G
AD7 0 D Q 0 A7
AD7
AD6 0 0 A6
AD5 0 0 A5
AD4 0 0 A4 Address bus
0 05H 0
AD3 A3 lightweight
AD2 1 1
A2
AD1 0 74LS373 0
A1
AD0 1 1
AD0 A0
0 D7
1 D6
0 D5
0 D4 Bus of
4FH 1 D3 data
1 D2
1 D1
1 D0
Figure V.2: Demultiplexing of address and data buses AD7-AD0
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Chapter V Microprocessor Systems

VI. Internal architecture of the 8085 [16]

The internal structure of the microprocessor is of very high complexity. To try to
however, it can be divided into four main sections: Accumulator, registers
generals, UAL, Instruction Register, Address Registers, instruction decoder,
interrupt controller, serial input/output controller, and sequencer.

Accumulator Records Address bus Accumulator A (8)

16 bits
generals
B (8) C (8)
ALU
D 8 E (8)
Flags Registers
pointers of Data bus H 8 L (8)
memory 8 bits
Decoder
Stack pointer (16)
instructions
Program counter (16)
Control unit Control bus Data bus Address bus

Bidirectional Unidirectional
Figure V.3: Basic internal architecture of the 8085 microprocessor

All the blocks are connected with internal connections called internal bus.
Arithmetic and logical operations are performed by the arithmetic and logical unit. The
results are stored in the accumulator and the flags. The 8085 uses the bus
addresses to send the addresses to the memories and peripherals, the eight lines of
data are the transfer lines to/from memory/I/O interfaces.

VI.1. Basic Registers of the 8085

Accumulator: It's the 8-bit register A. It is part of the arithmetic and logic unit.
is used for storing data and the results of arithmetic operations and
logics
• B, C, D, E, H and L: General-purpose 8-bit registers. They have a utility similar to the
RAM, but being internal to the microprocessor, they have additional features.
registers can be combined like even registers BC, DE, and HL to achieve
16-bit operations.

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Chapter V Microprocessor systems
• PC (Program Counter): Program Counter, it is a 16-bit register that supports
the address of the next memory byte to be fetched. When a byte is loaded, the PC increments
automatically by 1 (+1), so that it points to the next byte to be loaded.
• SP (Stack Pointer): 16-bit stack pointer, its role is to indicate to the
microprocessor the address of the next available slot in the stack.
State register: It is the set of flags that forms the 8-bit state register.
The state register associated with the accumulator forms the context or PSW (Program Status Word)

of 16 bits.
Here we mention the indicators (flags) affected by an arithmetic or logical instruction.
the following notations are used:

D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY

Figure V.4 : Status register bits

Flags are flags or state indicators (status register). They indicate the state of a
operation performed by the arithmetic and logic unit. This register contains 5 bits S, Z, AC, P
and CY.
S: Sign flag (Sign bit). It is bit D.7of the result of the operation.
Z: Zero flag. If the result of the operation equals 0, this bit is set to 1. Otherwise, it is set to 0.
AC : Auxiliary Carry flag. In an arithmetic operation, when a carry is generated
by the bit D3to D4the AC is set to 1 otherwise it is set to 0. It is used in BCD codes and it
is not used by the programmer.
P: Parity-flag. After an arithmetic or logical operation, if the result contains a number
pair of 1, the P flag is affected by 1. If the result contains an odd number of 1, the
Flag P is affected by 0.
CY: Carry-flag. In an arithmetic operation, when there is a carry during addition or a
The report during a subtraction is generated by the eight bits; the CY is set to 1, otherwise it is set to 0.
This bit is accessible by the programmer.

VI.2. Format of an instruction

The program is a sequence of instructions. An instruction is a binary word describing the action.
what the microprocessor must execute, for example copying a memory cell into another,
add the content of two memory cells etc.

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Chapter V Microprocessor systems
These instructions are binary words that are usually written in hex, but for a more
great ease, we will refer to them by their 'mnemonics'. The mnemonic is a
abbreviation in Latin characters.
An instruction is made up of one or more bytes. The first field represents
the operation to be performed, known as the opcode. In the 8085, the opcode always has a size
of 1 byte. The instruction is formed either by the opcode or by the opcode and an operand. This
the last can be specified by different forms. It can be a 8-bit (or 16-bit) data,
an internal register or an address of a memory location.

Operation to be performed Operand

Figure V.5: Instruction Format

The set of instructions of the 8085 is divided into three groups:

1. Size instructions 1 byte (no operand)
2. Size instructions 2 bytes (8-bit operand)
3. Size instructions 3 bytes (16-bit operand)

Example 1:
CMA: Complement the register A.
The corresponding opcode is 2FH. CMA is the mnemonic. This instruction does not have
of the operand. Its size is therefore 1 byte (one memory position).

Example 2:
Load the value 28H into register A.
The opcode of MVI A is 3Eh. The 8-bit operand is 34h. The size of the instruction is 2 bytes.

Example 3:
LDA 1234H: Load the content of address 1234H into accumulator A.
The corresponding opcode is 3AH. LDA is the mnemonic. This instruction has
the 16-bit operand 1234H. Its size is therefore 3 bytes.
So if the address of CMA is 1000H, we will get the following:

1000H 2FH --> CMA 1003H 3AH --> LDA 1234H

1001H 3EH --> MVI A,28H 1004H 34H
1002H 28H 1005H 12H

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Chapter V Microprocessor Systems
VI.3. Opcode format
All operations, registers, and flags are identified by a specific code.
For example, the internal registers are as follows:

Codes Records Codes Even registers

000 B 00 BC
001 C
010 D 01 DE
011 E
100 H 10 HL
101 L
111 A 11 AF or SP
110 Reserved for the
memory operations

Table V.1: Encoding of Registers

Some instruction codes are identified in table V.2 as follows:

Function Operation code

1. Left rotation of each bit of the accumulator by 00000111=07H
a position
2. Add the contents of the register and 10000 SSS
the accumulator
[Link] (MOV) the content of the Rs (source) register to 01 DDD SSS
register Rd (destination) Rd Rs

Table V.2: Coding of instructions

This instruction is completed by adding the registry code. For example:

The code for ADD B is: 10000 000=80H.
This instruction is completed by adding the code of the two registers. For example:
The code for MOV C,A is: 01 001 111=4FH

VI.4. Addressing modes

The ways to designate the operands are called 'addressing modes'.
The 8085 microprocessor has four addressing modes:
Register addressing mode.
Immediate addressing mode.
Direct addressing mode.
Indirect addressing mode.
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Chapter V Microprocessor Systems
VI.4.1. Register addressing
This addressing mode concerns any transfer or operation between two 8-bit registers.
In this mode, the operand will be stored in an internal register of the microprocessor.

Example:
MOV A, B ; this means that the operand stored in register B will be transferred to the
Register A. When using register addressing, the microprocessor performs all the
internal operations. So in this mode, there is no exchange with the memory,
which increases the operand processing speed.
Memory
8085
A Flags
B C 78
D E
H L
SP
PC

Figure V.6: Register Addressing

VI.4.2. Immediate addressing

In this addressing mode, the operand appears in the instruction itself, for example:
MVI A,50H ; this means that the value 50H will be stored immediately in register A.

Memory
8085
(A)=50H Flags
B C 3E
50
D E
H L
SP
PC

Figure V.7: Immediate addressing

Note:
To load A with the value 01H, one must use MVI A,01H. To load A with the value
-01H, we must use MVI A, FFH. Such that FFH is the 2's complement of 01H on 8 bits.

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Chapter V Microprocessor Systems
VI.4.3. Direct addressing
In this mode, the operand's address is specified directly in the instruction. For example
to load accumulator A with the content of address 2000H, we must write: LDA 2000H

Mémoire
8085
(A)=52H Flags
B C 3A
00
D E
20
H L
SP
PC
52 2000H

Figure V.8: Direct addressing

VI.4.4. Indirect addressing

In this addressing mode, the address of the operand is stored in a register that must be well
obviously load it beforehand with the correct address. The operand's address will be
stored in an even register B, D, H or SP.
Example:
LXI H,1234H ; immediate addressing coded by 21H 34H 12H
MOV A,M ; indirect addressing coded by 7E
For the second instruction (MOV A,M), the content of the memory location whose address
is found in the pair register H ((HL)=1234H) is placed in the accumulator A.

Memory
8085
(A)=F3H Flags
B C 21
34
D E
12
(H)=12H (L)=34H 7E
SP
PC
F3 1234H

Figure V.9: Indirect addressing

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Chapter V Microprocessor Systems
VII. Instruction set of the 8085 [16]
For the declaration of data, we must insert after the end of the program (HLT) the
mnemonics # ORG and # DB. For example, we want to initialize the memory area starting at
starting from the memory address C050H with the data 85H, 54H, 30H, 5EH, 3AH, BFH, we must
write the following lines:
ORG C050
DB 85H, 54H, 30H, 5EH, 3AH, BFH
The instructions of the 8085 are divided into three groups:
Transfer Instructions
Arithmetic and logical instructions
Wiring instructions

VII.1. Transfer Instructions

This first group of instructions allows you to transfer (copy) data from one place to another.
another (from a register or memory or I/O interface) called source to another register (or
E/S or memory) called destination. Indeed, the content of the source is not moved, but
copied to the destination without modifying the content of the source. The transfer instructions
are summarized as follows:

Move Copy a byte of data from a register or memory address

Syntax: MOV Rd, Rs or MOV M, Rs or MOV Rd, M
As Rd: Destination register Rs: Source register and M address specified by HL
Example:
MOV C,D or MOV M,B

2. MVI: Move Immediate: Load an octet of data

Syntax: MVI Rd, 8-bit data
As Rd: Destination register
Example:
Load immediate to register A with 14H

3. OUT: Output to port: Send a byte of data from A to an output interface

Syntax: OUT address of the output port
Example:
OUT 08H

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Chapter V Microprocessor systems
4. IN: Input from Port Receive a byte of data from an input interface in A
Syntax: IN input port address
Example:
AT 09H

5. LXI: Load register pair Immediate Load a word (16 bits) of data
Syntax: LXI Rp, 16-bit data
As Rp: Even register
Example:
LXI B, 1400H ; (B)=14H and (C)=00H

6. LDA: Load Accumulator Load the accumulator with the contents of an address
memory
Syntax: LDA 16-bit Address
Example:
Load A with 2000H

7. LDAX: Load Accumulator Load the accumulator with the content of an address
memory specified in a B or D register
Syntax: LDAX Rp
As Rp: Even register B or D
Example:
LDAX B

8. STA: Store Accumulator Store the accumulator in a memory cell

Syntax: STA 16-bit Address
Example:
STA 3000H

9. STAX: Store Accumulator Store the accumulator in a memory cell that

the address is specified in a B or D register
Syntax: STAX Rp
As Rp: Even register B or D
Example:
STAX D

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Chapter V Microprocessor systems
10. LHLD: Load HL registers direct: Load the H register pair with the content of the memory location

memory.
Syntax: LHLD 16-bit Address
Example:
LHLD 2000H

11. SHLD: Store HL registers direct: Load the content of the memory location by the
content of the even register H.
Syntax: SHLD 16-bit Address
Example:
SHLD 3000H

12. XCHG: Exchange the contents of HL with DE.

Syntax: XCHG

13. XTHL: Exchange the top of the stack with HL.

Syntax: XTHL

14. SPHL: Copy HL registers into the stack pointer: Copies the contents of the HL registers
in the SP register.
Syntax: SPHL

15. PCHL: Copy HL registers into the program counter: Copy the contents of the HL registers
in the CP register.
Syntax: PCHL

VII.2. Arithmetic Instructions

The 8085 microprocessor performs several arithmetic operations including addition.
(ADD or ADI), subtraction (SUB or SUI), 8-bit increment (INR), increment
16 bits (INX), 8 bits decrement (DCR) and 16 bits decrement (DCX).
For the ADD, ADI, SUB, and SUI instructions, the microprocessor assumes that the accumulator
A is by default one of the two operands and the result will be stored in the accumulator A.
flags will be affected.
The increment and decrement instructions affect the contents of the register.
specified and affect all the flags except for the CY.

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Chapter V Microprocessor Systems
1. ADD :Addition Add the contents of accumulator A with the
content of the register or memory case.
Syntax: ADD R or ADD M
Such that R : 8-bit register and M : address of a memory cell
Example:
Load immediate value 04H into register A

Move immediate value B, 03H

ADD B
This gives (A)=(A)+(B)=04H+03H=07H S=0 Z=0 CY=0

ADI: Immediate Addition Add the content of accumulator A with a

value
Syntax: 8-bit data ADI
As R: 8-bit Register
Example:
Move Immediate A, FFH

ADI 01H
This gives (A)=(A)+01H=FFH+01H=00H S=0 Z=1 CY=1

3. SUBJECT: Subtraction Subtract the contents of the register from the contents of

the accumulator A or memory cell.

Syntax: SUB R or SUB M
As R: 8-bit register and M: address of a memory cell
Example:
Load immediate value FFH into register A

Move Immediate to Register B, 03H

SUB B
What gives (A) = (A) - (B) = FFH - 03H = FCH S=1 Z=0 CY=0

4. SUI: Immediate Subtraction Subtract a value from the content of accumulator A

Syntax: SUI 8-bit data
As R: 8-bit Register
Example:
Load immediate value 05H into register A

SUI 02H
This gives (A)=(A)-02H=05H-02H=03HS=0 Z=0 CY=0
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Chapter V Microprocessor systems
5. INR: Increment Increment the content of a register or memory location by 1 (+ 1)
Syntax: INR R or INR M
Such that R: 8-bit register and M: address of a memory cell
Example:
Load immediate value 05H into register A

INR A
Which gives (A)=(A)+1=05H-1=06H S=0 Z=0

6. DCR: Decrement: Decrement the content of a register or memory cell by 1 (-1)

Syntax: DCR R or DCR M
As R: 8-bit register and M: address of a memory cell
Example:
Load immediate value 01H into register A

DCR A
What gives (A)=(A)-1=01H-1=00H S=0 Z=1

7. INX: 16-bit Increment Increment an even register or SP (16bits)

Syntax: INX Rp
As in Rp: Even register (B, D or H) or SP
Example:
LXI SP,2000H
INX SP
This gives (SP)=(SP)+1=2000H+1=2001H S=0 Z=1

8. DCX: 16-bit Decrement: Decrement a pair register or SP (16 bits)

Syntax: DCX Rp
As Rp: Even register (B, D or H) or SP
Example:
LXI B,3000H
DCX B
Which gives (B)=(B)-1=3000H-1=2FFFH S=0 Z=0

9. ADC: Add register contents with carry: Add 8-bit register or memory case with
A and CY
Syntax: ADC R or ADC M
R : 8-bit register and M: address of a memory location

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Chapter V Microprocessor Systems
Example:
Move immediate value 30H into register A

MVI B, F0H
ADD B (A)=30H+F0H=20H and CY=1
ADC B (A)=20H+F0H+1=11H

10. ACI: Add immediate 8 bits data with carry: Add an 8-bit data with A and CY
Syntax: ACI given 8 bits

Example:
MOV A, 30H
MVI B, F0H
ADD B (A)=30H+F0H=20H and CY=1
ACI 30H (A)=20H+30H+1=51H

11. SBB: Subtract register contents with borrow: Subtract 8-bit register or memory location
and report CY of A.
Syntax: SBB R or SBB M
Let R: 8-bit Register and M: address of a memory cell
Example:
Move Immediate Value A,30H

Move immediate value B into register 20H

ADI FFH (A)=30H+FFH=2FH and CY=1

SBB B ; (A)=2FH-20-1=0EH

12. SBI: Subtract immediate 8 bits data with borrow: Subtract 8 bits data and carry borrow
from A.
Syntax: SBI given 8 bits
Example:
Move immediate value A, 30H

ADI FFH (A)=30H+FFH=2FH and CY=1

SBI 20H ; (A)=2FH-20-1=0EH

13. DAA: Decimal Adjust Accumulator: Decimal Adjustment of the Accumulator

Syntax: DAA

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Chapter V Microprocessor Systems
Example:
Move Immediate Value A, 38H

Move immediate value 43H to register B

ADD B ; A=7BH
DAA A= 81H

VII.3. Logical instructions

The microprocessor is a programmable logic circuit. The set of logical operators
is composed of: AND, OR, XOR and NOT. The result of the operation will be stored in
the accumulator A. These operators generate a zeroing of the CY flag. They modify the state
from S, Z, and P based on the result except for CMA. The AND operator is used for masking to 0
and the OR operator is used for masking to 1. The opcodes of these operators are:

1. ANA :And And logic between accumulator A and the contents of the register
or memory case.
Syntax: ANA R or ANA M
Let R: 8-bit Register and M: address of a memory location
Example:
Move immediate value 81H to accumulator A

MOVE B, 77H
ANA B
Which gives (A)=01H. S=0 Z=0 P=0

(B) = 0 1 1 1 0 1 1 1
(A) = 1 0 0 0 0 0 0 1

ANA B

(A) = 0 0 0 0 0 0 0 1

2. ANI: And Immediate And logic between the content of accumulator A and a value
8 bits.
Syntax: 8-bit data ANI
Example:
Load the immediate value 55H into register A

ANI 01H
This gives (A)=54H. S=0 Z=0 P=0

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Chapter V Microprocessor systems
3. NOW : Or Logical OR between accumulator A and the content of the register or
memory case.
Syntax: ORA R or ORA M
Let R: 8-bit register and M: address of a memory cell
Example:
Load immediate value 81H into register A

Move immediate value B, 7EH

ORA B
This gives (A)=FFH. S=1 Z=0 P=1

4. ORI: Or Immediate Logical OR between the content of accumulator A and a value of 8

bits.
Syntax: ORI 8-bit data
Example:
Load immediate value 55H into register A

ORI 02H
Which gives (A)=57H. S=0 Z=0 P=0

5. XRA :Xor Exclusive OR between accumulator A and the contents of the register or
a memory cell.
Syntax: XRA R or XRA M
Let R: 8-bit register and M: address of a memory cell
Example:
Move Immediate A, 80H

Move Immediate Value into Register B, 7EH

XRA B
Which gives (A)=FEH. S=1 Z=0 P=0

6. XRI: Immediate XOR Exclusive OR between the content of accumulator A and a value
8bits.
Syntax: 8-bit data XRI
Example:
Move Immediate Value to Register A, 55H

XRI 02H
This gives (A)=57H. S=0 Z=0 P=0

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Chapter V Microprocessor systems
7. CMA: Complement A Complement the accumulator A (invert all the bits of A).
Syntax: CMA
Example:
Load the hexadecimal value 55 into register A

CMA
(A)=0101 0101b, after executing CMA, we will have (A)=1010 1010b=AAH.
The CMA instruction does not affect any flag. The addressing mode is implicit.

VII.4. Logical rotation instructions

The logical instructions involved in this paragraph consist of bit rotations of
the accumulator A. These rotations take place either to the left or to the right, with or without
Carry. The rotation operations are RLC, RAL, RRC, and RAR. The result of the operation
will always be stored in accumulator A.

RLC : Rotate Accumulator Left : Left rotation of A.

Each bit is shifted to the left by one position. The D bit.7will become D0.
CY is modified according to the value of D7.

The left rotation of A results in multiplying the value of A by 2 provided that

the bit D7let it be at 0.

Example:
Before RLC (A)=AAH and CY=0
CY
0

D7D6D5D4D3D2D1D0
1 0 1 0 1 0 1 0

After RLC (A)=55H et Y=1

CY
1

D7D6D5D4D3D2D1D0
0 1 0 1 0 1 0 1

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Chapter V Microprocessor Systems
RAL: Rotate Accumulator Left Through Carry: Left rotation of A by CY.
Each bit is shifted to the left by one position. The bit D7will become CY and the CY is
shifted towards D0.

Example:
Before RAL (A)=AAH et CY=0
CY
0

D7D6D5D4D3D2D1D0
1 0 1 0 1 0 1 0

2. After RAL (A)=54H et Y=1

CY
1

D7D6D5D4D3D2 D1D0
0 1 0 1 0 1 0 0

3. RRC: Rotate Accumulator Right: Right rotation of A.

Each bit is shifted to the right by one position. The bit D0will become D7.
CY is modified according to the value of D0.

The right rotation of A results in dividing the value of A by 2 provided that bit D0
so be it at 0.

4. RAR : Rotate Accumulator Right Through Carry.

Each bit is shifted to the right by a single position. The bit D0will become CY and the CY is
shifted to D7.

VII.5. Comparison instructions

The 8085 has two types of comparison operations, namely: CMP and CPI.
CMP: Compare with Accumulator: Comparison with accumulator A.
CPI: Compare Immediate with Accumulator: Comparison in immediate with the accumulator
A.
The microprocessor compares a byte of data (or contents of register/memory) with the
content of accumulator A by subtracting the data from A and indicates whether the data is
supérieur ou égale ou inferieur ou égale au contenu de l'accumulateur. Cependant les deux
Operands will not be modified.

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Chapter V Microprocessor Systems

1. CMP R or CMP M
R: 8-bit register and M: Address of a memory cell specified by HL
It is a single-byte instruction.
Compare the contents of the register/memory with the contents of A.
If (A) (R/M), CY is set to 1 and Z is set to 0.
If (A) = (R/M), Z is set to 1 and CY is set to 0.
If (A) (R/M), CY and Z are set to 0.
No content is modified by the CMP instruction, only the flags are affected.
by the operation of subtraction.

2. CPI given 8 bits

It is a two-byte instruction.
Compare the second byte (8-bit data) with the content of A.
If (A) 8-bit data, CY is set to 1 and Z is set to 0.
If (A) = given 8 bits, Z is set to 1 and CY is set to 0.
If (A) 8-bit data, CY and Z are set to 0.
No content is modified by the CPI instruction, only the flags are affected.
the subtraction operation.

VII.6. Wiring Instructions

The branching instructions allow the microprocessor to change execution.
sequential of the program under certain conditions or without condition. The instructions of
connections are classified into three categories:
The jump instructions,
The CALL and RETURN instructions,
The restart instructions.

VII.6.1. Unconditional jump

The instruction set of the 8085 includes only one unconditional jump instruction. This one
allows the programmer to create loops.
Syntax: JMP 16-bit Address
It is a three-byte instruction.

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Chapter V Microprocessor Systems
Example of a loop:
Memory address Code machine Etiquette Mnemonic
2000 DB START: IN 00H
2001 00
2002 D3 OUT 01H
2003 01 JMP START
2004 C3
2005 00
2006 20

VII.6.2. Conditional jumps

Les instructions de saut conditionnel permettent au microprocesseur de faire une décision
under certain conditions indicated by the flags. After logical operations and
Arithmetic flags are set to 0 or 1. Unconditional branch instructions
check the flags to decide whether or not to interrupt the sequential execution of
program.
The four flags of the status register used by branch instructions are: CF, Z, S.
and P. Two branch instructions are associated with each flag. The sequence of
the program can be changed or not depending on the test condition. For example with (JC) the
Withholding from the bill exists and with (JNC) the withholding is absent. The instructions of
connections belong to the immediate addressing mode.
All branch instruction contains three bytes; the second byte specifies the byte
the low part of the address and the third octet represents the high part of the jump memory address.
We summarize the wiring instructions as follows:

Opcode Operand Description

JC 16 bits Jump if withholding (if the result generates withholding: CY=1)
JNC 16 bits Jump if no restraint (Y=0)
JZ 16 bits Jump if zero (if the result is zero: Z=1)
JNZ 16 bits Jump if not zero (if the result is different from 0: Z=0)
JP 16 bits Jump if bigger (if D7=0 and S=0)
JM 16 bits Jump if smaller (if D7=1 and S=1)
JPE 16 bits Jump if even (P=1)
JPO 16 bits Jump if odd (P=0)

Remark
There are two instructions for manipulating the CY flag, namely:
1. STC: set to 1 of CY
2. CMC: Supplement CY

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Chapter V Microprocessor systems
Example:
The following program displays the value of the accumulator A, which is the result of the sum.
between D and E if CY=0 else it displays 01H (CY=0). The program execution is the
next
Memory address Code machine Etiquette Mnemonic
2000 16 MVI D,9BH
2001 9B
2002 1E Move Immediate to Register A7H

2003 A7
2004 7A MOVE A,D
2005 83 ADD E
2006 D2 JNC DISPLAY
2007 0B
2008 20
2009 3E Move immediate value A into register 01H

200A 01
200B D3 DISPLAY: OUT 01H
200C 00
200D 76 HLT

VII.6.3. Loops in assembler

The previously illustrated programs can be solved manually. However, some
processing difficulties will occur in the case of repetitive tasks, such as
the addition of 100 numbers or transfer of thousands of bytes. Assembly programming
offers the programmer the ability to repeat sequences: this is called looping. A
loops allow the microprocessor to change the execution sequence and repeat tasks
once again. This is accomplished by using branch instructions. In addition
perhaps counters are added to define the number of repetitions. The loops are
classified into two groups: infinite loops and conditional loops.

VII.6.3.1. Infinite loops

This type of loop is used for infinite repetition. Its principle is illustrated by the figure
10.a. A program with an infinite loop only stops when the system receives a
RESET (See external architecture section of the 8085).

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Chapter V Microprocessor systems
VII.6.3.2. Conditional Loops
A conditional loop is: used for repetition with certain conditions. It is
made based on branching instructions. These instructions check the state of the flags
(Zero, Carry,...) and repeat the relevant tasks if the conditions are met. These loops
generally use the concept of counting (figure 10.b).

Start

Initialization
Start of the meter

Execution
of the task
Execution
of the stain
(a) (b) Decrementing of
counter

Return Counter at 0
and repetition

End

Figure V.10: Principle of loops

VII.7. Implementation of the stack

As mentioned in the previous chapter, the stack pointer (SP) points to the top
from the stack (memory zone).
A stack in a microprocessor system can be described as a set of boxes.
memory for reading and writing. This memory area is used to store the bytes
temporarily during the execution of a program.
The beginning of the stack is defined in the program by using the instruction LXI SP, which
loads the memory address of the stack into the stack pointer (SP) register. In general, SP
points to the top of the stack. For example, if SP is loaded with 2099H (LXI SP, 20099H), the
Data storage starts from 2098H and continues in the order 2097H, 2096H,...
The size of the stack depends on the amount of available memory.
The contents of even registers can be stored in the stack (two bytes at a time)
by using the PUSH instruction. To transfer data from the stack to the
POP registers are used. Two bytes are transferred to/from the stack, which implies that when
A PUSH SP decrements by 2 and a POP SP increments by 2.

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Chapter V Microprocessor systems
PUSH and POP instructions
Syntax: PUSH Rp and POP Rp
Rp: register pair B, D or H or PSW (Program Status Word) which is the set
Accumulator (A) and status register (F).
Example 1:
LXI B, 1234H
LXI SP, 2000H
PUSH B
POP B
Example 2:
The PUSH and POP instructions can be used to exchange the contents of registers.
pairs B and D. The schedule is as follows:
PUSH B
PUSH D
POP B
POP D
Figure V.11 shows how a value is stored on the stack and figure V.12 shows
how it is retrieved:

For the pair register B=1234H and SP=2000H

Before PUSH B After PUSH B

Memory Memory
1FFC ? 1FFC ?
1FFD ? 1FFD ?
1FFE ? SP 1FFE 34
1FFF ? 1FFF 12
SP 2000 ? 2000 ?

B C B C
12 34 12 34

Figure V.11: Execution of PUSH B

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Chapter V Microprocessor Systems

Set SP=2000H
Before POP B After POP B

Memory Memory
1FFF 10 1FFF 10
SP 2000 20 2000 20
2001 30 2001 30
2002 40 SP 2002 40

B C B C
? ? 30 20

Figure V.12: Execution of POP B

VII.8. Subprograms
A subprogram is a group of instructions written separately from the main program.
to perform a task that appears repetitively in the main program.
To avoid the repetition of the same blocks of instructions, a subprogram is written and called.
when the main program needs.
The call of the subprogram is made by the CALL instruction, the return to the program
the main is ensured by the instructionRET(return). CALL is used in the program
while RET is used at the end of the subprogram.
When a subprogram is called, the content of the CP is stored in the stack. The content
the CP represents in this case the address of the instruction that will follow CALL. As soon as the execution of

The 8085 retrieves the return address to the program from the stack.

1. Instruction CALL
Syntax: CALL 16-bit address of the subroutine
It is a 3-byte instruction.
Save the content of the PC to the stack
Decrement SP by 2
Perform an unconditional jump to the address of the subroutine

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Chapter V Microprocessor Systems
2. Instruction RET
Syntax :RET
It is a single byte instruction.
Retrieve the initial SP value of the stack (return address to the main program).
Increment SP by 2.
Unconditional return to the main program.
Example:

Memory address Code machine Comment

2000H LXI SP,2400H Initialize SP with 2400H

2040H CALL 2070H Call the subroutine located at 2070H

2041H
2042H
2043H Next instruction The address of the instruction that follows CALL

205FH HLT ; End of the main

2070H First instruction; Start of the subprogram
the subprogram

207FH RET End of subroutine

The course of this program takes place as follows:

2000H

2042H 2070H
2043H

205FH 207FH

VII.9. Conditional calls and return instructions

Conditional calls and return instructions are based on four conditions (flags):
CY, Z, S, and P. These conditions are tested by checking the flags. In the case of a call
conditional, the execution is transferred to the subroutine if the condition is met,
otherwise the program continues to execute. In the case of a return statement
conditional, the sequence returns to the main program if the condition is met,
otherwise the sequence of the subroutine continues. The conditional call and the return
Conditionals are summarized as follows:

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Chapter V Microprocessor systems
Conditional calls
CC Call subroutine if CY=1
CNC Call subroutine if CY=0
CZ Call subroutine if Z=1
CNZ Call subroutine if Z=0
CM Call subroutine if S=1
CP Call subroutine if S=0
CPE Call subroutine if P=1
CPO Call subroutine if P=0

2. Conditional Returns
RC Call subroutine if CY=1
RNC Call subroutine if CY=0
RZ Call subroutine if Z=1
RNZ Call subroutine if Z=0
RM Call subroutine if S=1
RP Call subprogram if S=0
RPE Call subroutine if P=1
RPO Call subroutine if P=0

VIII. Instruction Execution Cycle [16]

To illustrate the execution cycle of a two or three byte instruction, we consider by
for example, the instruction MVI A,32H. The opcode of this instruction is 3EH and the operand is
32H. This is a load instruction for the accumulator A with the value 32H. We can
calculate the time needed to execute this instruction from the retrieval of
the opcode and the operand and the complete memory read cycle if the system frequency is
2MHz.
This instruction consists of two bytes; the first is the opcode and the second is
the operand. The 8085 needs two machine cycles for memory read. This
The instruction requires seven clock cycles for these two memory accesses.
Pendant T1the microprocessor sends 011 for the IO/M signals and the status signals S1and
S0It transmits the memory address 2000H from the CP register on the address bus, 20H on A15-A8
and 00H on AD7-AD0and increment CP to 2001H to point to the next byte. The ALE signal
is in the high state for T1The latter memorizes the low weight of the AD bus.7-AD0at the exit
latches. During T2, the 8085 activates the RD signal. The opcode fetch cycle is
completed after T3During T4the 8085 decodes the opcode and identifies the type of instruction, in
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In this case, he needs to read the next byte. After T3the content of bus A15-A8is unknown and
the AD data bus7-AD0is set to high impedance.

M1(search for the opcode) M2(Lecture memory)

T1 T 2T 3 T4 T1 T2T3

CLK

A15-A8 20H: High byte memory address unspecified 20H: High byte memory address

Memory address Memory address

AD7-AD0 00H Opcode 3E 01H Data 32H

lightweight of low weight

ALE

States IO/M=0, S1=1, S0=1 : search opcode IO/M=0, S1=1, S0=0

RD

Figure V.13: Execution cycle of an instruction

The 8085 sends the address 2001H on the address bus and increments the PC register to point.
towards the next address 2002H. The second cycle machine M2is identified as a
memory lecture (IO/M=0, S1=1 et S0=0) and ALE is set to 1. The RD signal becomes active.
On the rising front of T2the memory puts the data 32H on the data bus and the 8085 reads and
store the byte in the accumulator for T3.
The machine cycle time for this example is calculated as follows:
Clock frequency: f=2 MHz
- One cycle = clock period (1/f) = 0.5 us
Opcode search time: (4.T) x 0.5 = 2 us
Memory read time: (3.T) x 0.5 = 1.5 us
Execution time of the instruction: (7.T) x 0.5 = 3.5 us

IX. Generation of deadlines [16]

A delay is achieved by loading a register with a value and decrementing it.
register by using a loop until the value 0 of the register. The delay is determined by
the system clock period and the time required for the execution of each
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instruction in the loop. Deadlines are used in various applications namely: management
from road traffic, series transfers,...

IX.1. Generation of a delay using an 8-bit register

An 8-bit register is used to support the number of loop repetitions. Therefore its
maximum is (FFH). This register will be decremented by the DCR instruction. The latter
affecte le flag Z. Un exemple de programme délai est donné comme suit :

Etiquette Opcode Operand Comments Name of

cycles
MVI C,FFH Charger C with an 8-bit counting 7
LOOP: DCR C Decrement (C) by 1 4
JNZ LOOP If result 0, back jump to LOOP October 7

If TL denotes the loop delay, T is the system clock period, N10 is

the equivalent of the decimal number of the counting register, we will have:
TL = T x Number of loop cycles x N10
If the clock frequency is 2MHz, then T=0.5us
TL = 0.5 x 10-6x 14 x 254 + 0.5 x 10-6x 1
TL = 1783us 1.8ms

IX.2. Generation of a delay using a pair register

A pair register is used to define the number of repetitions of the delay loop.
(maximum FFFFH). The register is decremented by using the DCX instruction.
However, the DCX instruction does not affect the Z flag. Additional instructions must
to be added. The following program handles this case:

Etiquette Opcode Operand Comments Name

of cycles
61 B,FFFFH Charger BC with a 16-bit counting
10
LOOP: DCX B Decrement (BC) by 1 6
MOV A,C Place the content of C into A 4
NOW B OR (B) with (C) to set the Z flag 4
JNZ LOOP If result 0, back jump at LOOP 10/7

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The delay time is calculated as follows: DCX, MOV, ORA, and JNZ require 24 cycles.
for execution. The loop is repeated FFFFH times, which is 65535 times in decimal.
If the system operates at a frequency of 2MHz, the period of a clock cycle is
0.5us, so the delay TL of the loop is:
TL=0.5 x 10-6x 24 x 65534 + 0.5 x 10-6x 21 786ms
The total delay TD=TL if we neglect the execution time of the instruction LXI.

IX.3. Generation of a delay using two loops

Two loops can be used (one inside the other). For example, register C is
used in the inner loop (LOOP1) and register B is used in the outer loop
(LOOP2). The following instructions are therefore used:
Move Immediate Value B, FFH 7T

LOOP2: MOVE C,FFH 7T

LOOP1: DCR C 4T
JNZ LOOP1 10/7T
DCR B 4T
JNZ LOOP2 10/7T
TL1=1783us
TL2=255 x (TL1+21 cycles x 0.5us) - (10-7) x 0.5us
TL2=457ms

X. Example of an assembler program for a square wave generator

We want to write an assembly program that generates a square wave signal of period
500us. It is assumed that the system clock period is 325ns. The output signal is
retrieved from bit D0of the accumulator A.

The pulse must appear for 250us (1 logic) and disappear for 250us (0)
logic). So we have to load the accumulator with the value AAH (1010 1010 in binary) and
must perform the rotation at each loop iteration. The delay of 250us can be achieved
easily with an 8-bit register. The ANI instruction is used for masking bits to 0.

Calculation of the COUNTING delay [16]

The total duration must include the duration of the DELAI loop (TL) and the execution time of
instructions outside the DELAY loop (T0).
The number of instructions outside the DELAY loop is seven; six instructions from
the ROTATION label and the JMP ROTATION instruction.
T0=46 cycles x 325 ns = 14.95us
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Chapter V Microprocessor systems
2. The DELAY loop duration includes two instructions (DCR and JNZ) with 14 cycles at
the exception of the last cycle which has 11 cycles.
TL = 14 cycles x 325ns x (COUNT-1) + 11 cycles x 325ns
TL = 4.5us x (COUNT - 1) + 3.575us
3. The total requested time TD is 250us. However, COUNTING can be calculated as
suit: TD=T0+TL
250us = 14.95us + 4.5us (COUNT-1) + 3.575us
COMPTAGE=52.410=34H

Address
Code HEX Etiquette Mnemonic Comments
memory
XX00 16 MVI D,AAH (7T) Load the AAH form
01 AA
02 7A ROTATION: MOVE A, D (4T) Load the form in A
03 07 RLC (4T) ;Change the AAH form to 55H and
vice versa
04 57 MOV D,A (4T) Save (A)
05 E6 ANI 01H (7T) Hide the D bits7at D1
06 01
07 D3 OUT PORT1 (10T) Output to 1 or 0
08 PORT1
09 06 MVI B, COUNTING (7T) Load the delay for 250us
0A COUNTING
0B 05 DEADLINE: DCR B (4T) Next counting
0C C2 JNZ DELAY (10/7T) ;Repeat until (B)=0
0D 0B
0E XX
0F C3 JMP ROTATION (10T) Return to change the level
10 02 logic
11 XX

XI. Serial transmission lines of the 8085 microprocessor SOD and SID [16]
The 8085 has two pins for programmable serial transmission: SOD (Serial
Output Data) and SID (Serial Input Data). The transfer is controlled by the SIM instructions and
RIM. These instructions are used in the interrupt process or serial transfer.

XI.1. SOD Transmission Line

This line is interpreted for serial transmission as follows:

D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE X Pourless interruptions
SDE=0 : SOD disabled
SDE=1: SOD activated

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Chapter V Microprocessor Systems

Instructions:
MVI A,80H ; Set D to 17in the accumulator
RAR ; D6=1 and put CY in D7
YES Exit D7by the SOD line
In this sequence of instructions, serial transmission is active and the SIM instruction sends the
bit CY by position D7.

Example:
In this example, a subroutine SODATA must transmit a character, stored in the
Register B, in series on the SOD line. A counter is set to 11 bits: Start Bit + Data
on 8 bits + 2 bits Stop. The duration of a transmitted bit is about 9.1ms.

SODATA: The
Move Immediate Value to Register content
C, 0BH of C is 11
XRA A Reset of CY
NEXTBIT: LOAD A,80H ; D7from the accumulator to 1
RAR Place CY in D7and set to 1 of D6
YES Exit D7
CALL BITTIME Waiting for 9.1 ms
STC ; CY=1
MOVE A, B Place the character code in A
RAR Place D0of the character in CY, shift of 1 in D7
; and continue the offset for each loop iteration
Move B, A store A in B
DCR C When a bit is transmitted, decrement the counter
JNZ NEXTBIT If not all the bits are transmitted, return
RET

XI.2. SID reception line

The RIM instruction is used for receiving serial data. This instruction is
interpreted by the following:

D7 D6 D5 D4 D3 D2 D1 D0
SID P o u r l e s interruptions

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Note:
The RIM instruction is similar to the IN instruction, except that RIM reads a single bit and the
place in the accumulator at D7Also SIM is equivalent to OUT, but SIM sends only one
bit. The SID and SOD lines of the 8085 eliminate the need for an input/output port.
To receive a character, a procedure involves saving the bits coming from the
line SID.
After reading the first bit D0this bit is stored in CY with the RAL instruction. The bit is
stored and shifted to the right using RAR. This procedure is repeated eight times. At the
ninth iteration, the subprogram returns to the main program while ignoring the two
bits Stop.

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CHAPTER VI
INPUT OUTPUT INTERFACES

I. Generalities [5,6]
Input-output refers to the exchange of information between the processor and the
devices associated with it. In this way, the system can respond to changes in
its environment, or even control it. They are sometimes referred to by the acronym I/O, derived from
Input/Output or I/O for Inputs/Outputs.
Inputs are the data sent by a device (disk, network, keyboard...) to
destination of the central unit;
The data issued by the central unit are less sorted. à destination
of a device (disk, network, screen...).
Exemple :
typing on the keyboard sends a series of codes to the processor; these codes are
considered as input data;
the microprocessor displays the results of data processing on a screen; these are
Output data. Typically, the screen is managed by a display management program.
The objectives of this chapter are: Listing the elements of the 8255A 'Programmable
Peripheral Interface (PPI) and explanation of these modes of operation. Also, this chapter
donne une description détaillé de l'interface série (8250) et du Timer (8254) et leurs
different configurations.

II. Microprocessor and interface circuits [5,6]

Input/output interfaces are connected to the microprocessor through address buses.
of data and commands as shown in figure VI.1. The access points to
interfaces are called ports.
The 8085 has a memory space of 64 KB (address of a memory cell on 16 bits) and
of an I/O space of 256 bytes.
The signal that differentiates memory addressing from I/O port addressing
is the IO/M line:
• Pour un accès à la mémoire, IO/M = 0 ;
For access to I/O ports, IO/M = 1.
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External environment Peripheral 1 Peripheral 2

Port 1 Port 2
Calculator

Microprocessor Interface 1 Interface 2 ...

Data

Addresses

Orders

Figure VI.1: Microprocessor and interface circuits

III. Different types of interfaces [16]

There are several types of input/output interfaces in the INTEL family, namely: the interface
programmable peripheral 8255A, serial interface 8250, interrupt controller 8259A,
the Timer 8254 and the DMA 8237.

III.1. Programmable Peripheral Interface 8255A

Peripheral Interface: PPI
The role of a 8255A interface is to transfer data from the microprocessor to
devices and vice versa, all bits of data being sent or received simultaneously.
The 8255A is a programmable parallel interface: it can be configured for input and/or for
departure by program. It is a flexible and economical circuit (in case of need for several
The 8255A has three ports, which are used for bidirectional transfer of
data.

III.1.1. Wiring of the 8255A

The 8255A contains 24 input/output pins grouped into three 8-bit ports A, B, and C.
The eight bits of port C can be used individually or grouped into two subgroups.
from 4 bits: CSkinand CEnoughThe operation of these registers is identified by the bits of the register
of control.
A data register connects the external data bus and the register.
control as well as the input/output ports.
The command logic consists of six lines:

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Chapter VI Microprocessor Systems
RD: This signal allows for a read operation. When this signal is 0, the
microprocessor reads the data from the selected port of the 8255A.
WR: This signal allows for a write operation. When this signal is at 0, the
microprocessor writes the data to the selected port of the 8255A.
Reset: This is a high active signal, it allows to clear the register.
control and set the ports to input mode.
CS, A0A0These are the selection signals. Low state CS selects the circuit.
8255A and A0, A0specify the selected port or the control register as the
show the following table:
CS A1 A0 Register
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control Register
1 X X 8255A unselected

Table VI.1: Port Addressing and Control Register

Example:
For example, the addresses of the ports in the figure are calculated from the CS, A lines.0and
A1The CS line is high when A7=1 and A6up to A2are at a low state. When these
signals will be combined with A0and A1the port addresses will be between 80H and 83H.

A7
8255 Addresses
A6 A=80H CS Port
CS in Hexa
A7A6A5A4A3A2A1A0
A5
A1 A1 C=82H 1 0 0 0 0 0 0 0 80H A
A4 A0 A0 0 1 = 81H B
IOR RD 1 0 = 82H C
A3 B=81H
In Other Words
WR 1 1 = 83H Register of

A2 Reset control

Figure VI.2: Example of addressing the 8255A

The previous figure shows a register called control register. The contents of this
register is called a control word that specifies the input-output function of each port. This
the registry is not accessible for a read operation.

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RD
Group WR
A
Group Port I/O
A PA7-PA0
A
Control Port
PA3
(8) A
1 PA4
PA2 2 PA5 00 EN
PA1 3 PA6
PA0 4 PA7 Group
RD
RD 5 WR A
I/O WR WR
CS 6 RESET
Port C PC7-PC4
Data bus
GND D0 bidirectional Skin
7
A1
Are you buffering? (4)
8 D1
D7-D0 bus of Port
A0 9 D2
data
PC7 10 8255A D3 Data bus Group C
PC6 11 D4 8-bit internet B 10 EN
I/O
PC5 12 D5 Port C
PC3-PC0
PC4 13 D6 Base CS RD
PC0 14 D7 (4) WR
PC1 15 VCC Logic 11
PC2 16 PB7 of 10
RD A1
PC3 17 PB6 control Group Group 01
C Port B
WR A0 B
PB0 18 PB5 A1 B B 00
I/O A
PB1 19 PB4
Lecture Control Port
A0 PB7-PB0 01 EN
PB2 20 PB3
writing B
Reset
(8)

CS

Figure VI.3: Internal and external structure of the 8255A

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III.1.2. Programming the 8255A
The 8255A can be programmed in three modes:
Mode 0: Basic input/output.
Mode 1: Sampled input/output.
Mode 2: Bidirectional bus.
The format as well as the choice of modes is determined by the following control word:

Control word
D7D6D5D4D3D2D1D0
Group B

Port C (Bas_PC3-PC0)
1 = Entrée
0 = Exit
Port B
1 = Entrée
0 = Sortie
Selection of mode
0 = Mode 0
1 = Mode 1

Group A
Port C (High_PC7-PC4)
1 = Entrée
0 = Exit
Port A
1 = Entrée
0 = Output
Selection of mode
00 = Mode 0
01 = Mode 1
1X = Mode 2

1 = Input/Output Mode
0 = Mode BSR

Figure VI.4: Control word format of the 8255A for input/output mode

The bit D7The control register specifies both the I/O function or Bit Set/Reset. If the bit
D7=1, the bits D6-D0 determine the I/O functions with different modes. If the bit D7=0, the
Register C operates in Bit Set/Reset mode.
To communicate with the devices through the 8255A, three steps must be considered:

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1. Determination of the addresses of ports A, B, C and the contents of the control register while taking into account

circuit selection count and address lines.

2. Write the control word in the control register
3. Write the input/output instructions to communicate with the peripherals through the
port A, B, and C.

Mode BSR
This mode only concerns the eight bits of port C, which can be set to 1 or 0 by
control register configuration. A control word with bit D7=0 describes the mode
BSR. The I/O operations of ports A and B are not affected by the BSR mode. For the
set to 1 or 0 in port C, a control word is written in the control register and not
not in port C. The control word is specified by the following:

D7 D6 D5 D4 D3 D2 D1 D0
0 X X X Bit selection S/R
Set=1
Mode
Reset=0
BSR Unused
0 0 0 Bit 0
0 0 1 Bit 1
0 1 0 Bit 2
0 1 1 Bit 3
1 0 0 Bit 4
1 0 1 Bit 5
1 1 0 Bit 6
1 1 1 Bit 7
Table VI.2: Control Register
Example:
Write a subroutine in BSR mode to set the PC bits to 1.7and PC3and then their
reset after 10ms. It is assumed that the 10ms delay is available.
For setting bit PC to 17The control word = 0 0 0 0 1 1 1 1 = 0FH
To reset the PC bit7, the control word = 0 0 0 0 1 1 1 0 = 0EH
For setting the PC bit to 13, the control word = 0 0 0 0 0 1 1 1 = 07H
To reset the PC bit3the control word = 0 0 0 0 0 1 1 0 = 06H
The address of the control register = 83 H (figure VI.2)
Under program:
BSR: MOV A,0FH Load the byte 0FH into the accumulator
OUT 83H ; PC7=1
Load
Load immediate value A with 07H the byte 07H into the accumulator
OUT 83H ; PC3=1
CALL DELAY Delay of 10ms
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MOV A, 06H Load the byte 06H into the accumulator
OUT 83H PC3=0
MOV A, 0EH Load byte 0EH into the accumulator
OUT 83H PC7=0
RET

Mode 0: Simple entry or exit

In this mode, ports A and B are used as two simple 8-bit input/output ports.
bits and port C as two four-bit ports. Each port (or half port in the case of
C) can be programmed for input or output. The characteristics of input and output are
as follows:
The outputs are recorded,
2. The entries are not saved,
3. Ports do not take into account handshakes and interruptions.

Example:
1. Identify the addresses of the port in the following figure:

PA7

PA0

PC7 +5V

8255A
PC4

PC3

A15 CS PC0
Switches
A1 A1 PB7
A0 A0

MEMR RD
MEMW WR PB0
RESET OUT RESET

+5V

Figure VI.5: Example of the application of the 8255A in mode 0 for input and output

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2. Identify the control word of mode 0 to configure port A and port CSkinas
exit ports and port B and port CEnoughas entry points.
3. Write the program to read the states of the switches and display the reading of port B.
port A and reading from port CSkinat port CEnough.

Solution :
1. Port addresses and control register:
Port A : 8000H (A1=0 and A0=0)
Port B: 8001H (A1=0 and A0=1)
Port C : 8002H (A1=1 and A0=0)
Control register: 8003H (A1=1 and A0=1)
2. Control word:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 1 1 =83H
3. Program:
MVI A,83H ; Load the accumulator with the control word
STA 8003H; Write the word into the control register to initialize the ports
LDA 8001H ; Read the switches of port B
STA 8000H ; Display the reading on port A
LDA 8002H ; Read the switches of port C
ANI 0FH; Mask the four most significant bits of port C; These bits are not inputs
RLC; Rotate and place the data in the most significant bit of the accumulator
RLC
RLC
RLC
STA 8002H ; Display the reading on port C of the high weight
HLT

Mode 1: Input or output with Handshake

The characteristics of this mode are:
1. Two ports A and B can be configured as inputs or outputs.
Each port uses three lines from port C as Handshake signals. The two lines
The remaining ports C can be used as simple inputs or outputs.
3. The input or output data is stored.
4. An interruption logic can be used.

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Chapter VI Microprocessor systems
Mode 1: input
At the input, ports A and B are configured as input while PC.2, PC1and PC0ensuring the
handshake for B and PC3, PC4and PC5for A (PC6and PC7can be programmed in input
or out.
STB : (Strobe input) : Généré par un périphérique (actif niveau bas), indique qu'il a transmis
a data byte. The 8255A responds to STB and generates IBF and INTR. STBAand connected to the
PC pin4and STBBand connected to the PC pin2.
IBF: (Input Buffer Full): This signal is a response from the 8255A, indicating that the
The input latch has received the data. This signal will be reset when the microprocessor reads the
data.
INTR (Interrupt Request): It is an output signal that can be used to interrupt the
microprocessor. This signal is generated if STB, IBF, and INTE (Internal flip-flop) are all set to 1.
These signals will be reset to 1 on the rising edge of the RD signal emitted by the microprocessor.

INTE (Interrupt Enable): It is an internal flip-flop used to enable or disable the

generation of INTR. INTEAand NOTBare commanded by the control word of port C
(PC4for Port A and PC2for the Port B). The status word can be read in the accumulator if the
port C is read by the microprocessor.
The incoming handshake is summarized by the following figure:
8255A
PA7
Port A in input
INTEA
PA0 Control word - Mode 1 input
D7D6D5D4D3D2D1D0
PC4 STBA Port A with
1 0 1 1 1/0 1 1 X
signals
PC5 IBFA Handshake

Mode E/S Port B as input

Port A in mode 1 Port B in mode 1
PC3 INTRA
Port A in input PC6.7
INTEB 1 = Entrée
0 = Exit

PC2 STBB

PC1 IBFB Port B with

signals
Handshake
State word - Mode 1 input
PC0 INTRB D7 D6 D5 D4 D3 D2 D1 D0
PB7
I/O I/O IBFA INTEA INTROA NOTB IBFB INTROB
RD Port B as input
PB0

PC6,7 I/O
Figure VI.6: 8255A in mode 1 in input

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Chapter VI Microprocessor Systems
Mode 1: output
Figure VI.7 shows the control signals when ports A and B are configured as
exit ports. These signals are defined as follows:
OBF (Output Buffer Full): It is an output signal. Set to low when the
The microprocessor writes the data into the output latch of the 8255A. This signal indicates to
an output device that new data is ready for reading. It will
returned to high state after receiving ACK by the 8255A from a
device.
ACK (Acknowledge): It is an input signal coming from a device that must
send a 0 when it receives data from the 8255A ports.
INTR (Interrupt Request): It is an output signal. It is set to 1 by a rising edge.
of the ACK signal. This signal can be used to interrupt the microprocessor for
request the next data. The INTR signal is set to 1 when OBF, ACK, and INTE
are all at 1. INTR is reset to 0 at the falling edge of WR.
INTE (Interrupt Enable): It is an internal flip-flop of the port, it needs to be at 1.
to generate the INTR signal. INTEAand NOTB are controlled by the PC bits6and PC2
respectively through the BSR mode.
PC4.5These two lines can be configured as input or output.
8255A
PA7 Control word - Mode 1 in input
INTEA Port A output D7D6D5D4D3D2D1D0
PA0
1 0 1 0 1/0 1 0 X

PC7 OBFA

PC6 ACKA E/S Mode Port B output

Port A in mode 1 Port B in mode 1

Port A output PC6.7

PC3 INTRA 1 = Entrée
0 = Output
NOTB

PC1 OBFB

PC2 ACKB

State word - Mode 1 in output

PC0 INTRB D7 D6 D5 D4 D3 D2 D1 D0
PB7
OBFA INTEA 1/0 1/0 INTRA NOTB OBFB INTRB
WR Port B as output
PB0

PC4.5 I/O

Figure VI.7: 8255A in mode 1 in output

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Chapter VI Microprocessor Systems

III.1.3. Example of application of the 8255A

Figure VI.8 shows an interfacing circuit using an 8255A in mode 1. Port A is
designated as input for a keyboard with interruption and port B is designated as output for
to be used by the printer.
1. Find the addresses by analyzing the logic circuit.
2. Determine the control word to configure port A as input and port B as output.
mode 1.
3. Determine the BSR word to activate INTEA(port A).
4. Determine the masking byte to check the OBF lineBin input or output (port B).
Write the initialization instructions and the printer subroutine to send the
characters stored in memory.

PA7
D7 Port A in input: Connected with the keyboard
Bus of
data PA0
D0
8255A
PC4 STB of a peripheral
A7
A6
IBF
A5 PC5 towards a device
A4 CS
INTRA
A3 PC3 Interruption of the 8085 (RST 6.5)
A2
OBFB Printer
PC1
A1 A1 ACKB from the printer
A0 A0 PC2

MEMR RD PB7
MEMW WR
RESET OUT Port B output: Connected to the printer
RESET
PB0

Figure VI.8: Example of application of the 8255A in mode 1 for input and output

Solution :
1. Port addresses and control register:
Port A : FCH (A1=0 and A0=0)
Port B : FDH (A1=0 and A0=1)
Port C : FEH (A1=1 and A0=0)
Control Register: FFH (A1=1 and A0=1)
2. Control word configured for port A as input and port B as output in mode 1

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D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 0 1 0 0 =B4H
Operation in Port A in mode 1 Port A PC4.5 Port B Port B Bit D0
I/O in Little in mode in Few
entry import 1 exit import
Table VI.3: Control Register

To generate the interrupt signal INTRA, the INTE scaleAmust be set to 1, which can
to be carried out by using BSR mode to set 1 PC4.
The printer output (port B) has a controlled state. However, the state of the OBF lineBcan
to be verified by reading bit D1from port CEnough.
3. To BSR to set to 1 INTEA. For setting to 1 for activating the port interrupt
A (INTEA), the PC bit4must be set to 1.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 0 0 1 =09H
Bit D0
Mode BSR It doesn't matter Bit PC4.5
set to 1
4. State word to check OBFB
D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X OBFB X
You must mask the byte with 02H.
5. Program initialization
Move Immediate A, B4H Port A as input and Port B as output in mode 1.
OUT FFH
Move Immediate Value A, 09H Set to 1 of INTEA(PC4)
OUT FFH by using BSR mode
EI Accept interruptions
CALL PRINT switch to another task

Print subsystem
PRINT: LXI H,MEM ; Pointer to the beginning of the character area
Move Immediate Value to Register B, Count Number of characters to print
NEXT: MOV A,M ; Read the character
MOVE C, A Save character
STATUS: IN FEH Read port C for the OBF state
ANI 02H Mask all bits except D1
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Chapter VI Microprocessor Systems
JZ STATUS If low state, the printer is not ready: waiting by a
MOVE A, C ; loop
OUT FDH Send a character to port B
INX H Pointer to the next character
DCR B
JNZ NEXT
RET

Mode 2: Bidirectional data transfer

This mode is primarily used in applications such as the transfer between two
microcomputers or removable disk interface controller. In this mode, port A
can be configured in bidirectional mode and port B in mode 0 or mode 1. Port A
use five signals from port C as handshake signals for data transfer. The
three remaining signals from port C can be used as simple I/O or as a
handshake for port B. Figure VI.9 illustrates this mode.

Mode 2 and mode 0 in input Mode 2 and mode 1 as input

PA7
PA7PA0 8
8 8255A
INTRA
PA0 PC3
OBFA
8255A PC7
PC7 OBFA CS ACKA
PC6
ACKA
PC6 STBA
CS PC4
STBA
PC4 IBFA
PC5
IBFA
PC5
I/O RD PB7-PB1 8
PC2-0 WR
OBFB
PC1
RD PB7 ACKB
WR PC2
8
INTRB
PB1 PC0

Control word Control word

D7D6D5D4D3D2D1D0 D7D6D5D4D3D2D1D0
1 1 X X X 0 1 1/0 1 1 X X X 0 1 X

PC2-0
1 = Entrée
0 = Output
Figure VI.9: 8255A in mode 2

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Chapter VI Microprocessor Systems
III.2. Serial interface [18]
A serial interface (Figure VI.10) allows data exchange between the microprocessor and
a bit-by-bit device.

External environment Peripheral

TxD Port RxD
Calculator Transmission Reception

Microprocessor Serial interface

Data

Addresses

Orders

Figure VI.10: Data exchange with a bit-by-bit device (serial)

Advantage: reduction in the number of connections (1 wire for transmission, 1 wire for the

reception).
Disadvantage: lower transmission speed than for a parallel interface.
There are two types of serial transmissions:
•Asynchronous: each byte can be sent or received without a predetermined duration between one byte and the next.

following;
Synchronous: the successive bytes are transmitted in blocks separated by bytes of
synchronization.
The most widely used asynchronous transmission is that defined by the RS232 standard.
Example
Transmission of the character 'E' (ASCII code 45H = 01000101B) in serial form according to the

RS232 standard:

Bit of Bits of Bit of Bits of

START DATA PARITE STOP

9 to +15V
LSB MSB
-9 to -15V
1 0 1 0 0 0 1

Duration of a bit

Figure VI.11: Format of a character for asynchronous serial transmission

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Chapter VI Microprocessor systems
State 1 corresponds to a negative voltage between -9 and -15 V, state 0 to a voltage
positive is between +9 and +15 V. At rest, the line is in state 1 (negative voltage);
The start bit marks the beginning of the character transmission;
Data bits are transmitted one after the other starting with the most significant bit.
low. They can be numbered 5, 6, 7, or 8. Each bit is held on the line for
a fixed duration T. The inverse of this duration defines the bit rate = number of bits
per second = transmission speed. The standardized speeds are: 50, 75, 110, 134.5,
150, 300, 600, 1200, 2400, 4800, 9600 bits/s;
• Le bit deParité(facultatif) est un bit supplémentaire dont la valeur dépend du nombre de
data bits equal to 1. It is used for transmission error detection;
The Stop bits (1, 1.5 or 2) mark the end of the character transmission.

III.2.1. Principle of a serial interface

An integrated circuit for asynchronous serial interface is called a UART: Universal Asynchronous

Receiver Transmitter) ; a synchronous/asynchronous serial interface is a USART.

Data record Shift register TxD

broadcast emission
D7-D0

Data register Offset register

RxD
reception reception

Bus of Register of Logic of Signals of

data configuration and status synchronization control
internal Parity check

Clock

Figure VI.12: Principle of a serial interface

III.2.2. Connection of two devices via an RS232 serial link

The equipment that can be connected through an RS232 serial connection is two
types :
Data Terminal Equipment (DTE) that generate the
data to transmit, example: a computer;
Data Communication Equipment (DCE)
which transmit data over communication lines, for example: a modem.
Different signals are carried by the connectors of the RS232 port. The table provides a
description of these signals.
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DB9 DB25 Sense
Signal Description
Number of pins No. brooch DTE DCE
TxD 3 2 Transmit Data Exit Entry
RxD 2 3 Receive Data Entry Exit
RTS 7 4 Request To Send Exit Entry
CTS 8 5 Clear To Send Entry Exit
DTR 4 20 Data Terminal Ready Output Entry
DSR 6 6 Data Set Ready Entry Exit
DCD 1 8 Data Carrier Detect Entrance Exit
RI 9 22 Ring Indicator Entrance Exit
GND 5 7 Ground - -
Table VI.4: RS232 serial port lines

Only the two signals TxD and RxD are used to transmit data. The other signals are
control signals for data exchange.
When the DTE equipment wants to transmit data, it activates the DTR signal. If the DCE
is ready to receive the data, it activates the DSR signal and then the DCD signal: communication
can begin,
When the DTE equipment has data to transmit, it activates the RTS signal. If the DCE can
receive the data, it activates CTS: the DTE sends the data on the TxD line,
If the DCE equipment wants to request a pause in transmission, it disables CTS:
DTE stops transmission until CTS is reactivated. It is a hardware control of
data flow;
When the transmission is complete, the RTS, CTS, DTR, DCD, and DSR signals are
successively disabled.

III.2.3. Implementation of a serial interface, the UART 8250

D0 VCC
D1 RI
D2 DCD
D3 DSR
D4 CTS
D5 MR
D6 OUT1
D7 DTR
RCLK RTS
SIN 8250 OUT2
SOUT INTRPT
CS0 NC
CS1 A0
CS2 A1
BAUDOUT A2
Crystal1 ADS
XTAL32 CSOUT
DOSTR DDIS
DOSTR DISTR
GND DISTR

Figure VI.13: Pinout of the UART 8250

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The 8250 has 11 registers. Since there are only 3 address bits (A0, A1and A2), several
registers must share the same address:

DLAB A2 A1 A0 Register
0 0 0 0 RBR: Receiver Buffer Register, reception register (accessible only in
lecture)
0 0 0 0 THR: Transmitter Holding Register, transmission register (accessible only in
writing
1 0 0 0 DLL: Divisor Latch LSB, the least significant byte of the clock divisor
1 0 0 1 DLM: Divisor Latch MSB, most significant byte of the clock divider
0 0 0 1 IER: Interrupt Enable Register, interrupt authorization register
X 0 1 0 IIR : Interrupt Identification Register, registre d’identification des interruptions
X 0 1 1 LCR : Line Control Register, registre de contrôle de ligne
X 1 0 0 MCR: Modem Control Register, modem control register
X 1 0 1 LSR: Line Status Register, line status register
X 1 1 0 MSR: Modem Status Register, modem status register
X 1 1 1 SCR: Scratch Register, general-purpose register

Table VI.5: Selection of registers of the 8250

Depending on the status of DLAB (Divisor Latch Access Bit = most significant bit of the LCR register),
we have access either to the transmission/reception register, or to the clock divider, or to the mask
interruptions.

Line Control Register (LCR)

Bits 0 and 1: length of the transmitted word, bit 1 bit 0
0 0 5 bits
0 1 6 bits
1 0 7 bits
1 1 → 8 bits
Bit 2: number of stop bits, 0 → 1 stop bit,
1 → 1.5 stop bits if 5 bits, 2 stop bits otherwise;
bit 3: parity authorization, 0 → no parity,
1 → generated and verified parity;
bit 4: parity selection, 0 → odd parity,
1 → even parity;
bit 5 : /
bit 6 : /
bit 7: DLAB (Divisor Latch Access bit)
0 → access to emission, reception, and IER registers,
1 → access to the clock divider.

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Line Status Register (LSR)
bit 0 : 1 → donnée reçue ;
bit 1: 1 → character overwrite error;
bit 2 : 1 → parity error ;
bit 3 : 1 → framing error (invalid stop bit);
bit 4: 1 → detection of a logical state 0 on RxD for a duration greater than the duration
in a word ;
bit 5: 1 → empty transmission register;
bit 6: 1 → empty shift register;
bit 7: unused, always 0.

Clock divider (DLM, DLL)

The transmission speed is determined by the value of the clock divider:

speed(bits/s) clock frequency

16x(DLM,DLL)
Calculation example:
Desired transmission speed = 1200 bit/s, clock frequency = 1.8432 MHz.
Determination of the clock divider value:

divisor clock frequency 1.8432x106

96 DLM 0et DLL 96
16xspeed 16x1200

III.2.4. USB Ports (Universal Serial Bus)

The new USB serial connection bus, promoted by major manufacturers
computing and software publishers (Compaq, DEC, IBM, Intel, Microsoft, NEC, Nortel) and
where the first specifications must allow connection to a single socket of
several various equipment (printer, telephone, modem, fax, keyboard, mouse, scanners,
screens...). This aims to avoid the current multiplication of connectors on PCs. This bus
allows for the transmission of data in series. This new technique must be fast,
bidirectional, synchronous, low cost and the attachment of a new device must be
dynamic. Moreover, the power supply for the equipment is possible.
The gross throughput (transmission plus reception) can reach up to 12 Mbit/s at maximum. The throughput

brut must be shared among all devices connected to the bus.

The USB port has 4 pins namely: a power pair (VCC and GND) and a pair
twisted of inverted data (-DATA and +DATA). At rest +DATA and -DATA are in the state
up and down respectively.

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III.3. Timer, Intel 8254
The Timer 8254 is an input/output controller. It couples with a clock to
provide the machine with a time measurement mechanism.
The diagram in Figure IV.14 provides a minimal representation of the connection by limiting itself
to the data bus and signals for selecting the controller registers.
The bits A0and A1allow access to one of the four internal registers: one register per
counter (Counter 0 : A1=0 and A0=0, Counter 1: A1=0 and A0=1, Counter 2: A1=1 and
A0=0) and order register (A1=1 and A0The CS is the result of decoding addresses.
of the other bits of the address bus.

CLK 0

D7D0 GATE 0

RgC 0 OUT 0

RD
CLK 1
WR
A1 GATE 1
A0 RgC 1 OUT 1
CS

CLK 2

GATE 2

CWRg RgC 2 OUT 2

8254

Figure VI.14: Internal block diagram of the 8254

The circuit consists of three identical functional units, called counters, focused on the
time counting.
A counter has two hardware inputs (CLK), Gate, and a software input, the
RgC counter. The CLK input receives pulses that can be periodic or not.
GATE is a hardware input for validating the count. The 16-bit register RgC is
programmable and can be pre-set to a certain value. Each
Pulse on the CLK input decrements the counter. The OUT output is initially 0.
to 1 when RgC goes to the value 0. From the initialization of the counter register, the 8254

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propose 6 modes of operation. This is the programming of the CWRg register (Control
Word Register) which allows configuring the operating mode of a functional unit
with the values of bits M2 to M0. SC1 and SC0 serve to define in a command word
the counting unit (Counter Selection 0: SC1=0 and SC0=0, Counter 1: SC1=0 and
SC0=1, Counter 2: SC1=1 and SC0=0) subject to configuration by the word
command. The bits RW0 and RW1 define the data transfer word. The BCD bit
allows for a BCD counting.

D7 D6 D5 D4 D3D2D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
0 Binary counting
1 BCD Counting
0 0 0 Mode 0
0 0 1 Mode 1
X 1 0 Mode 2
X 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5
0 0 Latch counter command
0 1 Read/Write Least Significant Bit 8 bits

1 0 R/W MSB 8 bits

1 1 R/W LSB then MSB
0 0 Selection of Counter 0
0 1 Selection of Counter 1
1 0 : Sélection du Compteur 2
1 1 Reading order

Table IV.6: Control word CWRg of the 8254

Example of mode 0
This mode is suitable for event counting. After programming the counting unit.
through the command register and initialized the counter. When GATE goes to 1. The
the counter is then decremented with each event signaled by a pulse on the input
CLK. The output OUT changes from its initial value 0 to the value 1 when the counting reaches 0.
OUT then remains at the high level until a new value is loaded into the register.
counter. The OUT output can serve as an interrupt signal.

Example:
1. Identify the addresses of the ports and the control register and the counter 2 of figure IV.15
2. Write a subroutine to initialize mode 0 for a count of 50,000.
3. Write the main program to display the seconds by calling the subprogram
several times.

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Solution:
1. Port addresses: CS is active if A7=1 and the control register is selected by A1=1
and A0The counter 2 is selected when A1=1 and A0Suppose that the lines
unused addresses A6to A2are at 0. We will have the following:
Control register = 83H
Counter 2 = 82H
18 Clock 2 MHz
1 CLK 2
D7
Bus of 16 +5 V
data 8 GATE 2
D0
17
OUT 2
8254
15
21 CLK 1
A7 CS
14
GATE 1
13
20 OUT 1
A1
19
A1
9
A0 A0 CLK 0
22 11
IOR RD GATE 0
23
IOW WR
10
OUT 0

Figure VI.15: Example of selection of the 8254

2. Subroutine: to initialize the 8254, a loading operation with the value B0H
is given as follows:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 0 0 0 0

Control word for memorizing the count: the D bits5 and D4must be at 0. In this case
the content of the control word is 80H.

COUNTER: MVI A, B0H Initialize counter 2

OUT 83H Write in the control register
MVI A, OCTETB the low weight byte of counting 50000
OUT 82H Load counter 2 with the least significant byte
MOV A, OCTET the high-order byte of counting 50000
OUT 82H Load counter 2 with the high byte
LOAD A,80H Control word to memorize the counting
OUT 83H Write in the control register
IN 82H Reading the least significant byte

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Chapter VI Microprocessor Systems
MOVE D, A Store the least significant byte in D
IN 82H Reading the most significant byte
ORA D OR the low and high weight bytes to set Z to 1
JNZ LECTURE If counting 0 go to the next count
RET

3. Main program: The COUNTER sub-program offers a delay of 25 ms (50000 x

0.5 us Clock); If this routine is called 40 times, the total delay will be one second.
LXI SP,STACK Initialize SP
Move immediate data B, 00H Erase B to load the number in seconds
SECOND: MVI C,28H It is loaded by 28H=4010
WAIT: CALL COUNTER: Waiting for 25 ms
DCR C
JNZ WAIT Is it a second? Otherwise, go back and wait.
MOVE A, B
ADI 01H Add a second
DAA
OUT PORT1
MOV B,A Memorizing the seconds
JMP SECOND Return and start again for the next second

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Chapter VII Microprocessor Systems

CHAPTER VII
THE INTERRUPTIONS

I. Definition of an interruption [9]

Consider a microprocessor that needs to exchange information with a peripheral: There are two
possible methods to receive data from devices:
1-Periodic polling: the main program contains instructions that
they cyclically read the state of the I/O ports.

Advantage: ease of programming.

Disadvantages: - Time loss if there are many devices to query;
New data is not always available;
Data may be lost if it changes quickly.
2-Interrupt: when a data appears on a device, the I/O circuit signals it
to the microprocessor so that it reads the data: it is a request
interrupt (IRQ: Interrupt Request):
Advantage: the microprocessor performs a read of the I/O ports only when a
Data is available, which saves time and avoids data loss.
Examples of devices using interrupts:
Keyboard: request for interruption when a key is pressed;
Serial port: request for interruption upon arrival of a character on the line.
transmission.
Request
interruption
Microprocessor Interface
Interruption
accepted

Figure VII.1: Interrupt Signals between Microprocessor / Interface

II. Handling an interrupt by the microprocessor [9]

Following a request for interruption by a device and if the interruption request
is accepted:

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The microprocessor completes the execution of the current instruction and deactivates the
interruptions,
He stores the program counter's content in the stack, address of the next one
instruction to execute, for a possible return,
It issues an acknowledgment (Interrupt Acknowledge: INTA) indicating to the I/O circuit
that the request for interruption is accepted:
He abandons the execution of the current program and will execute a sub-program of
interrupt service (ISR: Interrupt Service Routine),
After the execution of the ISR, the registers are restored from the stack and the
The microprocessor resumes execution of the program it had abandoned.

Main program
Under program of
interruption service
Arrival of the
request
interruption

Return to
main program

Figure VII.2: Steps for executing the ISR

Remarks
1. The microprocessor can reject the interrupt request: it is then masked.
Masking of an interrupt is generally done by positioning a switch 'EI' (Enable
Interrupt).
There is a non-maskable interrupt (TRAP) that is always taken into account by the
microprocessor
3. The last instruction of an interrupt service subroutine must be
the instruction "RET".

III. Interruptions of the 8085 [16]

A maskable interrupt service can be activated by the instruction 'EI'. In this case, a
"EI" flag is set to 1; otherwise, the interrupt is disabled by the "DI" instruction (IE=0).
Two types of interrupts are recognized by the 8085:
Software interruptions produced by the RST instruction.
Material interruptions caused by the activation of at least one of the five lines
RST7.5, RST6.5, RST5.5, INTR and TRAP of the microprocessor.

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III.1. Software Interruptions (RST Instruction 'Restart')
The 8085 includes eight RST instructions (Table VII.1). These are single instruction.
octet. These instructions are calls that allow for the transfer of execution of the
programs at well-specified memory positions. A return to the main program will
ensured by the retrieval of the stack's CP upon the execution of the RET instruction.

RST 0 CALL 0000H RST 4 CALL 0020H

RST 1 CALL 0008H RST 5 CALL 0028H
RST 2 CALL 0010H RST 6 CALL 0030H
RST 3 CALL 0018H RST 7 CALL 0038H
Table VII.1: Addresses of software interruption calls

III.2. Material Interruptions

There are two types of interrupts for the 8085: non-vectored and vectored.

III.2.1. Non-vectored interrupt INTR

Upon receiving an INTR signal from an input interface, the microprocessor
send an acknowledgment on the INTA line to indicate to the interface that the interruption has
was accepted (if EI=1). The memory position of the interrupt service routine (ISR) is
unknown. So it is up to the interface to send the address of the ISR to the microprocessor.

III.2.2. Vectorized Interruptions

The 8085 has four interrupts vectored by order of priority: TRAP (Non-maskable interrupt
maskable), RST 7.5, RST 6.5, RST 5.5. The positions of the interrupt subprograms
are as follows:
TRAP 0024H
RST 7.5 003CH
RST 6.5 0034H
RST 5.5 002CH
Table VII.2: Address of calls for hardware interrupt lines

III.2.2.1. TRAP
TRAP is recognized by NMI (Non Maskable Interrupt). This interruption cannot be inhibited.
It is a disruption used in critical situations such as power issues,...

III.2.2.2. RST 7.5, 6.5, and 5.5

These are maskable interrupts triggered by EI and SIM (Set Interrupt Mask) which...
The description is given as follows.
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Instruction SIM
It is a single byte instruction. This instruction reads the content of the accumulator and activates
You disable the maskable instructions RST 7.5, RST 6.5, and RST 5.5 according to the content of
A.
7 6 5 4 3 2 1 0
SOD SDE X R7.5 MSE M7.5 M6.5 M5.5

Mask by "1" RST7.5,

Ignored RST6.5 and RST5.5

Masking bits 2, 1, and 0: 0 masked, 1 not masked
Resetting of the RST7.5 switch if MSE=1
If = 1, the bit D7is sent
Value of the bit to be sent, ignored if D6= 0

Figure VII.3: Configuration of hardware interrupts RST

The D bit3is a control bit, if this bit is 1 the D bits2, D1and D0are effective. The
Logic level 0 of these three bits activates the interrupt and 1 denies the interrupts. Otherwise for
D3If 0, these three bits are ignored.
The D bit4is used for the command of RST 7.5. If this bit = 1, RST 7.5 is set to zero.
Ceci est utilisé pour ignorer RST 7.5.
3. The D bits7and D6are used in serial transmission.
Example:
1. To accept interrupts in a 8085 based system.
EI
MVI A,08H
YES
2. For resetting interruption 7.5
Move immediate value A, 18H

YES

Pending Interruptions
The fact that there are multiple interrupt lines, when one interrupt is serviced, the other
interrupts must wait. The 8085 has a second instruction called RIM (Read
Interrupt Mask) to know the pending interrupts.

Instruction RIM
This is a single-byte instruction. This instruction is defined as follows:
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7 6 5 4 3 2 1 0
SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5

Hide interruptions
1 = masquée

Interruption valide (=1); non valide (0)

{"Interruptions en attente : 1 = attente":"Pending interruptions: 1 = waiting"}

Receiving a bit in series: if it is used

Figure VII.4: Reading the states of hardware interrupts

1. For reading the status of masked interrupts. This instruction loads the accumulator
A with 8 bits indicating the state of the masks.
2. For the identification of pending interrupts. The D bits6, D5and D4identify the
pending interruptions.
3. Pour la réception sérielle des données, le bit D7is used.

Example:
It is assumed that the 8085 is executing a RST 7.5 interrupt request. A
Verification of RST 6.5 waiting for example. If there is a wait, an activation of RST
6.5 must be done without assigning other interrupts, otherwise return to the program
principal.
RIM Reading the interrupt mask
MOVE B, A Save the mask in B
ANI 20H Check if there is a waiting for RST 6.5
JNZ NEXT
EI
RET RST 6.5 not in waiting, returning to the main program
NEXT: MOV A,B RST is pending
ANI 0DH Validate RST 6.5 by resetting D to zero1

ORI 08H Validate SIM by setting D to 13

YES
JMP SERV Go execute the service of routine RST 6.5

IV. Programmable Interrupt Controller, PIC 8259 [16]

To connect multiple devices using interrupts, one can use the
programmable interrupt controller 8259 whose role is to:
receive requests for interruptions of devices,
address the priorities of interruptions
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generate the interrupt signals,
issue the interrupt number on the data bus.
An 8259 can manage up to 8 hardware interrupt requests. The pinout of such a device
the circuit is given by figure VII.5.

CS VCC
WR A0
RD INTA
D7 IR7
D6 IR6
D5 IR5
D4 8259 IR4
D3 IR3
D2 IR2
D1 IR1
D0 IR0
CAS0 INT
CAS1 SP/EN
GND CAS2

Figure VII.5: Broaching of the 8259

CAS0, 1, 2: Used in cascading PIC8259s to increase the number

up to 64 processor interrupts. In Slave mode, the CAS0,1,2 are ignored.
IR0..7: are request inputs (Interrupt Request); depending on the initialization, one can
choose sensitive inputs at a high level or at the rising edge.
SP/EN(Slave Programming/Enable): (SP/EN ='1') Master, SP/EN = '0' Slave.
Note: if the number of interruption requests exceeds 8, we can place
multiple 8259 in cascade:

IRQ0
IR0
IRQ1
PIC 8259 IR1
IRQ2
Master IR2
INTR IRQ3
INT IR3
INTA IRQ4
INTA IR4
IRQ5
8 PM IR5
IRQ6
IR6
IR7 IRQ7

CAS0 CAS1 CAS2

CAS0 CAS1 CAS2

IR0 IRQ8

PIC 8259 IR1 IRQ9

Exclave IR2 IRQ10

INT IR3 IRQ11
INTA IR4 IRQ12

A0h IR5 IRQ13

IR6 IRQ14
IR7 IRQ15

Figure VII.6: Cascading two 8259

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The component provides for two modes of priority management:
Automatic rotation: in this mode, when a device has been served, it receives the
lowest priority so that in the worst case, a device
the requester only has to wait for the other seven devices to be served at most
only once.
The specific rotation: in this mode, the programmer can change the input assigned to
the lowest priority, the other priorities being set based on this one.
In PCs, the second solution was chosen. This mode is programmed during
the initialization of your motherboard by the BIOS. It is the IRQ7 entry that receives the highest priority.
low and IRQ0 the highest priority. The fact that the second controller is cascaded
on IRQ2 of the first controller, we will have in descending order of priority the ...
following entries:
IRQ0, IRQ1, IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15, IRQ3, IRQ4
IRQ5, IRQ6, IRQ7.
The PIC has internal registers that manage interrupts. These include:
IRR: (Interrupt request Register)
IMR: (Interrupt Mask Register)
ISR: (In Service Register)

Control logic

IR0
ISR IRR IR1
IR2
In- Resolution Interrupt IR3
Service of priority Request IR4
Register Register IR5
IR6
IR7

IMR : Interrupt Mask Register

Figure VII.7: Internal Diagram of the PIC 8259

The eight input lines pass through the masking register which will determine whether a
entry is hidden or not. If it is hidden, the request arriving on this line will not be
consideration. If it is not masked, the request will be recorded in the register of

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request for interruption which will keep her until the moment she is served. Depending on
with scheduled priorities, the PIC will be able to determine which interrupt it should handle. It
Send an INT request to the microprocessor by activating its INT pin.
The microprocessor finishes its current instruction and will inform the PIC that it accepts the
request by activating its INTA (Interrupt Acknowledge) terminal.
Upon receiving this signal, the PIC will set the corresponding bit for the serviced interrupt.
in the ISR register to '1' and the corresponding bit in the IRR register to '0'.
The microprocessor will then send a second INTA signal indicating to the PIC that it must
place on the data bus the number of the software interrupt that needs to be served. This
the number is constructed as follows by the PIC: the three least significant bits
corresponding to the interrupt number while the five most significant bits
corresponding to a preprogrammed value during the initialization of the PIC. For PCs, the PIC
the master receives the value 00001 and the slave PIC the value 01110. If we take the hardware IRQ
3 (IRQ master PIC 3), this will correspond to 00001011b (0BH) while if we take
the hardware IRQ 10 (slave PIC IRQ 2), this will correspond to 01110010 (72).
Let's now analyze priority management:
Let's start from an initial condition where the material interruption 4 is served. We will find back
so the following data in the different records:

IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0

0 0 0 0 0 0 0 0
IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0
0 0 0 0 0 0 0 0

Suppose two interrupt requests occur on the inputs IR6 and IR2 of the
PIC. IRQ6 being less prioritized than the ongoing interrupt 4, the request
stay on hold.
IRQ2 being more prioritized than the interruption 4 currently being processed will be handled next.
count by the PIC. It will therefore send an INT request to the microprocessor which
will respond with the succession of two INTA signals. The registers will then contain the
following data:
IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0
0 1 0 0 0 0 0 0

IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0

0 0 0 1 0 1 0 0

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It is important to note that the running IRQ4 routine has been interrupted at
benefit of the IRQ2 routine. When this routine is finished, it sends an EOI (End Of
Interrupt) to the PIC. It, by analyzing its ISS register, knows that it is an end signal.
of interruption for IRQ2.
Here is the content of the registers:

IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0

0 1 0 0 0 0 0 0

IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0

0 0 0 1 0 0 0 0

The processor having completed the execution of the IRQ2 routine, it returns to the execution of the
code before interruption: it was the IRQ4 routine. When this routine ends,
It sends an EOI (End Of Interrupt) to the PIC. By analyzing its ISS register, it knows
This is a termination signal for IRQ4. Here is the content of the registers:
IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0
0 1 0 0 0 0 0 0

IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0

0 0 0 0 0 0 0 0

The PIC can then take into account the IRQ6 request since there are no other.
priority request currently being processed.

Redirection IRQ2/IRQ9: despite the fact that this interrupt was reserved from the
first PC XT for cascading a second controller, some manufacturers
used this interruption for a completely different purpose by using it for some
devices. When AT PCs appeared on the market, it required some tricks to
maintain compatibility with such devices. IRQ9 was then used to
replace IRQ2 but the problem was that IRQ9 was present on the slave controller
while IRQ2 was initially on the master controller. The problem was resolved by the
As follows: at the level of the routine associated with IRQ9, an EOI is sent to the PIC
slave and then an ISR is called for IRQ2.

IV.1. Initialization of the PIC 8259

1- Configuration of the ICW1 (20h for the 1st 8259 and A0h for the 2nd):
Bits 7, 6 and 5 to 0
Bit 4 to 1 to mark the beginning of the initialization sequence.
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Bit 3 set to 1 to trigger interrupts by level or set to 0 for edge.
Bit 2 to 0
Bit 1 if the 8259 is alone or 0 if cascaded
Bit 0 at 0 of ICW4

2- Configuration of the ICW2 (21h for the 1st 8259 and A1h for the 2nd):

The ICW2 is there to manage the offset of the IRQ number and the associated interrupt in the
interrupt vector table. So:
for the first 8259: ICW2 = 08h. From 08h to 0Fh.
for the second 8259: ICW2 = 70h. From 70h to 77h.

3- Configuration of ICW3 (Only if cascaded)(21h or A1h)

Used only when multiple PICs are cascaded. One PIC with 8 PICs. 64 Interruptions
Hardware.
ICW3 for master: Bit corresponding to input at 1 for slave; Assuming that bit
7 and bit 4 are '1' Two slave circuits used connected to IR7 and IR4
ICW3 for the slave: Bits 0,1,2 for the slave number; PIC IR number
Master that is connected to this Slave PIC.

Example:
Initialization of the PIC8259 with the following data:
CPU8085, address 20h, Single (no Cascade), IRx in Level Trigger, INT 08H on IR0. The
PIC8259 being in normal EOI mode.
ICW1 000 1 1 0 1 1 1BH (Need for ICW4, PIC Only, IRx Trigger Level)
ICW2 0000 1000 08H (000 IR0 INT 08H
ICW3 No need, only one PIC is used.
ICW4 0000 0000 00H

Here is the initialization program of the PIC8259

Move immediate value A into register 1BH ICW1
OUT 20H ; Vers Port 20H
ICW2
Load immediate value 08H into register A

OUT 21H To Port 20H

ICW4
Load immediate value 01H into accumulator A

OUT 9 PM Vers Port 21H

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IV.2. Order Registers

After initializing the 8259, can access the command words OCW1-2-3.
OCW1: IMR (Interrupt Mask Register), address: 21h/A1h. Each bit represents a
interruption, 1 = masquée.
OCW2: EOI command register, address: 20h/A0h. To access it, you need the
bits 3 and 4 to 0. This is where an EOI should be signaled by writing 20h, which will have
effect of clearing the corresponding bit in the ISR and thus allowing any interruption
less than or equal to. If bits 2, 1, and 0 are 011 respectively the levels of
priorité sont : IR3, IR4, IR5, IR6, IR7, IR0, IR1, IR2.
OCW3: Allows reading the IRR (Interrupt Request Register) or the ISR (Interrupt Service)
Register) by positioning the corresponding bits and then rereading OCW3. To do so
to access it, bit 3 must be 1 and bit 4 must be 0, always at address 20h/A0h

Example:
The figure shows the diagram of a system using the 8259. Four sources are connected to the
IR lines of the 8259; Emergency signal, Keyboard, A/D Converter, and Printer. The signal
Urgency has the highest priority and the printer has the lowest priority.

A7
A6 IR0 Emergency signal
A5 IR1 Keyboard
E1E2E3 IR2 A/N Converter
A3 MSB A2
8259
A2 A1
A1 A0 O0 CS
LSB IR6
A0 A0 Printer
74LS138

Figure VII.8: Example of application of the 8259

Initialization instructions
DI
Load immediate value 76H into register A; ICW1

OUT 80H Initialization of the 8259

Move immediate value A into port 20H ; Initialization Command Word 2

OUT 81H Initialization of the 8259

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1. DI disables interrupts, which means that the initialization process will not be
interrupted.
2. The command word 76H specifies the following parameters:
0 1 1 1 0 1 1 0 =76H
A single 8259
Address bits A7 A6 A5 Impulse Call of the address range
lightweight for the four positions

The low-order byte of the IR0 call address is:

A7 A6 A5 A4 A3 A2 A1 A0
0 1 1 0 0 0 0 0 =60H

The address bits A4-A0 are provided by the 8259. The resulting addresses are four.
addresses.
3. The address of the port of the 8259 for ICW is 80H; A0must be set to logical level 0 and the

other bits are determined by the decoder.

4. The ICW2 command word is 20H, which specifies the high byte of the interrupt vector address.

5. The address of the ICW2 port is 81H; A0must be set to 1.

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