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Majority Function Logic Design Exercise

The document outlines an exercise to design a logic circuit for the majority function with three inputs (A, B, C) and one output (Q). It requires the submission of a truth table, derivation and simplification of the output equation in both SOP and POS forms, screenshots of the schematic design and waveform in SOP form, and Verilog code design with its waveform in POS form. Additionally, all Quartus Prime Software design files must be submitted in a zipped folder, with student ID visible on all screenshots.

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7 views4 pages

Majority Function Logic Design Exercise

The document outlines an exercise to design a logic circuit for the majority function with three inputs (A, B, C) and one output (Q). It requires the submission of a truth table, derivation and simplification of the output equation in both SOP and POS forms, screenshots of the schematic design and waveform in SOP form, and Verilog code design with its waveform in POS form. Additionally, all Quartus Prime Software design files must be submitted in a zipped folder, with student ID visible on all screenshots.

Uploaded by

q8.a7mad00
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Extra Lab Exercise

In Boolean logic, the majority function is the Boolean function that evaluates to false when half or more
arguments are false and true otherwise, i.e. the value of the function equals the value of the majority of
the inputs. Representing true values as 1 and false values as 0.

Design the logic circuit of the majority function with three inputs (A, B, C) and one output (Q). You need
to submit the following:

• Pdf file containing:


1. The truth table of the function, as the one shown below.
Input Output Minterms Maxterms

A B C Q Term Designation Term Designation


0 0 0 0 A’ B’ C’ m0 A+B+C M0

0 0 1 0 A’ B’ C m1 A+B+C’ M1

0 1 0 0 A’ B C’ m2 A+B’+C M2

0 1 1 1 A’ B C m3 A+B’+C’ M3

1 0 0 0 A B’ C’ m4 A’+B+C M4

1 0 1 1 A B’ C m5 A’+B+C’ M5

1 1 0 1 A B C’ m6 A’+B’+C M6

1 1 1 1 ABC m7 A’+B’+C’ M7

2. Derivation and detailed simplification steps of the output equation in both SOP and POS
forms.
1

1 1

0 0

0 1

1 1

0 1

3. Full screenshot of the schematic design and its waveform for the output equation in SOP
form (2 screenshots).
4. Full screenshot of the Verilog code design and its waveform for the output equation in
POS form (2 screenshots).
Zipped file for the folder containing all your Quartus Prime Software design files.

P.S. You need to show your student ID at the top toolbar of every screenshot of your Quartus Prime
Software design files and waveforms (total of 4 screenshots).

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