YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Objectives:
1. To understand the operation theory of FSK demodulator.
2. To implement the FSK detector circuit by using PLL.
3. To understand the operation theory of comparator by using operational
amplifier as voltage level converter.
1. Theory Review
In chapter 13 we use FSK modulator for long distance communication, which
the voltage level of digital signal has been converted to frequency. Therefore, at the
receiver, we have to recover the FSK signal to digital signal, that means the
frequency should be converted back to voltage. We use phase locked loop (PLL) as
FSK demodulator. PLL is a kind of automatic tracking system, which is able to detect
the input signal frequency and phase. PLL is widely used in wireless applications,
such as AM demodulator, FM demodulator, frequency selector and so on. In the
digital communications, various types of digital PLLs are developed. Digital PLL is very
useful in carrier synchronization, bit synchronization and digital demodulation.
Figure (1) Structure diagram of FSK modulator
2. Synchronous FSK Detector
Let the received data signal 𝑉𝐹𝑆𝐾 (𝑡) multiply by local oscillation(LO)
signalscos(𝜔𝐶 + 𝜔𝐷 )𝑡 or cos(𝜔𝐶 − 𝜔𝐷 )𝑡 as shown in equations (1) and (3). Then we
can obtain cos[2(𝜔𝐶 + 𝜔𝐷 )]𝑡, which the digital signal frequency is represented as 1
or cos[2(𝜔𝐶 − 𝜔𝐷 )]𝑡, which the digital signal frequency is represented as 0. After
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YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
that by using the filter to remove the second order harmonics and DC voltage, then
we can obtain the original digital signal as shown in figure (2).
In this section, we utilize the theory of mathematic to solve the FSK
demodulation as shown in equation (1). The synchronous FSK detector needs two LO
oscillators, which the LO frequencies are 𝜔𝐶 − 𝜔𝐷 and 𝜔𝐶 + 𝜔𝐷 , respectively, as
shown in figure (2). When the received signal is cos[2(𝜔𝐶 + 𝜔𝐷 )]𝑡 , then we get:
𝑣(𝑡) = 𝐴 cos(𝜔𝐶 + 𝜔𝐷 )𝑡 [cos(𝜔𝐶 + 𝜔𝐷 )𝑡 − cos(𝜔𝐶 − 𝜔𝐷 )𝑡]
= 𝐴 cos 2 (𝜔𝐶 + 𝜔𝐷 )𝑡 − 𝐴 cos(𝜔𝐶 + 𝜔𝐷 )𝑡 cos(𝜔𝐶 − 𝜔𝐷 )𝑡
𝐴 𝐴
= − [cos(2𝜔𝐶 𝑡) + cos(2𝜔𝐷 𝑡) − cos(2(𝜔𝐶 + 𝜔𝐷 )𝑡)] (1)
2 2
By using a filter to remove all the unwanted signal in equation (1) then the
represented output signal frequency is 1 and we can rewritten equation (1) as
follow:
𝐴
𝑣1 (𝑡) = cos[2(𝜔𝐶 + 𝜔𝐷 )𝑡] (2)
2
𝜔𝐶 : Carrier frequency.
𝜔𝐷 : Signal frequency.
When the received signal is cos(𝜔𝐶 − 𝜔𝐷 )𝑡 , then we get:
𝑣(𝑡) = 𝐴 cos(𝜔𝐶 + 𝜔𝐷 )𝑡 [−cos(𝜔𝐶 + 𝜔𝐷 )𝑡 + cos(𝜔𝐶 − 𝜔𝐷 )𝑡]
= −𝐴 cos 2 (𝜔𝐶 + 𝜔𝐷 )𝑡 + 𝐴 cos(𝜔𝐶 + 𝜔𝐷 )𝑡 cos(𝜔𝐶 − 𝜔𝐷 )𝑡
𝐴 𝐴
= − + [cos(2𝜔𝐶 𝑡) + cos(2𝜔𝐷 𝑡) − cos(2(𝜔𝐶 + 𝜔𝐷 )𝑡)] (3)
2 2
By using a filter to remove all the unwanted signal in equation (3) then the
represented output signal frequency is 0 and we can rewritten equation (1) as follow
𝐴
𝑣2 (𝑡) = cos[2(𝜔𝐶 − 𝜔𝐷 )𝑡] (4)
2
Generally, phase locked loop (PLL) can be divided into 3 main parts, which are the
phase detector (PD), loop filter (LF) and voltage controlled oscillator (VCO). The block
diagram of PLL is shown in figure (3).
In figure (3), when the input signal frequency changes, the output signal of
the phase detector will change and so as well as the output voltage. We can use this
characteristic to design the FSK demodulator. Let the FSK signal frequencies as 𝒇1
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Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
and 𝒇𝟐 . Then these signals are inputted to the input terminal of figure (3). When the
signal frequency is 𝒇𝟏 , the output voltage will be 𝑽𝟏 When the input signal frequency
is 𝒇𝟐 , the output voltage is 𝑽𝟐 At this moment, we have converted the frequency to
voltage. If we add a comparator at the output terminal of PLL, the reference voltage
will lie between 𝑽𝟏 and 𝑽𝟐 , then at the output terminal of comparator, we are able
to obtain the digital signal, which is the demodulated FSK signal.
Figure (2) Block diagram of synchronous FSK detector.
In this experiment, we implement the FSK demodulator by using LM565 PLL
as shown in figure (4). The operation frequency of LM565 PLL is below 500 kHz and
the internal circuit diagram is shown in figure (4) It includes phase detector, voltage
controlled oscillator and amplifier. The phase detector is a double-balanced
modulator type circuit and the VCO is integrated Schmitt circuit.
Figure (3) Block diagram of PLL.
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Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Figure (4) Circuit diagram of FSK demodulator.
Pin 1 is connected to negative voltage supply, -5 V. Pins 2 and 3 are
connected to the input signals, but normally pin 3 will connect to ground. If pins 4
and 5 are connected to frequency multiplier, then various multiplications of
frequencies can be obtained. In this experiment, we need not use the frequency
multiplier, therefore, these two pins are shorted. Pin 6 is the reference voltage
output. The internal resistor (𝑹𝒙 ) of pin 7 and the external capacitor (𝑪𝟑 ) comprise a
loop filter. Pin 8 is connected to timing resistor (𝑽𝑹𝟏 ). Pin 9 is connected to timing
capacitor (𝑪𝟐 ). Pin 10 the positive voltage supply +5 V of LM565. The important
parameters of LM565 PLL circuit design are as below:
1. The Free-Running Frequency of LM565
When LM565 without any input signal, the output signal of VCO is called free-
running frequency. The 𝑪𝟐 is timing capacitor and the variable resistor 𝑽𝑹𝟏 is timing
resistor. The free-running frequency (𝒇𝟎 ) of VCO of the LM565 is determined by 𝑪𝟐
and 𝑽𝑹𝟏 . The expression is:
1.2
𝒇𝟎 = (5)
4 𝑉𝑅1 𝐶2
2. The Locked Range ofLM565
When the PLL is in locked conditions, if the frequency of the input signal (𝒇𝒊 )
deviates from 𝒇𝒐 , then the PLL will remain in the locked condition. When fi reaches
a certain frequency, which the PLL is not able to lock, then the difference between 𝒇𝒊
and 𝒇𝒐 is called the locked range. The locked range of LM565 can be expressed as:
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Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
8 𝑓𝑜 8 𝑓𝑜
𝒇𝑳 = = (6)
𝑉𝑐 𝑉𝑐𝑐 −𝑉𝐸𝐸
3. The Captured Range of LM565
The initial mode of PLL is in unlocked condition, then the frequency of the input
signal (𝒇𝒊 ) will come near to 𝒇𝒐 . When fi reaches a certain frequency, the PLL will be
in locked condition. At this moment, the difference between 𝒇𝒊 and 𝒇𝒐 is called the
captured range. The captured range of LM565 can be expressed as
𝟏 𝑳𝟐𝝅×𝒇
𝒇𝑪 = � 𝟑
(7)
𝟐𝝅 𝟑.𝟔×𝟏𝟎 ×𝑪 𝟐
In figure (4), pin 7 of LM565 is connected to 𝑹𝟑 , 𝑹𝟒 , 𝑹𝟓 , 𝑪𝟑 , 𝑪𝟒 𝑎𝑛𝑑 𝑪𝟓 to comprise a
low-pass filter. The objective is to remove the unwanted signal, which will cause the
comparator produce incorrect action. µA741 is the comparator and its reference
voltage is inputted at pin 6 of LM565. The output voltage of LM565 will pass through
µA741 and 𝑫𝟏 to obtain the output voltage of digital signal of TTL level.
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Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Practical 1: XR 2206 FSK modulator
1. Refer to the circuit diagram in figure DCS 14-1 on ETEK DCS-6000-07 module.
Without adding any signal at the input terminal (FSK I/P), then by using
oscilloscope, observe on the VCO output (TP1) of LM565, adjust variable
resistor 𝑽𝑹𝟏 so that the free-running frequency ofLM565 operates at 1170
Hz.
2. At the input terminal (FSK I/P) of figure DCS14-1, input 4 V amplitude and
870 Hz sine wave frequency. By using oscilloscope and switching to DC
channel, then observe on the output signal waveform of FSK I/P, TP1 , charge
and discharge test point (TP2), low-pass loop circuit 1 (TP3), low-pass loop
circuit 2 (TP4), low-pass loop circuit 3 (TP5), low-pass loop circuit 4 (TP6),
reference voltage of the comparator (TP7), output terminal of the
comparator (TP8) and data signal output port (Data O/P). Finally, record the
measured results in table (1).
3. At the input terminal (FSK I/P) of figure DCS 14-1, input 4 V amplitude and
1370 Hz sine wave frequency. Repeat step 2 and record the measured results
in table (2).
4. Refer to figure (3) with 𝑹𝟏 = 7.5 𝑘Ω and 𝑹𝟓 = 15 𝑘Ω or refer to figure DCS
13-1 on ETEK DCS-6000-07 module. Let J2 and J4 be open circuit, J3 and J5 be
short circuit.
5. Without adding any signal at the input terminal (FSK l/P) of figure DCS14-1,
then by using oscilloscope, observe on the VCO output (TP1) of LM565, adjust
variable resistor 𝑽𝑹𝟏 so that the free-running frequency of LM565 operates
at 1170 Hz.
6. At the data signal input terminal (Data l/P) of figure DCS 13-1, input 5 V
amplitude, 150 Hz TTL signal.
7. Connect the modulated FSK signal (FSK O/P) of figure DCS 13-1 to the input
terminal (FSK l/P) of figure DCS 14-1. By using oscilloscope, observe on the
output signal waveforms of TP1, TP2, TP3, TP4, TP5, TP6 and Data O/P.
Finally record the measured results in table (3).
8. According to the input signal in table (3), repeat step 6 to step 7 and record
the measured results in table(3).
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YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Practical 2: LM 565 FSK demodulator
1. Refer to the circuit diagram in figure 13-6 or figure DCS 13-2 on ETEK DCS-
6000-07 module.
2. From figure DCS 13-2, let the data signal input terminal (Data l/P) be short
circuit and J1 be open circuit, i.e. input 0 V DC voltage to the data signal input
terminal (Data l/P). By using oscilloscope, observe on the output signal
waveform of the VCO output port (TP1) of LM 566. Slightly adjust 𝑽𝑹𝟏 so that
the output frequency of TP1 is 1370 Hz. Again let the data signal input
terminal (Data l/P) be open circuit and J1 be short circuit, i.e. input 5 V DC
voltage to the data signal input terminal (Data I/P). By using oscilloscope,
observe on the output signal waveform of the VCO output port (TP1) of LM
566. Slightly adjust 𝑽𝑹𝟏 so that the output frequency of TP1 is 870 Hz.
3. Without adding any signal at the input terminal (FSK l/P) of figure DCS14-1,
then by using oscilloscope, observe on the VCO output (TP1) of LM565, adjust
variable resistor 𝑽𝑹𝟏 so that the free-running frequency of LM565 operates at
1170 Hz.
4. At the data signal input terminal (Data l/P) of figure DCS 13-1, input 5 V
amplitude, 150 Hz TTL signal. Connect the modulated FSK signal (FSK O/P) of
figure DCS 13-2 to the input terminal (FSK l/P) of figure DCS 14-1. By using
oscilloscope and switching to DC channel, observe on the output signal
waveforms of FSK l/P, TP1, TP2, TP3, TP4, TP5, TP6 and Data O/P. Finally
record the measured results in table (4).
5. According to the input signal in table (4), repeat step 4 and record the
measured results in table (4).
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Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Data Signal
Data I/P TP1
Frequencies
TP2 TP3
𝟖𝟕𝟎 𝑯𝒛
TP4 TP5
Table (1) Measured results of FSK demodulator. (𝑉𝑖𝑛 = 4 𝑉)
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Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Carrier Signal
TP6 TP7
Frequencies
870 Hz
TP8 Data O/P
Table (1) Measured results of FSK demodulator. (𝑉𝑖𝑛 = 4 𝑉). (Continue)
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Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Carrier Signal
Data I/P TP1
Frequencies
TP2 TP3
𝟏𝟑𝟕𝟎 𝑯𝒛
TP4 TP5
Table (2) Measured results of FSK demodulator. (𝑉𝑖𝑛 = 4 𝑉)
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YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Carrier Signal
TP6 TP7
Frequencies
1370 Hz
TP8 Data O/P
Table (2) Measured results of FSK demodulator. (𝑉𝑖𝑛 = 4 𝑉). (Continue)
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YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Carrier Signal
Data I/P TP1
Frequencies
TP2 TP3
𝑽𝒑 = 𝟓 𝑽
𝟏𝟓𝟎 𝑯𝒛
TP4 TP5
Table (3) Measured results of FSK demodulator using 2206 IC (J3, J5 SC; J2, J4 OC)
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YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Carrier Signal
TP6 TP7
Frequencies
𝑽𝒑 = 𝟓 𝑽
𝟏𝟓𝟎 𝑯𝒛 TP8 Data O/P
Table (3) Measured results of FSK demodulator by using 2206 IC. (J3, J5 SC; J2, J4 OC)
(Continue)
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YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Carrier Signal
Data I/P TP1
Frequencies
TP2 TP3
𝑽𝒑 = 𝟓 𝑽
𝟐𝟎𝟎 𝑯𝒛
TP4 TP5
Table (3) Measured results of FSK demodulator using 2206 IC (J3, J5 SC; J2, J4 OC) (Continue)
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YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Carrier Signal
TP6 TP7
Frequencies
𝑽𝒑 = 𝟓 𝑽
𝟐𝟎𝟎 𝑯𝒛 TP8 Data O/P
Table (3) Measured results of FSK demodulator by using 2206 IC. (J3, J5 SC; J2, J4 OC)
(Continue)
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YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Carrier Signal
Data I/P TP1
Frequencies
TP2 TP3
𝑽𝒑 = 𝟓 𝑽
𝟏𝟓𝟎 𝑯𝒛
TP4 TP5
Table (4) Measured results of FSK demodulator using LM 566
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YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Carrier Signal
TP6 TP7
Frequencies
𝑽𝒑 = 𝟓 𝑽
𝟏𝟓𝟎 𝑯𝒛 TP8 Data O/P
Table (4) Measured results of FSK demodulator by using LM 566 (Continue)
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YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Carrier Signal
Data I/P TP1
Frequencies
TP2 TP3
𝑽𝒑 = 𝟓 𝑽
𝟐𝟎𝟎 𝑯𝒛
TP4 TP5
Table (4) Measured results of FSK demodulator using LM 566 (Continue)
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YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Carrier Signal
TP6 TP7
Frequencies
𝑽𝒑 = 𝟓 𝑽
𝟐𝟎𝟎 𝑯𝒛 TP8 Data O/P
Table (4) Measured results of FSK demodulator by using LM 566 (Continue)
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YARMOUK Private University Assignment 14
Faculty of Informatics and Communication Engineering FSK Demodulator
Digital Communication Lab
Problem Discussion
1. In figure (4), what are the factors that determine the free-running frequency
ofLM565 PLL?
2. In figure (4), what are the purposes of µA741?
3. In figure (4), what are the functions of pin 6 of LM565?
4. Why the output signal of LM565 must pass through the multi-stages low-pass
filter, and then connects to comparator?
*These questions should be answered in the report.
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