UNIT IV INPUT OUTPUT ORGANIZATION

Input/ Output Subsystem

The Input / output organization of computer depends upon the size of computer and the
peripherals connected to it. The I/O subsystem of a computer provides an efficient mode of
communication between the central system and the outside environment. It handles all the input
output operations of the computer system.

Peripheral Devices:

Input or output devices that are connected to computer are called peripheral devices. These
devices are designed to read information into or out of the memory unit upon command from the CPU
and are considered to be the part of computer system. These devices are also called peripherals.

For example: Keyboards, display units and printers are common peripheral devices.

There are three types of peripherals:

Input peripherals: Allows user input, from the outside world to the computer. Example: Keyboard,
Mouse etc.

Output peripherals: Allows information output, from the computer to the outside world. Example:
Printer, Monitor etc

Input-Output peripherals: Allows both input(from outside world to computer) as well as,
output(from computer to the outside world). Example: Touch screen etc.

Interface:

Input Output Interface provides a method for transferring information between internal storage
and external I/O devices.

Interface is a shared boundary between two separate components of the computer system
which can be used to attach two or more components to the system for communication purposes.

There are two types of interface:

1. CPU Interface

2. I/O Interface

Input-Output Interface:

Input-output interface provides a method for transferring information between internal

storage and external I/0 devices.

Peripherals connected to a computer need special communication links for interfacing them
with the CPU.

The purpose of the communication link is to resolve the differences that exist between
the central computer and each peripheral.
The major differences are:

o Peripherals are electromechanical/electromagnetic devices and CPU/memory are

electronic devices. Therefore, a conversion of signal values may be required.
o The data transfer rate of peripherals is usually slower than the transfer rate of the CPU.
Therefore, a synchronization mechanism may be needed.
 Data codes and formats in peripherals differ from the word format in the CPU and memory.
 The operating modes of peripherals are different from each other and each must be controlled
so as not to disturb the operation of other peripherals connected to the CPU.
 To resolve these differences, computer systems include special hardware components
between the CPU and peripherals to supervise and synchronize all input and output
transfers. These components are called interface units.

I/O bus and Interface modules:-

 A typical communication link between the processor and several peripherals is shown in
figure.
 The I/O bus consists of data lines, address lines and control lines.
 Each peripheral device has associated with it an interface unit. Each interface
 Decodes the address and control received from the I/O bus.
 Interprets address and control information for the peripheral.
 Provides signals for the peripheral controller.
 Synchronizes the data flow and supervises the transfer between peripheral and processor.

WORKING OF AN INTERFACE OR ACCESSING I/O DEVICE:

• The I/O bus from the processor is attached to all peripheral interfaces.
• To communicate with a particular device, the processor places a device address on the
address lines and function code in the control lines.
• Each interface attached to the I/O bus contains an address decoder that monitors the
address lines.
• When the interface detects its own address, it activates the path between the bus lines
and the device that it controls.
• All peripherals whose address does not correspond to the address in the bus are disabled
by their interface.
 • The function code is referred to as IO command and there are four types of commands that an
interface may receive.

Control command - It is issued to activate the peripheral and to inform it what to do.

Status command – It is used to test various status conditions in the interface and the peripheral.

Output data – It causes the interface to respond by transferring data from the bus into one of its
registers (from bus to the peripheral).

Input data – It causes the interface receives an item of data from the peripheral and places it
in its buffer register (from the peripheral to the bus).
ASYNCHRONOUS DATA TRANSFER

Synchronous - All devices derive the timing information from common clock line

Asynchronous - No common clock

 The internal operations in a digital system are synchronized by means of clock pulses supplied
by a common pulse generator.
 If the interface registers and CPU shares a common clock, the transfer is said to be
synchronous.
 Clock pulses are applied to all registers within a unit and all data transfers among internal
registers occur simultaneously during the occurrence of a clock pulse.
 If the internal timing in each unit is independent from the other, each uses its own private
clock for internal registers.
 In this case, two units are said to be synchronous to each other.
 Methods Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to indicate the time at
which data is being transmitted.

Two ways of achieving this,

1. Strobe control

2. Handshaking

STROBE CONTROL:

 The strobe control method of Asynchronous data transfer employs a single control line to time
each transfer. The strobe may be activated by either the source or the destination unit.
 The strobe control method of asynchronous data transfer employs a single control line to time
each transfer.
 The strobe may be activated by either the source or the destination unit.
 Strobe pulse is supplied by one of the units to indicate to the other unit when the transfer has
to occur a data transfer initiated by the destination unit activates the strobe pulse informing the
source to provide the data.
 The source unit responds by placing the requested binary information on the data bus.
 The data must be valid and remain in the bus long enough for the destination unit to accept it.
The falling edge of the strobe pulse can be used again to trigger a destination register.
 The destination unit then disables the strobe. The source removes the data from the bus
after a predetermined time interval.

Data Transfer Initiated by Source Unit:

The data bus carries the binary information from source to destination unit. Typically, the bus
has multiple lines to transfer an entire byte or word. The strobe is a single line that informs the
destination unit when a valid data word is available.

The source unit first places the data on the data bus. The information on the data bus and
strobe signal remains in the active state to allow the destination unit to receive the data.
Data Transfer Initiated by Destination Unit:

In this method, the destination unit activates the strobe pulse, to informing the source to
provide the data. The source will respond by placing the requested binary information on the data bus.

The data must be valid and remain in the bus long enough for the destination unit to accept it.
When accepted the destination unit then disables the strobe and the source unit removes the data from
the bus.

HANDSHAKING:

This is commonly used to accompany each data being transferred with a control signal that
indicates the presence of data in a bus.

The unit receiving the data item responds with another control signal to acknowledge receipt
of the data. This type of agreement between two independent units is referred to as handshaking.

The basic principle of the two-wire handshaking method of data transfer is as follows: One
control line is in the same direction as the dataflow in the bus from the source to the
destination. It is used by the source unit to inform the destination unit whether there are valid data in
the bus. The other control line is in the other direction from the destination to the source. It is used by
the destination unit to inform the source whether it can accept data.
Source Initiated Transfer using Handshaking:

The sequence of events shows four possible states that the system can be at any given time.
The source unit initiates the transfer by placing the data on the bus and enabling its data valid signal.
The data accepted signal is activated by the destination unit after it accepts the data from the bus.

The source unit then disables its data accepted signal and the system goes into its initial state.

Destination Initiated Transfer Using Handshaking:

The name of the signal generated by the destination unit has been changed to ready for data to
reflect its new meaning. The source unit in this case does not place data on the bus until after it
receives the ready for data signal from the destination unit. From there on, the handshaking procedure
follows the same pattern as in the source initiated case.

The only difference between the Source Initiated and the Destination Initiated transfer is in
their choice of Initial sate.
Asynchronous Serial Transmission:

The transfer of data between two units is serial or parallel. In parallel data transmission, n bit
in the message must be transmitted through n separate conductor path. In serial transmission, each bit
in the message is sent in sequence one at a time.

Parallel transmission is faster but it requires many wires. It is used for short distances and
where speed is important. Serial transmission is slower but is less expensive.

In Asynchronous serial transfer, each bit of message is sent a sequence at a time, and binary
information is transferred only when it is available. When there is no information to be transferred,
line remains idle.

In this technique each character consists of three points

 Start bit
 Character bit
 Stop bit

Start Bit- First bit, called start bit is always zero and used to indicate the beginning character.

Stop Bit-Last bit, called stop bit is always one and used to indicate end of characters. Stop bit is
always in the 1- state and frame the end of the characters to signify the idle or wait state.

Character Bit- Bits in between the start bit and the stop bit are known as character bits. The character
bits always follow the start bit.

Serial Transmission of Asynchronous is done by two ways:

 Asynchronous Communication Interface

 First In First out Buffer
Asynchronous Communication Interface:

 It works as both a receiver and a transmitter. Its operation is initialized by CPU by sending a
byte to the control register.
 The transmitter register accepts a data byte from CPU through the data bus and transferred to a
shift register for serial transmission.
 The receive portion receives information into another shift register, and when a complete data
byte is received it is transferred to receiver register.
 CPU can select the receiver register to read the byte through the data bus. Data in the status
register is used for input and output flags.
First In First Out Buffer (FIFO):

A First in First out (FIFO) Buffer is a memory unit that stores information in such a manner
that the first item is in the item first out. A FIFO buffer comes with separate input and output
terminals. The important feature of this buffer is that it can input data and output data at two different
rates.

When placed between two units, the FIFO can accept data from the source unit at one rate,
rate of transfer and deliver the data to the destination unit at another rate.

If the source is faster than the destination, the FIFO is useful for source data arrive in bursts
that fills out the buffer. FIFO is useful in some applications when data are transferred asynchronously.

MODES OF TRANSFER:

Transfer of data is required between CPU and peripherals or memory or sometimes between
any two devices or units of your computer system. To transfer a data from one unit to another one
should be sure that both units have proper connection and at the time of data transfer the receiving
unit is not busy. This data transfer with the computer is Internal Operation.

All the internal operations in a digital system are synchronized by means of clock pulses supplied
by a common clock pulse Generator. The data transfer can be

 Synchronous
 Asynchronous

When both the transmitting and receiving units use same clock pulse then such a data transfer is
called Synchronous process. On the other hand, if the there is not concept of clock pulses and the
sender operates at different moment than the receiver then such a data transfer is called Asynchronous
data transfer.

Data transfer to and from peripherals may be handled in one of three possible modes:

 Programmed I/O
 Interrupt-initiated I/O
 Direct memory access (DMA)

Programmed I/O:

In this mode of data transfer the operations are the results in I/O instructions which is a part of
computer program. Each data transfer is initiated by a instruction in the program. Normally the
transfer is from a CPU register to peripheral device or vice-versa.

Once the data is initiated the CPU starts monitoring the interface to see when next transfer can
made. The instructions of the program keep close tabs on everything that takes place in the interface
unit and the I/O devices.
Interrupt- initiated I/O:

In this method an interrupt facility an interrupt command is used to inform the device about
the start and end of transfer. In the meantime the CPU executes other program. When the interface
determines that the device is ready for data transfer it generates an Interrupt Request and sends it to
the computer.

When the CPU receives such an signal, it temporarily stops the execution of the program and
branches to a service program to process the I/O transfer and after completing it returns back to task,
what it was originally performing.

In this type of IO, computer does not check the flag. It continues to perform its task.

Whenever any device wants the attention, it sends the interrupt signal to the CPU.

CPU then deviates from what it was doing, store the return address from PC and branch to the address
of the subroutine.

There are two ways of choosing the branch address:

 Vectored Interrupt
 Non-vectored Interrupt

In vectored interrupt the source that interrupt the CPU provides the branch information. This
information is called interrupt vectored.

In non-vectored interrupt, the branch address is assigned to the fixed location in the memory.

PRIORITY INTERRUPT:

A priority interrupt is a system that establishes a priority over the various sources to
destination which condition is to be serviced first when two or more requests arrive
simultaneously. The system may also determine which conditions are permitted to
interrupt the computer while another interrupt is being serviced. Higher-priority interrupt levels are
assigned to requests, which, if delayed or interrupted, could have serious consequences.

Devices with high-speed transfer such as magnetic disks are given high-priority, and
slow devices such as keyboards receive low-priority. When two devices interrupt the computer at the
same time, the computer services the device, with the higher priority first. Establishing the priority of
simultaneous interrupt can be done by software or hardware. A polling procedure is used to identify
the highest-priority source by software means.

In this method there is one common branch address for all interrupts. The program that
takes care of interrupts begins at the branch address and polls the interrupt sources in sequence. The
order in which they are tested determines the priority of each interrupt. The highest-priority source is
tested first, and if its interrupt signal is on, control branches to a service routine for this source.
Otherwise the next-lower priority source is tested and so on. Thus the initial service routine for all
interrupts consists of a program that tests the interrupt sources in sequence and branches to one of
many possible service routines.

The particular service routine reached belongs to the highest-priority device among all devices
that interrupted the computer. The disadvantage of the software method is that if there are many
interrupts, the time required to poll them can exceed the time available to service the I/O
device. In this situation a hardware priority-interrupt unit can be used to speed up the operation. A
hardware priority-interrupt unit functions as an overall manager in an interrupt system environment. It
accepts interrupt requests from many sources, determines which of the incoming request has the
highest priority and issues an interrupt request to the computer based on this determination. To speed
up the operation each interrupt source has its own interrupt vector to access its own service routine
directly. Thus no polling is required because priority interrupt unit. The hardware priority function
can be established by either a serial or a parallel connection of interrupt lines. The serial
connection is also known as the daisy chaining method.

POLLING PROCEDURE:

There is one common branch address for all interrupts.

 Branch address contains the code that polls the interrupt sources in sequence. The highest
priority is tested first.
 The particular service routine of the highest priority device is served.
 The disadvantage is that time required to poll them can exceed the time to serve them in large
number of IO devices. Using Hardware:
 Hardware priority system functions as an overall manager.
 It accepts interrupt request and determine the priorities.
 To speed up the operation each interrupting devices has its own interrupt vector.
 No polling is required, all decision are established by hardware priority interrupt unit.
 It can be established by serial or parallel connection of interrupt lines.

PARALLEL PRIORITY INTERRUPT:

The parallel priority interrupt method uses a register whose bits are set separately by the
interrupt signal from each device priority is established according to the position of the bits in the
register. In addition to the computer register, the circuit may include a mask register whose purpose is
to control the status of each interrupt request. The mask register can be programmed to disable lower
priority interrupts while a higher priority device is being serviced. It can also provide a facility
that allows a high priority device to interrupt the CPU while a lower priority device is being serviced.
 The priority logic for a system of four interrupts sources. It consists of an
interrupt register whose individual bits are set by external conditions and cleared by program
instructions. The magnetic disk, being a high-speed device, is given the highest priority. The printer
has the next priority, followed by a character reader and a keyboard. The mask register has the same
number of bits as the interrupt register. By means of program instructions, it is possible to set or reset
any bit in the mask register. Each interrupt bit and its corresponding mask bit are applied to an AND
gate to produce the four inputs to a priority encoder. In this way an interrupt is recognized only
if its corresponding mask bit is set to 1 by the program. The priority encoder generates two bits of the
vector address, which is transferred to the CPU.
SERIAL OR DAISY CHAINING PRIORITY:

The daisy chaining method of establishing priority consists of a serial connection of all
devices that request an interrupt.

The device with the highest priority is placed in the first position, followed by lower
priority devices up to the device with the lowest priority, which is placed last in the chain.

This method of connection between these devices and the CPU is known as daisy chain
priority interrupt.

The interrupt request line is common to all devices and forms a wired logic connection.

If any device has to interrupt signal in the low-level state, the interrupt line goes to the low-
level state and enables the interrupt input in the CPU.

When no interrupts are pending, the interrupt line stays in the high-level state and no
interrupts are recognized by the CPU responds to an interrupt request by enabling the interrupt
acknowledge line.

This signal is received by device 1at its PI (Priority In) input. The acknowledge signal passes
on to the next device through the PO (Priority out) output only if device 1 is not requesting an
interrupt.

If device 1 has a pending interrupt, it blocks the acknowledge signal from the next device by
placing a 0 in the PO output.

It then proceeds to insect its own interrupt vector address (VAD) into the data bus for the
CPU to use during the interrupt cycle.

A device with a 0 in its PI input generates a 0 in its PO output to inform the next-lower-
priority device that the acknowledge signal has been blocked.

A device that is requesting an interrupt and has a 1 in its PI input will interrupt the
acknowledge signal by placing a 0 in its PO output.

If the device does not have pending interrupts, it transmits the acknowledge signal to the next
device by placing a 1 in its PO output.

Thus the device with PI-1 and PO=0 is the one with the highest priority that is requesting an
interrupt and the device places its VAD on the data bus.

The daisy chain arrangement gives the highest priority to the device that receives the
interrupt acknowledge signal from the CPU.

The farther the device is from the first position, the lower is its priority.
Direct Memory Access (DMA):

DMA is a process of communication for data transfer between memory and input/output, controlled by an
external circuit called DMA controller, without involvement of CPU. Mp- Micro processor

It has two pins HOLD and HLDA which are used for DMA operation.

First, DMA controller sends a request by making Bus Request (BR) control line high. When it receives high
signal to HOLD pin, it first completes the execution of current machine cycle, it takes few clocks and sends
HLDA signal to the DMA controller.

After receiving HLDA through Bus Grant (BG) pin of DMA controller, the DMA controller takes control over
system bus and transfers data directly between memory and I/O without involvement of CPU. During DMA
operation, the processor is free to perform next job which does not need system bus.

At the end of data transfer, the DMA controller terminates the request by sending low signal to HOLD pin and
processor regains control of system bus by making HLDA low.

In the Direct Memory Access (DMA) the interface transfer the data into and out of the
memory unit through the memory bus.

The transfer of data between a fast storage device such as magnetic disk and memory is often
limited by the speed of the CPU.

Removing the CPU from the path and letting the peripheral device manage the memory buses
directly would improve the speed of transfer. This transfer technique is called Direct Memory Access
(DMA).
 During the DMA transfer, the CPU is idle and has no control of the memory buses. A DMA
Controller takes over the buses to manage the transfer directly between the I/O device and memory.

The CPU may be placed in an idle state in a variety of ways. One common method extensively
used in microprocessor is to disable the buses through special control signals such as:

 Bus Request (BR)

 Bus Grant (BG)

These two control signals in the CPU that facilitates the DMA transfer.
The Bus Request (BR) input is used by the DMA controller to request the CPU. When this input is
active, the CPU terminates the execution of the current instruction and places the address bus, data
bus and read write lines into a high Impedance state. High Impedance state means that the output is
disconnected.

The CPU activates the Bus Grant (BG) output to inform the external DMA that the Bus Request
(BR) can now take control of the buses to conduct memory transfer without processor.

When the DMA terminates the transfer, it disables the Bus Request (BR) line. The CPU disables the
Bus Grant (BG), takes control of the buses and return to its normal operation.

The transfer can be made in several ways that are:

 DMA Burst
 Cycle Stealing

DMA Burst :- In DMA Burst transfer, a block sequence consisting of a number of memory words is
transferred in continuous burst while the DMA controller is master of the memory buses.

Cycle Stealing :- Cycle stealing allows the DMA controller to transfer one data word at a time, after
which it must returns control of the buses to the CPU.

DMA Controller:

The DMA controller needs the usual circuits of an interface to communicate with the CPU and
I/O device. The DMA controller has three registers:

 Address Register
 Word Count Register
  Control Register

Address Register :- Address Register contains an address to specify the desired location in memory.

Word Count Register :- WC holds the number of words to be transferred. The register is incre/decre
by one after each word transfer and internally tested for zero.

Control Register :- Control Register specifies the mode of transfer

The unit communicates with the CPU via the data bus and control lines. The registers in the
DMA are selected by the CPU through the address bus by enabling the DS (DMA select) and RS
(Register select) inputs. The RD (read) and WR (write) inputs are bidirectional.

When the BG (Bus Grant) input is 0, the CPU can communicate with the DMA registers
through the data bus to read from or write to the DMA registers. When BG =1, the DMA can
communicate directly with the memory by specifying an address in the address bus and activating the
RD or WR control.

DMA Transfer:

The CPU communicates with the DMA through the address and data buses as with any
interface unit. The DMA has its own address, which activates the DS and RS lines. The CPU
initializes the DMA through the data bus. Once the DMA receives the start control command, it can
transfer between the peripheral and the memory.

When BG = 0 the RD and WR are input lines allowing the CPU to communicate with the
internal DMA registers. When BG=1, the RD and WR are output lines from the DMA controller to
the random access memory to specify the read or write operation of data.

Interface is the point where a connection is made between two different parts of a system.

The strobe control method of Asynchronous data transfer employs a single control line to time
each transfer.
 The handshaking method solves the problem of strobe method by introducing a second control
signal that provides a reply to the unit that initiates the transfer.

Programmed I/O mode of data transfer the operations are the results in I/O instructions which
is a part of computer program.

In the Interrupt Initiated I/O method an interrupt facility an interrupt command is used to
inform the device about the start and end of transfer.

In the Direct Memory Access (DMA) the interface transfer the data into and out of the
memory unit through the memory bus.

Memory Organization:

A memory unit is the collection of storage units or devices together. The memory unit stores
the binary information in the form of bits. Generally, memory/storage is classified into 2 categories:

Volatile Memory: This loses its data, when power is switched off.

Non-Volatile Memory: This is a permanent storage and does not lose any data when power is
switched off.

What is Memory Hierarchy?

The memory in a computer can be divided into five hierarchies based on the speed as well as
use. The processor can move from one level to another based on its requirements. The five hierarchies
in the memory are registers, cache, main memory, magnetic discs, and magnetic tapes. The first three
hierarchies are volatile memories which mean when there is no power, and then automatically they
lose their stored data. Whereas the last two hierarchies are not volatile which means they store the
data permanently.

The memory hierarchy design in a computer system mainly includes different storage devices.
Most of the computers were inbuilt with extra storage to run more powerfully beyond the main
memory capacity. The following memory hierarchy diagram is a hierarchical pyramid for computer
memory. The designing of the memory hierarchy is divided into two types such as primary (Internal)
memory and secondary (External) memory.
Primary Memory :

The primary memory is also known as internal memory, and this is accessible by the processor
straightly. This memory includes main, cache, as well as CPU registers.

Secondary Memory:

The secondary memory is also known as external memory, and this is accessible by the
processor through an input/output module. This memory includes an optical disk, magnetic disk, and
magnetic tape.

Registers:

Usually, the register is a static RAM or SRAM in the processor of the computer which is used
for holding the data word which is typically 64 or 128 bits. The program counter register is the most
important as well as found in all the processors. Most of the processors use a status word register as
well as an accumulator. A status word register is used for decision making, and the
accumulator is used to store the data like mathematical operation. Usually, computers
like complex instruction set computers have so many registers for accepting main memory, and
RISC- reduced instruction set computers have more registers.

Cache Memory

The data or contents of the main memory that are used again and again by CPU, are stored in the
cache memory so that we can easily access that data in shorter time.
Whenever the CPU needs to access memory, it first checks the cache memory. If the data is not found
in cache memory then the CPU moves onto the main memory. It also transfers block of recent data
into the cache and keeps on deleting the old data in cache to accomodate the new one.
Main Memory
The memory unit that communicates directly within the CPU, Auxillary memory and Cache
memory, is called main memory. It is the central storage unit of the computer system. It is a large and
fast memory used to store data during computer operations. Main memory is made up of RAM and
ROM, with RAM integrated circuit chips holing the major share.

RAM: Random Access Memory

DRAM: Dynamic RAM, is made of capacitors and transistors, and must be refreshed every 10~100
ms. It is slower and cheaper than SRAM.

SRAM: Static RAM, has a six transistor circuit in each cell and retains data, until powered off.

NVRAM: Non-Volatile RAM, retains its data, even when turned off. Example: Flash memory.

ROM: Read Only Memory, is non-volatile and is more like a permanent storage for information. It
also stores the bootstrap loader program, to load and start the operating system when
computer is turned on. PROM(Programmable ROM), EPROM(Erasable PROM)
and EEPROM(Electrically Erasable PROM) are some commonly used ROMs.
Magnetic Disks

The magnetic disks in the computer are circular plates fabricated of plastic otherwise metal by
magnetized material. Frequently, two faces of the disk are utilized as well as many disks may be
stacked on one spindle by read or write heads obtainable on every plane. All the disks in computer
turn jointly at high speed. The tracks in the computer are nothing but bits which are stored within the
magnetized plane in spots next to concentric circles. These are usually separated into sections which
are named as sectors.

Magnetic Tape

This tape is a normal magnetic recording which is designed with a slender magnetizable
covering on an extended, plastic film of the thin strip. This is mainly used to back up huge data.
Whenever the computer requires to access a strip, first it will mount to access the data. Once the data
is allowed, then it will be un mounted. The access time of memory will be slower within magnetic
strip as well as it will take a few minutes for accessing a strip.

Characteristics of Memory Hierarchy:

The memory hierarchy characteristics mainly include the following.

Performance

Previously, the designing of a computer system was done without memory hierarchy, and the
speed gap among the main memory as well as the CPU registers enhances because of the huge
disparity in access time, which will cause the lower performance of the system. So, the enhancement
was mandatory. The enhancement of this was designed in the memory hierarchy model due to the
system’s performance increase.

Ability

The ability of the memory hierarchy is the total amount of data the memory can store. Because
whenever we shift from top to bottom inside the memory hierarchy, then the capacity will increase.

Access Time

The access time in the memory hierarchy is the interval of the time among the data availability
as well as request to read or write. Because whenever we shift from top to bottom inside the memory
hierarchy, then the access time will increase

Cost per bit

When we shift from bottom to top inside the memory hierarchy, then the cost for each bit will
increase which means an internal Memory is expensive compared with external memory.

Associative Memory

Associative memory is a memory unit whose database can be accessed by the data or content
instead of an address or memory location. It is also called content addressable memory or CAM. It
helps optimize searching any data as the searching process does not involve addressing, but it works
on data.
 The diagram shown above is a block diagram of the hardware organization of associative
memory.

It includes input register, mask register, select register and output register, and an associative
array with m words, each with n bits.

Here, the function of the input register is to hold the content that we want to write or search in
the associative memory. At the moment, it can hold only one word having length let us say n. The
function of the mask register is to provide a mask for selecting a specific key or field in the word of
the input register. The input register can hold single word length data, where length is n so that the
maximum value of the mask register's length can be n. The function of the select register is to contain
m-bits, one for each memory's word. If the input data of the input register get compared with the key
in the m registers, and we get a match, then that particular bit is set in the select register. The function
of the output register is to contain the data word that got matched retrieved from the associative
memory.

Relationship between the memory array and the external registers in associative memory

Following is the diagram showing the relationship between the memory array and external registers in
associative memory:
 These are the cells marked by the letter C in the array with two subscripts. The first subscripts
provide the word number, and the second one depicts the bit's position in the world. So, cell Cij is the
cell for bit j in word i. Bit Ai in the argument register got compared with every bit in column j of the
array provided that Ki = 1. This has been done for every column j = 1, 2, . . . , n. If one match occurs
between every unmasked bit of the argument and the bits in word i, the corresponding bit M1 in the
match register is set to 1. If one or more unmasked bits of the argument and the word do not match,
M1 is cleared to 0.

Virtual Memory

Virtual memory is a segment of volatile memory generated on the storage drive for a limited time.

Programmers discern a larger memory which is allocated on the disk this memory is referred
to as virtual memory. A programmer needs a huge virtual space to develop his or her program or
software.

Program or a processor references a data space which is independent of available physical

memory space. The address issued by a processor is called a virtual address.

The virtual address can be translated into the physical address by a combination of hardware
and software components.

If a virtual address is a part of the program in the physical memory then it can be accessed
immediately and if the address is not in the main memory then its content will be brought into the
main memory before it can be used.

To improve the performance hardware are added to the system, these hardware units are
known as Memory Management Unit (MMU).
 In the paging system, page table helps us to find the physical address form virtual address
since the virtual address space is used to develop a process. So the work of the MMU is to translate
the virtual address to physical address.