BITS Pilani

presentation
BITS Pilani Rahul Kumar, Ph.D.
Electrical & Electronics Engineering
Pilani Campus
 BITS Pilani
Pilani Campus

Physics and Modeling of Microelectronic Devices ,

MEL ZG631
Lecture No. 18 (MOSFET)
Introduction & Outline

• Roadblocks for practical implementation of MOSFET: Lack of understanding and

control of insulator/semiconductor system.

• At bell lab in 1948, BJT was invented accidentally in effort to make MOSFET.

• 1960s: First commercial MOSFET appeared.

• Most Extensively used SSD: several advantage over BJT for digital circuits.
➢ Simpler fab technology, easier to build in dense arrays, consume less power.

• Widely used in memory and microprocessors.

• Miniaturization:

• Scaling: Various scaling rules are there but scaling trends had been more influenced
by technology limitations and device functionalities.

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Miniaturization

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4
Basic MOSFET Behavior

• Two types: NMOSFET & PMOSFET.

• S & D regions are disconnected electrically in absence of inversion layer.
• Enhancement mode (E-mode) & Depletion mode (D-mode) MOSFETS

Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
MEL G631, MOSFET 5 BITS Pilani, Pilani Campus
MOSFET Symbols

• Analog circuits: Voltage-controlled resistor; Digital circuits: ON/OFF Switch.

Electrical symbols for MOSFETs: (a) p-channel enhancement, (b) p-channel depletion,
(c) n-channel enhancement, (d) n-channel depletion devices.

Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
MEL G631, MOSFET 6 BITS Pilani, Pilani Campus
Long-Channel MOSFET Eqn

𝑾 𝟏 𝟐
𝑰𝑫 = 𝝁𝒏 𝑪𝒐𝒙 [ 𝑽𝑮 − 𝑽𝑻 𝑽𝑫 − 𝑽𝑫 ]
𝑳 𝟐 7
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
MEL G631, MOSFET BITS Pilani, Pilani Campus
Output Characteristics

𝑾 𝟏
𝑰𝑫 = 𝝁𝒏 𝑪𝒐𝒙 [ 𝑽𝑮 − 𝑽𝑻 − 𝑽𝑫 𝑽𝑫
𝑳 𝟐
𝑾
𝑾 𝟏 𝟐 𝑰𝑫 = 𝝁𝒏 𝑪𝒐𝒙 𝑽 𝑮 − 𝑽𝑻 𝟐
𝑰𝑫 = 𝝁𝒏 𝑪𝒐𝒙 [ 𝑽𝑮 − 𝑽𝑻 𝑽𝑫 − 𝑽𝑫 ] 𝟐𝑳
𝑳 𝟐 8
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
MEL G631, MOSFET BITS Pilani, Pilani Campus
Beyond Pinch off

• In pinch-off region, current is determined by the rate at which carriers

are delivered to the pinch-off region.

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Water Analogy

Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
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Channel Length Modulation

• Basic MOSFET equation predict with sufficient accuracy for long-

channel devices.
• Channel length modulation: current does not stay constant beyond
pinch-off, but increases linearly with VD.

𝑾 𝟐
𝑽𝑫
𝑰𝑫 = 𝝁𝒏 𝑪𝒐𝒙 𝑽𝑮 − 𝑽𝑻 (𝟏 + )
𝟐𝑳 𝑽𝑨

Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
MEL G631, MOSFET 11 BITS Pilani, Pilani Campus
Body Bias Effect

• Influence of VSB on ID. 𝑽𝑩 = 𝟎, 𝑽𝑺 = 𝑽𝑫 = 𝟎 𝑽𝑩 = −𝟏𝑽, 𝑽𝑺 = 𝑽𝑫 = 𝟎

1
𝑉𝑇 = 𝑉𝐹𝐵 + 2 Φ𝑝 + 2𝜖𝑠 𝑞𝑁𝑎 (2 Φ𝑝 )
𝐶𝑜𝑥

𝟐𝝐𝒔 𝒒𝑵𝒂
∆𝑽𝑻 = ( 𝟐 𝜱𝒑 + 𝑽𝑺𝑩 − 𝟐 𝜱𝒑 )
𝑪𝒐𝒙

𝟐𝝐𝒔 𝒒𝑵𝒂 Body-bias coefficient, unit: V-1.

𝜸=
𝑪𝒐𝒙
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
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Bulk Charge Effect

• Assumption: Qd is constant along the channel.

• V(y) increases from S to D, hence Qd also increases along the channel.

𝑄𝑑 𝑦 = 𝑞𝑁𝑎 𝑥𝑑 = 2𝜖𝑠 𝑞𝑁𝑎 (2 Φ𝑝 + 𝑉(𝑦) − 𝑉𝐵 )

𝑄𝑛 (𝑦) = −𝐶𝑜𝑥 𝑉𝐺 − 𝑉𝐹𝐵 − 2 Φ𝑝 − 𝑉(𝑦) + 2𝜖𝑠 𝑞𝑁𝑎 (2 Φ𝑝 + 𝑉(𝑦) − 𝑉𝐵 )

𝑾 𝜶
𝑰𝑫 = 𝝁𝒏 𝑪𝒐𝒙 [ 𝑽𝑮 − 𝑽𝑻 − 𝑽𝑫𝑺 𝑽𝑫𝑺
𝑳 𝟐
𝑾 𝟐
𝑰𝑫 = 𝝁𝒏 𝑪𝒐𝒙 𝑽𝑮 − 𝑽𝑻
𝟐𝜶𝑳
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Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
MEL G631, MOSFET BITS Pilani, Pilani Campus
VT Adjustment by Implantation

• VT can be adjusted by light channel implantation.

• Two special cases :
– Implantation depth is greater than depletion width.
– Implantation is contained within the depletion region.

2𝜖𝑠 ( Φ𝑝 +Φ𝑆 ) 𝑁𝑎𝑖

• 𝑥𝑑 = − 𝑥𝑖2
𝑞𝑁𝑎 𝑁𝑎
𝑞𝑁′ 1
• 𝑉𝑇 = 𝑉𝐹𝐵 + 𝑉𝑆 + Φ𝑝 + Φ𝑝𝑠 + 𝐶 +𝐶 2𝜖𝑠 𝑞𝑁𝑎 ( Φ𝑝 + Φ𝑝𝑠 + 𝑉𝑆𝐵 ) − 𝑞 2 𝑥𝑖 𝑁𝑎 𝑁′
𝑜𝑥 𝑜𝑥
– 𝑉𝑆 + Φ𝑝 + Φ𝑝𝑠 instead of 𝑉𝑆 + 2 Φ𝑝 : Voltage drop across DR
𝑞𝑁′
– : VT depends linearly on dose
𝐶𝑜𝑥
– Depletion charge term altered by 𝑞 2 𝑥𝑖 𝑁𝑎 𝑁′ in square root.
𝒒𝑵′
• Effectively 𝑉𝑇 = 𝑉𝐹𝐵 + 𝑉𝑆 + 2 Φ𝑝 + 𝑪
𝒐𝒙

Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
MEL G631, MOSFET 14 BITS Pilani, Pilani Campus
VT Adjustment by Implantation

Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
MEL G631, MOSFET 15 BITS Pilani, Pilani Campus
Depletion Mode MOSFET

• Depletion Mode: ON at zero VGS.

• NMOS inverter with depletion load.
• For n-channel MOSFET with implanted
𝒒𝑵′
donors: ∆𝑉𝑇𝑛 = −
𝑪𝒐𝒙
• For p-channel MOSFET with implanted
𝒒𝑵′
acceptors: ∆𝑉𝑇𝑝 =
𝑪𝒐𝒙

Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
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Subthreshold Conduction

• Subthreshold Current: Small ID when VG is smaller than VT.

• For VG<VT: mobile charge and ID changes exponentially with VG.

• Subthreshold current flow mechanism is somewhat similar to current

flow in BJT.

• At VG<(VT-0.2V), ID begins to
vary exponentially with VG.

𝒒𝑽𝑮𝑺
𝑰𝑫 ≈ 𝑰𝑫𝟎 𝒆𝒙𝒑
𝒏𝒌𝑻

Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
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Subthreshold Conduction

• Relation between VG and φS.

𝑑Φ𝑆 1 1
𝜂= = =
𝑑𝑉𝐺𝑆 1 + 𝐶𝑑ൗ 𝑛
𝐶 𝑜𝑥

• Inverse subthreshold slope (often simply 𝒒𝑽𝑮𝑺

𝑰𝑫 ≈ 𝑰𝑫𝟎 𝒆𝒙𝒑
called subthreshold slope): S 𝒏𝒌𝑻

𝒌𝑻 𝑪𝒅
𝑺= 𝐥𝐧 𝟏𝟎 𝟏 + = 𝟔𝟎𝒏 𝒎𝑽/𝒅𝒆𝒄𝒂𝒅𝒆
𝒒 𝑪𝒐𝒙
𝒌𝑻 𝑪𝒊𝒕 + 𝑪𝒅 In case of interface trap charges
𝑺= 𝐥𝐧 𝟏𝟎 𝟏 + where Cit = qDit.
𝒒 𝑪𝒐𝒙

• Minimum achievable value of S is 60 mV/decade. Value of S

determines the VG needed to ensure OFF condition.
Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
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Small Signal Circuit Model

• CGS & CGD: Intrinsic to MOSFET.

• CRS & CRD: Overlap Capacitance.

• CTS & CTD: Depletion Capacitance.

𝜕𝐼𝐷
𝑔𝑚 =
𝜕𝑉𝐺

In linear region:
𝑾
𝑔𝑚 = 𝝁𝒏 𝑪𝒐𝒙 𝑽𝑫𝑺
𝑳
In saturation region:
𝑾 𝟐𝑰𝑫𝒔𝒂𝒕
𝑔𝑚𝑠𝑎𝑡 = 𝝁𝒏 𝑪𝒐𝒙 𝑽𝑮 − 𝑽𝑻 =
𝑳 𝑽𝑮 − 𝑽𝑻

Device Electronics for Integrated Circuits, 3/E by Richard S. Muller and Theodore I. Kamins
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Short-Channel Effects

• Source/drain charge sharing

• Drain-induced barrier lowering
• Subsurface punchthrough
• Mobility Degradation
• Velocity saturation

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 Source/Drain Charge Sharing

• For short-channel devices, VT reduces exponentially with decreasing L.

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Drain-induced barrier lowering

• DIBL: Influence of VD on ΦS. VD reducing source injection barrier.

• Subthreshold current is most sensitive to DIBL. Subthreshold current increases with
VD due to DIBL.

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Subsurface Punchthrough

• Like DIBL, this also reduce source injection

barrier.
• Subsurface Punchthrough occurs away from
surface.
• Both effects leads to variable and high leakage
currents in normally-off devices.
• Remedies: Increasing substrate doping,
thinning SiO2, reducing xj.

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Mobility Degradation

• Channel carriers moves close to the interface, where mobility gets affected by
interface scattering (dependent on vertical electric field).
• It affect both short and long channel devices. However, it is particularly severe in
short-channel devices because of high vertical electric field.

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Velocity Saturation

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End of Module 7

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