Sinhgad Technical Education Society’s
SINHGAD COLLEGE OF ENGINEERING, PUNE-
Department of Computer Engineering
DELD Question bank
UNIT -I: Minimization Techniques
1. Using graphical method obtain the minimal expression for
F = ∑m (6,7,8,9) +d (10,11,12,13,14, l5) (06)
2. Minimize the following boolean expression using K-map and realize it using basic gates.
Y= ∑m(1,3,5,9,11,13) (04)
3. Design the combinational circuit to produce the 2 's complement of a 4 bit binary number as a input
(08)
4. Use a multiplexer to design the logic function F = A xor B xor C. (08)
5. Minimize the following expression using K -map. (08
) Y=A 'BC'D+A'B 'CD+AB 'CD'+ABCD+A'B 'C'D'+AB'CD
6. Why gray code is used in labeling the cells of K-map? [Dec 05/ May 10] (4)
7. Minimize the following expression using K-map and implement using logic gates:
Y=∑m(4, 5,6,7,12,1314,15) [May 18] (4)
8. Using K-map calculate minimized expression for following function and implement it by using basic
gates
F( A, B, C, D) = ∑m (0,2,4,8,11,15) +d (3,10,12,13) [Dec 18] (6)
8. Minimize the function using K-map implement using NAND gates only
F(A,B,C,D)=∑m (0,1,3,5,6,9,1 1,1 3) (08)
9. Minimize the function using K-map implement using NAND gates only (08)
F(A,B,C,D)=∑m (0,1,3,5,6,9,1 1,1 3)
10. Minimize the function using K-map implement using NAND gates only (08)
F(A,B,C,D)=∑m (1,2,3,5,7,8,9,11,14)
Sinhgad Technical Education Society’s
SINHGAD COLLEGE OF ENGINEERING, PUNE-
Department of Computer Engineering
UNIT II: Combinational circuits
1. Design full adder using logic gates. [Dec 17] (4)
2. Design full adder using two half adders. [May 18] (4)
3. Design a BCD to excess -3 code converter using decoder and some logic gates. (08)
4. Design 4-bit binary to gray code converter and implement using logic gates. [Dec 11] (8)
5. Design 4-bit excess-3 to BCD code converter and implement using logic gates. [May 12] (10)
6. Design a circuit to convert gray code to binary code. [Dec 7] (6)
7. Design 3-bit binary to gray code converter. [May 17/ Dec 17/ May 19] (6)
8. Explain look ahead carry generator and advantages of the same. [Dec 6/ Dec 7] (4)
9. Design 4-bit BCD adder using binary adder using binary adder ICs. [May 12](08)
10. Design BCD subtractor using binary adder. (08)
11. Design one bit magnitude comparator. [Dec 16] (4)
12. Design 2-bit comparator using K-map and implement it. [Dec 12] (8)
13. Write short notes on look ahead carry (06)
14. Design the following function using single 4:1 MUX and logic gates.
F(A,B,C,D)= ∑m(0,1,5,9,10,15) (08)
15. What is MUX? Draw and explain 4:1 multiplexer. [May 10] (6)
16. Implement a 16:1 multiplexer using 4:1 multiplexer. [May 6] (4)
17. Implement full adder using 8:1 MUX. [Dec 19] (6)
18. Implement the full subtractor using a 1:8 demultiplexer. [May 6] (4)
19. Compare the multiplexer and demultiplexer. [Dec 16] (4)
20. State the applications of decoder. [Dec 4/Dec 6] (4)
21. Design 2-bit comparator using logic gates. [Dec 7/10/13] (6)
22. Design 2-bit comparator using suitable decoder. (08)
23. Design the combinational circuit to generate an odd parity bit for a 4-bit input. (08)
24. Design even parity generator circuit for 4-bit input using multiplexer. [Dec 10]
(6)
Sinhgad Technical Education Society’s
SINHGAD COLLEGE OF ENGINEERING, PUNE-
Department of Computer Engineering
UNIT III: Sequential Logic Design
1. Write short note on one-bit memory cell. [May 10] (4)
2. Draw and explain SR flip-flop using NAND gates. [April 2013] (08)
3. Justify names delay for D flip-flop giving truth table and waveforms.
4. Draw and explain the diagram of JK flip-flop using NAND gates and explain how race around
condition is avoided? [Oct 2013]
(06)
5. Explain Race around condition a n d also state the remedial action for it.
[April 2012] (10)
6. Draw and explain operation of JK flip-flop using logic gates with waveforms.
7. Design and implement the following counter-states using JK flip-flop and avoid the lockout
condition: 0-2-4-6-7-0. [April 2013] (08)
8. Explain operation of a master-slave JK flip-flop. [Dec 19](6)
9. What is the use of PRESET and CLEAR terminals in filp-flop? Write a short note on JK master slave
filp-flop. [October 2012] (08)
10. Convert: (i) JK FF to SR FF (ii) T FF to SR FF. [October 2012] (08)
11. Convert D to T flip-flop and vice versa [April 2013] (08)
12. With truth table, K-map and logic diagram explain how SR F/F converted to D F/F. [Dec 18] (6)
13. Explain how JK F/F is converted to T F/F? [may 10] (4)
14. Convert: i) SR F/F to T F/F ii) D FF to JK FF
15. Perform the following conversion: (i) JK FF to D FF (ii) SR FF to JK FF. [April 2012] (08)
16. Define the following terms as applied to flip-flop: i)set up time ii)Hold time iii) Propagation delay
17. Which are the various methods of triggering the flip-flop. Explain with its symbol. [April 2012] (08)
18. What is clock skew and clock jittering in synchronous circuits? [May 19] (4)
19. What is shift register? State the types and explain any one of them. State applications of shift registar.
[May 18] (4)
20. Explain the following shift registers: (i) Serial-in serial-out shift register (ii) Parallel-in parallel-out
shift register. [October 2012] (08)
21. Draw circuit diagram and explain 4-bit Universal shift register. [April 2012] (08)
22. Explain how shift registers are used as: (i) Ring Counter [April 2012] (08)
23. With the help of a neat circuit diagram, explain the working of ring counter. If initial data loaded is
(0001 )2, then draw the timing diagram for same. [October 2012] (08)
24. Design pulse train generator using shift register to generate the following pulse:
……10110…… [October 2012/Oct 2013] (08)
25. Design pulse train generator using shift register to generate the following pulse:
……1000 110…… [April 2012] (10)
26. Design a 3-bit binary up/down ripple counter. Draw the timing diagram. [May 07/Dec 08] (6)
27. Design and implement synchronous BCD counter using T flip-flops. [May 06/Dec 09] (8)
28. Design and explain a 4-bit binary UP/DOWN ripple counter with a control for UP/DOWN
Sinhgad Technical Education Society’s
SINHGAD COLLEGE OF ENGINEERING, PUNE-
41
Department of Electronics and Telecommunication
counting. Engineering [October 2012] (08)
29. Design and implement 3-bit synchronous counter using JK FF. [April 2012] (08)
30. Design the sequence generator using JK flip-flop: 0-2-4-6-0 [Dec 19] (6)
31. Design synchronous counter which will go through the following steps JK FF: 0-2-5-4-7- 3.
[April 2013/ April 2012]
(08)
UNIT-IV: Algorithmic State Machines and Digital Logic Families
1) Draw the state diagram, state table, and ASM chart for a 2 -it binary counter
having one enable line E such that E=l counting enabled, and
E=0countingdisabled.
2) What is an ASM Chart? Name the elements of an ASM chart and define each
of them.
3) Draw the ASM chart for a 2-bit UP-DOWN counter with mode select line M
such that :M= 0 (UP Counting), M=1(DOWN Counting).
4) What is an ASM Chart? Name the elements of an ASM chart and define each
of them.
5) What is ASM chart? Design ASM chart for 3-Bit gray code sequence with up-
down conditions.
6) What is ASM Chart? State & Explain basic components of ASM chart. Also
explain the salient features of ASM chart.
7) Draw and explain various notations use d in ASM charts
8) ComparebetweenFSMandASM
9) With the help of an eat diagram, explain the working of two-input TTL NAND
gate. 10)What is the advantage of open collector output? Justify your answer with
suitable circuit.
11) Compare TTL and CMOS logic family.
12)What is logic family? Give the classification of logic family and also write
Sinhgad Technical Education Society’s
SINHGAD COLLEGE OF ENGINEERING, PUNE-
41
important characteristics of CMOS.
Department of Electronics and Telecommunication
Engineering
13)Explain TTL open collector
14)Define the following terms and mention the standard values for TTL logic Family i)Fan-
out ii) Power Dissipation iii) Propagation Delay. iv)Noise margin v)Figure of Merit
UNIT V: Programmable Logic Devices
1) Implement following Boolean function using PAL
F1=Σm(0,2,4,6,8,12)
F2=Σm(2,3,8,9,12,13)
F3=Σm(l,3,4,6,9,11,12,14,15)
2) Draw a block diagram of the PLA device and explain.
3) Implement BCD to Excess-3 code converter using PAL.
4) What is the difference between PAL and PLA?
5) Draw and explain the general structure of PLA.
6) Implement following Boolean function using PAL F(A,B,C,D)=Σm(0,1,3,15)
7) Implement BCD to Ex-3 code converter using PAL.
8) What is the difference between PAL and PLA?
9) Implement the following Boolean function using PAL. F1Σm(0,3,5,7,9,10,11,14,15) F2Σm(2,3,12,14)
10)Draw block diagram of PLA device and explain in detail.
11)Implement gray to binary code using PLA.
12)Implement the following using PROM A(X,Y,Z)=∑m(5,6,7) B(X,Y,Z)=∑m(3,5,6,7)
13)Implement the following Boolean functions using PAL X1(A,B,C,D)Σm(0,2,6,7,8,9,12,13)
X2(A,B,C,D)Σm(3,6,7,11,14,15)