Integrated Circuit and Digital system

Design

Associate Professor. Truong Ngoc Son

Email: sontn@[Link]
Mobile: 0931.085.929
Department of Computer and Communication Engineering
Faculty of Electrical and Electronics Engineering
Course Materials
 Lecture notes
Online lecture (youtube)
 Textbook
 Software
FPGA Design and Simulation
Xilinx ISE Design Suite
ModelSim
Others
Truong Ngoc Son, Ph.D - Department of Computer and Communication Engineering
Course Participation and Requirements
 Attendance Policy
 Regular attendance is mandatory, with a minimum requirement of 80%.
 Examination and Assignment Guidelines
 Participate in all examinations, including online and paper-based tests
 Ensure all homework is submitted on time

Truong Ngoc Son, Ph.D - Department of Computer and Communication Engineering

A Brief History of integrated circuit
1. Early Beginnings: Pre-Integrated Circuits (Before 1958)
Before the invention of the integrated circuit, electronic devices relied on
discrete components like resistors, capacitors, and transistors. These
components were manually assembled onto circuit boards, which made
devices bulky, less reliable, and more expensive to produce
2. The Birth of the Integrated Circuit (1958-1959)
1958: Jack Kilby, an engineer at Texas Instruments, developed the first
working integrated circuit. Kilby’s invention was revolutionary; it consisted
of a single piece of germanium semiconductor that integrated a transistor,
several resistors, and a capacitor, all on one chip. His work laid the
foundation for the miniaturization of electronic circuits. Kilby was awarded
the Nobel Prize in Physics in 2000 for his invention

Chapter 1: introduction to VLSI

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 A Brief History of integrated circuit
1959: Robert Noyce, a co-founder of Fairchild Semiconductor, independently
invented a more practical version of the integrated circuit using silicon as the
semiconductor material. Noyce's approach used a planar process, which involved
layering and etching on the silicon wafer, allowing for more efficient production.
This method became the standard for IC fabrication and was more easily scalable
for mass production.

Chapter 1: introduction to VLSI

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 A Brief History of integrated circuit
3. The Growth of Integrated Circuits (1960s-1970s)
1960s: The integrated circuit began to gain traction as companies like Texas
Instruments and Fairchild Semiconductor started mass-producing ICs. The number
of transistors that could be placed on a single chip increased steadily, a trend that
was famously captured by Gordon Moore’s 1965 prediction, known as Moore’s
Law. Moore, another co-founder of Intel, predicted that the number of transistors
on a chip would double approximately every 18-24 months, a prediction that held
true for several decades.

Chapter 1: introduction to VLSI

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 A Brief History of integrated circuit
3. The Growth of Integrated Circuits (1960s-1970s)
1968: Intel was founded by Robert Noyce and Gordon Moore. The company
quickly became a leader in the IC industry
1971: Intel introduced the first commercially available microprocessor, the
Intel 4004. It was a 4-bit processor with 2,300 transistors on a single chip,
capable of performing basic arithmetic and control tasks. The introduction of
the microprocessor marked the beginning of a new era, leading to the
development of personal computers.

Chapter 1: introduction to VLSI

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 A Brief History of integrated circuit
4. Advances in IC Technology (1980s-1990s)
1980s: The industry saw the adoption of CMOS (Complementary Metal-
Oxide-Semiconductor) technology, which became the dominant technology
for manufacturing ICs due to its low power consumption and high noise
immunity. This period also witnessed the rise of microprocessors and
microcontrollers, which became essential components in consumer
electronics, computers, and industrial applications.
1989: The Pentium microprocessor was introduced by Intel, representing a
significant leap in processing power and marking the beginning of modern
computing.

Chapter 1: introduction to VLSI

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 A Brief History of integrated circuit
1990s: This decade saw the rise of complex ICs with millions of transistors,
capable of performing sophisticated tasks. The development of ASICs
(Application-Specific Integrated Circuits) allowed for customization of ICs
for specific applications, leading to more efficient and specialized devices.

Chapter 1: introduction to VLSI

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 A Brief History of integrated circuit
5. Modern Era of Integrated Circuits (2000s-Present)
2000s: The industry witnessed exponential growth in IC complexity and performance.
The number of transistors on a single chip grew into the billions. The introduction of
multi-core processors allowed for parallel processing, significantly improving
computational power. The size of transistors continued to shrink, with manufacturing
processes moving from 130nm to 45nm, 32nm, and smaller.
2010s: FinFET (Fin Field-Effect Transistor) technology was introduced, allowing
for further miniaturization and energy efficiency improvements. This period
also saw the rise of System-on-Chip (SoC) designs, integrating various
functions such as processing, memory, and input/output on a single chip,
making devices like smartphones and tablets more powerful and energy-
efficient.

Chapter 1: introduction to VLSI

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 A Brief History of integrated circuit
5. Modern Era of Integrated Circuits (2000s-Present)
2020s: The semiconductor industry continues to push the boundaries with
advanced manufacturing nodes like 5nm and 3nm processes. Innovations in
chip design, such as 3D stacking and chiplet architectures, are helping to
overcome the limitations of traditional scaling. The demand for high-
performance computing, driven by artificial intelligence, data centers, and
edge computing, has pushed the development of specialized ICs such as
GPUs (Graphics Processing Units) and TPUs (Tensor Processing Units).

Chapter 1: introduction to VLSI

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 A Brief History of integrated circuit
6. The Future of Integrated Circuits
The future of ICs is likely to be shaped by several key trends:
Continued miniaturization: As manufacturers continue to shrink the size of
transistors, we are approaching physical limits, leading to the exploration of new
materials and architectures, such as quantum computing and neuromorphic
computing.
Increased integration: More functions will be integrated into single chips, leading to
even more compact and energy-efficient devices.
New materials and processes: Research into materials like graphene and carbon
nanotubes, as well as advanced lithography techniques, could drive the next wave of
IC innovation.

Chapter 1: introduction to VLSI

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Integrated circuit Design
VLSI Design Flow
Integrated circuit Design
Integrated circuit Design
Integrated circuit Design
 How to go from Idea/Algorithm to the actual hardware

module RippleCarryAdderII (Cin, X, Y, S, Cout);

parameter n = 4; input Cin; input [n-1:0] X, Y; output [n-1:0] S;
wire [n-1:0] C;
Full_Adder stage0 (Cin, X[0], Y[0], S[0], C[1]);
Full_Adder stage1 (C[1], X[1], Y[1], S[1], C[2]);
Full_Adder stage2 (C[2], X[2], Y[2], S[2], C[3]);
Full_Adder stage3 (.Cout(Cout), .Cin(C[3]), .x(X[3]), .y(Y[3]), .S(S[3]));
endmodule

ASIC FPGA
 Integrated circuit Design

Standard
Specifications
Cells

Pre-Layout Post-Layout
Simulation Yes Timing Yes Back Yes
RTL Coding Synthesis APR Timing Logic
Pass? Alanysis Annotation Alanysis verification
Pass? Pass?
NO NO
Test Bench Timing NO
Constraints
Tapeout

1. HDL Coding 2. Simulation 3. Synthesis 4. Placement & routing 5. Timing Analysis & Verification

Front-End Back-End
 In this course we learn all the above steps in detail for
 ASIC Platform
 FPGA Platform
 Course Introduction:
 PLDs & FPGA Architectures
 FPGA Technologies
 SPLDs (PAL and PLA architectures)
 Commercial CPLD Architectures
 SRAM/LUT Based FPGAs
 Anti‐fuse/MUX Based FPGAs
 Flash Based FPGAs
 FPGA Architectures
 Heterogeneous/Homogeneous FPGAs
 Fine‐grained, coarse‐grained and platform FPGAs
 FPGA Elements & Design Trade‐offs
 Logic Cells Common Architectures
 Programmable Routing Channels Design
 I/O & Pad architectures
 Commercial FPGAs
 Altera (FLEX 10K, Stratix III) , Xilinx (XC4000, Virtex II,4,5), Actel (Act3, Axcelerator)
 Course Introduction:
 Hardware Description Language
 Verilog Fundamentals
 Language Fundamentals
 Modeling Combinational/Sequential Logic Circuits
 Modeling Finite State Machines
 Verilog for Verification
 Verification/Simulation techniques with test‐benches
 Verilog for synthesis
 Verilog Styles for Synthesis
 Architectural techniques for high‐speed designs
o Parallel proc., pipelining, retiming, …
 Implementations of common operations
o Complex multiplication, division, complex norm, CORDIC
 Fundamentals of fixed‐point realization
 Course Introduction:
 Advanced Digital System Design with Xilinx FPGAs
 Design Creation
 Synthesize
 Simulation
 Constraints Entry
 Implementation
 Implementation Results Analysis – Timing Analysis
 Implementation Results Analysis – Power Analysis
 Implementation Results Improvement
 Device Configuration and Programming
 Design Debugging
 Course Introduction:
 Power Dissipation
 Power Dissipation concept
 Dynamic Power
 Static Power
 Challenges
 Course Introduction:
 Prerequisites:
 Only Digital Logic!
 All the skills you need will be taught in the course

 Softwares you should learn:

 Altera Quartus
 Xilinx ISE
 Mentor Graphics Modelsim
 TCL Scripting
 Synopsys Design Compiler
 Cadence SOC Encounter
 Course Introduction:
 Implementation Platform:
 Altera DE2 Board
 Atlys Xilinx Board

You will do several practical assignments including Verilog Coding,

FPGA implementation and testing based on the DE2 and Atlys Boards
Course Outline
• Course Outline
• Introduction to ASIC/FPGA IC Design
 Integrated Circuits (IC) History
 Digital Design vs. Analog Design
 ASIC vs. FPGA
 Design Abstraction and Metrics
 CMOS as the building block of Digital ASICs
 Layout
 Packaging

20
Integrated Circuit (IC) History

Discrete Circuits Integrated Circuits

 Limited applications  Many applications
 Power hungry  Low power
 Large area  Small area
 Moderate speed  High speed
Integrated Circuits (IC) History
1940 1945 1947 1951 1955 1957 1958 1959 1961 1962 1968 1970 1971

Ohl built the PN Junction: 1940

Shockley Lab was established: 1945

Brattain and Bardeen invented the first transistor (US Patent 2524035): 1947

A picture of the filed patent

Integrated Circuits (IC) History
1940 1945 1947 1951 1955 1957 1958 1959 1961 1962 1968 1970 1971

 1951: Shockley invented the first junction transistor for mass production
 (US Patent
2623105)

A picture of the filed patent

 IC History
1971 ……………………………………………………………………………………… 2010

K 1 Billion Transistors
1,000,000
Projected
100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086

1
1975 1980 1985 1990 1995 2000 2005 2010
Source: Intel

Number of Transistors doubled every 18 months!

(Moore’s Law)
Scaling still continues…
IC History
1971 ………………………………………………..……………………… 2015

 Amazingly visionary – million transistors/chip barrier was

crossed in the 1980’s.
 2300 transistors, 1 MHz clock (Intel 4004) - 1971
 16 Million transistors (Ultra Sparc III)
 42 Million, 2 GHz clock (Intel P4) - 2001 Integration Levels
 140 Million transistor (HP PA-8500) SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
IC History
Early Designs Advanced Designs

(1971) (2017)
 1000 Transistors (1 MHz)  Intel Corei7 -7700K(~ 4.2 GHz)
 Process: 10um  Process: 14nm
 Fully Handcrafted  Fully Automated
 Manual Layout  Automated Layout
 Individually Optimized  Hierarchical Design
Digital Very Large Scale Integration (VLSI) (Not Analog!)
Technology Direction

Year 1999 2002 2005 2008 2011 2014 2017

Feature size (nm) 180 130 100 70 50 35 14
M trans/cm2 7 14-26 47 115 284 701 900
Chip size (mm2) 170 170-214 235 269 308 354 460
Signal pins/chip 768 1024 1024 1280 1408 1472 ~1600
Clock rate (MHz) 600 800 1100 1400 1800 2200 4200
Wiring levels 6-7 7-8 8-9 9 9-10 10 10
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6 0.8
Why Scaling?

 Technology shrinks by ~0.7 per generation

 With every generation can integrate 2x more functions on a chip; chip cost
does not increase significantly

 Cost of a function decreases by 2x

 But …
 How to design chips with more and more functions?
 Design engineering population does not double every two years…
 Hence, a need for more efficient design methods
 Exploit different levels of abstraction
 IC Manufacturing Process

Silicon Wafer Patterned Silicon

Wafer

Silicon Cylinder

Circuit Core
Packaged Die Final Test
Unpackaged Die
 IC Manufacturing Process

Circuit core
Cavity
Die Bond wire
Package Trace
Patterned Silicon
PAD Wafer

Packaged Die
Lead

Circuit Core
 Digital vs. Analog Design : Analog Circuits
 Transmitter: Analog/RF

Voice
Modulator

Power
Amplifier
High-frequency
carrier

 Receiver:

Down
Demodulator
Converter
Low-Noise Audio
Amplifier Amplifier

Analog/RF
 Digital vs. Analog Design : Analog-Digital Circuit
 Transmitter:
Digital (Baseband) Analog/RF Front-end

Voice Voice Coding Pulse

ADC Modulator
Compression Interleaving shaping
Power
Amplifier

 Receiver: This Course

Down
ADC Demodulator Equalizer
Converter
Low-Noise
Amplifier

Voice De-interleaving
DAC
Decompression Decoding
Audio
Amplifier
Digital (Baseband)
 Digital vs. Analog Design
 Digital Design Advantages:
More noise reliability
 Allows signal decoding and amplification
Allows coding to achieve higher performance
Allows encryption for higher security
Provides a perfect vehicle for digital signal processing
Allows modular chip design
Enjoys the benefit of advanced sophisticated CAD tools
Can be verified on programmable devices before tape-out
Provides a platform to merge multiple networks such as
telephone, terrestrial TV and computer networks.
Digital vs. Analog Design
 Digital System Design Steps
 Specific application (e.g., Digital Image Processor)
 As opposed to a general microprocessor
 Design requirements
 Images to be processed per second
 Required processing
RTL
 Interfacing
 Dimension, power, price,…
 General design and simulation
 RTL level design to verify and simulate the design

 Higher levels: Few complicated blocks

 Lower levels: Many simple blocks

 To avoid any problem in lower levels, many simulations

in higher levels
Design Flow
IC Fabrication
Idea
Wafer
Architecture Design (hundreds of dies)

Sawing & Packaging

Block
diagram Final chips

Circuit & Layout Design Testing

customers
Layout

Bad chips Good chips

Digital Systems Components
 Printed Circuit Board (PCB)
 Embedded Software
 Microprocessor (general Purpose)
 Microcontroller
 Digital Signal Processor (DSP)
 Programmable Logic Devices
 Simple Programmable Logic Device (SPLD)
 Complex Programmable Logic Device (CPLD)
 Field Programmable Gate Arrays (FPGAs)
 Application Specific Integrated Circuits (ASICs)
Digital Systems Components
DSPs

 Easy to program (usually standard C)

 Very efficient for complex sequential math-intensive tasks

 Fixed datapath-width. Ex: 24-bit adder, is not efficient for 5-bit addition

 Limited resources
Digital Systems Components
Microprocessors/Microcontrollers

 Lessens the risk of system development by reducing design complexity

 Fixed hardware so more effort on developing a good code

 Fixed HW not suitable for high level of parallelism/computations

 Many sequential nature
 One order of magnitude less performance than to-date FPGA/ASICs
Digital Systems Implementation Platforms

Digital IC

PLDs ASIC

SPLD CPLD FPGA Semi-Custom Full-Custom

PLA PAL Standard cell Gate Array

This course
Technology Timeline

The white portions of the timeline bars indicate that although early incarnations of these technologies
may have been available, they weren’t enthusiastically received by the engineers working in the
trenches during this period. For example, although Xilinx introduced the world’s first FPGA as early as
1984, design engineers didn’t really start using it until the early 1990s.
Course Outline
• Course Outline
• Introduction to ASIC/FPGA IC Design
 Integrated Circuits (IC) History
 Digital Design vs. Analog Design
 ASIC vs. FPGA
 Design Abstraction and Metrics
 CMOS as the building block of Digital ASICs
 Layout
 Packaging

49
 FPGA vs. ASIC

 Field Programmable Gate Array (FPGA) Advantages:

 Fast programming and testing time by the end user (instant turn-around)
 Excellent for prototyping
 Easy to migrate from prototype to the final design
 Can be re-used for other designs
 Cheaper (in small volumes) lower start-up costs
 Re-programmable
 Lower financial risk
 Ease of design changes/modifications
 Cheaper design tools
 FPGA vs. ASIC

 FPGA Drawbacks:
 Slower than ASIC (2-3 times slower)
 Power hungry (up to 10 times more dynamic power)
 Use more transistors per logic function
 More area (20 to 35 times more area than a standard cell ASIC)
 FPGA vs. ASIC
 Application Specific Integrated Circuit (ASIC) Advantages:
 Faster
 Lower power
 Cheaper (if manufactured in large volumes)
 Use less transistors per logic function

 ASIC Drawbacks:
 Implements a particular design (not programmable)
 Takes several months to fabricate (long turn-around)
 More expensive design tools
 Very expensive engineering/mask cost for the first successful design
 ASIC Mask Generation Cost

 The ASIC is accompanied by increasing nonrecurrent engineering (NRE) costs which meant
that there was an increased emphasis on “right first time” design.

 These NRE costs is largely due to the cost of generating masks as it is becoming more
expensive to generate the masks for finer geometries needed by shrinking silicon
technology dimensions.
Implementation Approaches (ASIC vs. FPGA)

ASIC FPGA
Application Specific Field Programmable
Integrated Circuit Gate Array
 Bought off the shelf & reconfigured
 Expensive & time consuming
by the end designers
fabrication in semiconductor
foundry
 No physical layout design
 Designed all the way from
behavioral description to
 Design ends with a bitstream
physical layout
used to configure a device
Implementation Approaches (ASIC vs. FPGA)
ASICs FPGAs

Off-the-shelf
High performance

Low development cost

Low power
Short time to market

Low cost in
high volumes Re-configurability
ASIC vs. FPGA

57
Course Outline
• Course Outline
• Introduction to ASIC/FPGA IC Design
 Integrated Circuits (IC) History
 Digital Design vs. Analog Design
 ASIC vs. FPGA
 Design Abstraction and Metrics
 CMOS as the building block of Digital ASICs
 Layout
 Packaging

57
 Design Abstraction Levels
 Divide-and-Conquer
 Design modules once
SYSTEM
 Instantiate them
thereafter
 Standard Cells MODULE
 Already laid out +
 Avoid re-design GATE
 Same as programming
 Designer cares about module’s: CIRCUIT

 Functionality
 Delay characteristics G
DEVICE

 Area S
n+ n+
D

 NOT:
 How the module was This Course VLSI Course
designed
 Detailed solid-state behavior

57
Design Abstraction Levels
Y-Chart System Level Algorithmic Level
A:=A*B+F
I/O Processor IF(C=TRUE) THEN
A:=A+2*F
ELSE A:=A-1
RAM ROM ENDIF

Register Transfer Level Logic Level

MUX A C Q

Register
Circuit &
L |
Logic D Qn
ROM U
Register Transfer
Algorithmic Circuit Level
Architectural
(System)

57
 Device Metrics
Performance Metrics of a Digital Chip:
 Cost
 NRE (fixed) costs - design effort
 RE (variable) costs - cost of parts, assembly, test
 Speed Single Die
 Delay (ns) → Operating Frequency (MHz)
 Power Dissipation
 Energy to Perform a Function
 Energy per bit (nJ/b)
 Reliability
 Noise immunity
 Noise margin
 Scalability Wafer
 Larger Designs Diameter: 10-30 cm
 Time-to-Market Thickness: 1 mm
 Device Metrics
Performance Metrics of a Digital Chip:
 Cost
 NRE (fixed) costs - design effort
 RE (variable) costs - cost of parts, assembly, test
 Speed Single Die
 Delay (ns) → Operating Frequency (MHz)
 Power Dissipation
 Energy to Perform a Function
 Energy per bit (nJ/b)
 Reliability
 Noise immunity
 Noise margin
 Scalability Wafer
 Larger Designs
 Time-to-Market
 Cost of Integrated Circuits
 NRE (non-recurring engineering) costs
 Fixed cost to produce the design
• Design effort
• Design verification effort
• Mask generation
 Influenced by the design complexity and designer productivity
 More pronounced for small volume products
 RE (Recurring costs) – proportional to the product volume (i.e., Variable)
 Silicon processing
• also proportional to chip area
 Assembly (packaging)
 Test
fixed cost
Cost per IC = variable cost per IC + -----------------
volume
Recurring Costs
variable cost = cost of die + cost of die test + cost of packaging
----------------------------------------------------------------
final test yield
cost of wafer
cost of die = -----------------------------------
dies per wafer × die yield
 × (wafer diameter/2)2  × wafer diameter
Dies per wafer = ----------------------------------  ---------------------------
die area  2 × die area

α depends on the complexity of the

manufacturing process (roughly
proportional to the number of masks)

die yield = (1 + (defects per unit area × die area)/)-

Yield Example

 Example
 Wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2,
  = 3 (measure of manufacturing process complexity)
 252 dies/wafer (remember, wafers round & dies square)
 Die yield of 16%
 252 x 16% = only 40 dies/wafer die yield !

 Die cost is a strong function of the die area

 Proportional to the third or fourth power of the die area

Cost of die = f(die area)4

 Examples of Cost Metrics (1994)

Chip Metal Line Wafer Defects Area Dies Yield Die

layers width cost (mm2) cost
/cm2 /wafer
386DX 2 0.90 $900 1.0 43 360 71% $4
486DX2 3 0.80 $1200 1.0 81 181 54% $12
PowerPC 601 4 0.80 $1700 1.3 121 115 28% $53
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149
Super SPARC 3 0.70 $1700 1.6 256 48 13% $272
Pentium 3 0.80 $1500 1.5 296 40 9% $417

65
 Device Metrics
Performance Metrics of a Digital Chip:
 Cost
 NRE (fixed) costs - design effort
 RE (variable) costs - cost of parts, assembly, test
 Speed Single Die
 Delay (ns) → Operating Frequency (MHz)
 Power Dissipation
 Energy to Perform a Function
 Energy per bit (nJ/b)
 Reliability
 Noise immunity
 Noise margin
 Scalability Wafer
 Larger Designs
 Time-to-Market
Performance

 Frequency of operation: 1/T

 Dependent on the propagation delay of signal through the logic
 Time to get the data out/in of the registers
 Clock uncertainty
 tp is a typical measure (not an accurate one)
 the delay experienced by a signal when passing through a gate
 50% transition points of the input and output waveforms
• Two types LH and HL
• Good for comparison
 Rise time/fall time affects delay
 10% - 90% definitions
Delay Definitions
Vin Vout

Vin
Propagation delay
input 50% tp = (tpHL +tpLH)/2
waveform

t
tpHL tpLH
Vout
90%
output
50% signal slopes
waveform
10%
t
tf tr
 Device Metrics
Performance Metrics of a Digital Chip:
 Cost
 NRE (fixed) costs - design effort
 RE (variable) costs - cost of parts, assembly, test
 Speed Single Die
 Delay (ns) → Operating Frequency (MHz)
 Power Dissipation
 Energy to Perform a Function
 Energy per bit (nJ/b)
 Reliability
 Noise immunity
 Noise margin
 Scalability Wafer
 Larger Designs
 Time-to-Market
Power Consumption

 Peak transient power

 Power line sizing, decoupling, etc. Ppeak = ipeakVsupply =max[p(t)]

 Average power
 Battery current delivery, cooling system

 Static power vs. Dynamic power

 Static current  no computation, etc
 Dynamic current  Switching on/off the gates
 The higher the number of switching events, the higher the dynamic power consumption

 Dynamic Energy  Amount of energy that is needed to be spent to do a job

 Time is no matter
 Power and Energy Dissipation
 Propagation delay and the power consumption of a gate are related
 Propagation delay is (mostly) determined by the speed at which a
given amount of energy can be stored on the gate capacitors
 the faster the energy transfer (higher power dissipation) the faster the gate
 For a given technology and gate topology, the product of the power
consumption and the propagation delay is a constant
 Power-delay product (PDP) – energy consumed by the gate per switching event
 An ideal gate is the one that is fast and consumes little energy, so the
ultimate quality metric is
 Energy-delay product (EDP) = power-delay
 Device Metrics
Performance Metrics of a Digital Chip:
 Cost
 NRE (fixed) costs - design effort
 RE (variable) costs - cost of parts, assembly, test
 Speed Single Die
 Delay (ns) → Operating Frequency (MHz)
 Power Dissipation
 Energy to Perform a Function
 Energy per bit (nJ/b)
 Reliability
 Noise immunity
 Noise margin
 Scalability Wafer
 Larger Designs
 Time-to-Market
 Reliability: Noise in Digital Integrated Circuits
 Noise : unwanted variations of voltages and currents at the logic nodes

 from two wires placed side by side

 Capacitive coupling v(t)

 Voltage change on one wire can

influence signal on the neighboring wire
 Cross talk
i(t)
 Inductive coupling
 Current change on one wire can
influence signal on the neighboring wire

 from noise on the power and ground supply rails VDD

 May influence signal levels in the gate

Noise Margins
 For robust circuits, want the “0” and “1” intervals to be as large as possible
VDD VDD

VOH "1"
NMH = VOH - VIH
VIH
Noise Margin High Undefined
Region
Noise Margin Low VIL
NML = VIL - VOL
VOL
"0"
Gnd Gnd
Gate Output Gate Input

Noise margin represents the levels of noise that can be sustained

when gates are cascaded
 Noise Immunity
 Noise margin expresses the ability of a circuit to overpower a noise source
 Noise sources: supply noise, cross talk, interference, offset
 Absolute noise margin values are deceptive
 Floating node is more easily disturbed than a node driven by a low
impedance (in terms of voltage)

 Noise immunity expresses the ability of the system to process and transmit
information correctly in the presence of noise (noise rejection)

 For good noise immunity, the signal swing (i.e., the difference between VOH
and VOL) and the noise margin have to be large enough to overpower the
impact of fixed sources of noise
Course Outline
• Course Outline
• Introduction to ASIC/FPGA IC Design
 Integrated Circuits (IC) History
 Digital Design vs. Analog Design
 ASIC vs. FPGA
 Design Abstraction and Metrics
 CMOS as the building block of Digital ASICs
 Layout
 Packaging

78
 MOS Device Theory

 Bipolar Junction Transistor (BJT)

 Small current in Base drives a larger current b/w Emitter & Collector.
Mostly  Quiescent power dissipation due to the Base current
Analog  High power dissipation limits the number of transistors on a single chip
 Not suitable for Very Large Scale Integration (VLSI)

 Metal Oxide Semiconductor Field Effect Transistors (MOSFET)

 Come with almost zero control current (Gate voltage controls the drain current)
 Higher integration
Mostly  Much lower power consumption than BJT
Digital  Come in two flavors : n-MOS (n-type dopants), p-MOS (p-type dopants)

 Complementary Metal Oxide Semiconductor (CMOS)

 Utilizing both n-MOS and p-MOS transistors
 MOS Device Theory
 Transistors are built on a silicon substrate
 Silicon is a Group IV material → covalent bonds with 4 adjacent atoms
 Silicon is a poor conductor → can be raised by adding dopants

Si Si Si
n-type p-type
 Group V dopants Si Si Si  Group III dopants
 Five valence electrons  3 valence electrons
 Extra electron free to move Si Si Si  Missing electron(hole) free to move
 Negative carrier  Positive carrier
 Example:  Example:
 Arsenic, Phosphorus  Boron
Si Si - Si Si Si Si
+
Si As+ Si Si B- Si

Si Si Si Si Si Si
 MOS Device Theory
 Four terminals: Body Source Gate Drain
1. Gate Polysilicon
2. Source SiO 2
3. Drain
4. Body G
n+ n+

p bulk Si D S
B
 Consists of :
 Gate (Metal (old), Polysilicon (now)) nMOS
 Insulating layer (SiO2 (oxide- glass))
 Source (n+ in nMOS, p+ in pMOS)
 Drain (n+ in nMOS, p+ in pMOS)
 Body (conductor)
 n+: Heavily doped n-type
 P+: Heavily doped p-type
 nMOS Transistors
 Gate–oxide–body stack looks like a capacitor

 Body is commonly tied to ground (0 V)

 Gate at low voltage:

 Body is at low voltage
 Source-body diode is OFF
 Drain-body diode is OFF
 No current flows Body Source Gate Drain
 Transistor is OFF

OFF
n+ n+

p bulk Si
 nMOS Transistors

 Gate at high voltage:

 Positive charge on gate
 Negative charge attracted to body
 Inverts a channel under gate to n-type
 Current flow in this channel b/w source and drain when drain voltage is nonzero
 Transistor is ON

Body Source Gate Drain

ON
n+ n+

p bulk Si
pMOS Transistors

 Similar to nMOS with reversed doping and voltages

 Body is commonly tied to high voltage (VDD)
 Gate low: transistor ON
 Gate high: transistor OFF
 Bubble indicates inverted behavior

Body Source Gate Drain

Polysilicon

SiO 2

G
p+ p+

p bulk Si D S
B
pMOS
MOS Transistors
 L is the channel length
 L : Process parameter, technology
 Smaller L → Faster transistors → higher speed circuits
 Typical process values: 0.35μm, 0.18μm, 0.13μm, 90nm, 60nm, …
 VDD decreases by technology
 1.5 V for 0.18 μm
 1.2 V for 0.13 μm
 Lower VDD saves power consumption
 GND = 0 V
 CMOS
 Silicon wafer is the base material
 Diameter: 10-30 cm
 Thickness: 1 mm

 CMOS : both nMOS and pMOS transistors fabricated on a single wafer

 Wells : special regions to separate bulks of nMOS and pMOS

SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

 CMOS
 Substrate must be tied to GND and n-well to VDD
 Poor connection of metal to lightly-doped semiconductor (Shottky Diode)
 Use heavily doped well and substrate contacts
GND V DD

p+ n+ n+ p+ p+ n+

n well
substrate tap p substrate
well tap
Cross Section along Dashed Line

GND VDD
Top View
 Layout
 Chips are specified with set of masks
 Minimum dimensions of masks determine transistor size (and hence
speed, cost, and power) SiO gate oxide 2

 “Feature size”
polysilicon
Lmin= distance between source and drain (channel) gate
W

(minimum width of Polysilicon) t ox

L
n+ n+
p-type body

 Feature size improves 30% every 3 years or so

Feature Size

 Can integrate 2× more functions per chip → 2× less cost per function

 Normalize for feature size when describing design rules (  Lmin / 2 )

 E.g.,  = 90nm in 0.18 μm process
 Layout Layers
 Each layout consists of various levels described by different colors.

Top View

Cross Section View

n well
P substrate
wafer
Design Rules
 Circuit engineer designs a circuit Deign Rule Check (DRC)
 Process engineer fabricates the design is the interface between them
 DRC : constraints on patterns in terms of minimum width and separation
 DRC: guarantees that the circuit to be manufacturable
 Digital VLSI Layout
 Designed and laid-out standard cells
 They are placed & abutted in a chip

Metal 2

Via 12

Metal 1

Several metal layers used for routing

 Digital VLSI Layout
 Standard cells are automatically placed and routed using different metal
layers through the corresponding CAD tools
 Chip Floorplan
 Start with the pin count (# of I/O and VDD, VSS pads)
 Pads are already designed (provided in the design kit)
Corner
Pads I/O Pads Corner VSS Core
Pads
VDD Core

I/O Pads
Core
I/O Pads

Design

Corner Corner
Pads I/O Pads Pads
Chip Floorplan : Pads

Layout View Design View

Course Outline
• Course Outline
• Introduction to ASIC/FPGA IC Design
 Integrated Circuits (IC) History
 Digital Design vs. Analog Design
 ASIC vs. FPGA
 Design Abstraction and Metrics
 CMOS as the building block of Digital ASICs
 Layout
 Packaging

97
Packaging
 Package:
 Die interface to outside world
 Removes heat from chip
 Mechanical support
 Protects die against humidity
× Introduces delay/parasitics to the chip

 Advanced Package Requirements:

 Electrical: Low Parasitics
 Mechanical: Reliable and Robust
 Thermal: Efficient Heat Removal
 Economical: Cheap
Package/Socket to Board Interconnection

Through-Hole Mounting Surface Mount

 Mechanically reliable  More wiring space
× Low package density  Higher package density
× Limits routing on the board  Chips at both sides of the board
 Dualin-Line (DIP) (up to 64 pins) × Weak chip-board connection
 PGA (up to 400 pins) × Non-accessible pins for testing
 Package/Socket to Board Interconnection
 For very large pin-counts, even surface-mount packaging is not enough!
 Ball Grid Array (BGA)

Solder bumps are used to connect both the die to the

package substrate and the package to the board
 Packaging Material/Type
 Package Material:
 Plastics (cheaper)
 Ceramic (Better heat removal)

 Package Types:
Packaging Types

Pin Grid Array (PGA) Quad Flat Pack (QFP)

Die
Solder bumps
Interconnect
Layers

Substrate

Ball Grid Array (BGA) Plastic Leader Chip Carrier

(PLCC)
Chapter 2: Programmable Logic Device
Logic circuit design review
• Sum of Product
• To get the desired canonical SOP expression we will add the minterms
(product terms) for which the output is 1.

• F = A’B + AB’ + AB
• Product of Sums (POS)
• To get the desired canonical POS expression we will multiply the maxterms
(sum terms) for which the output is 0.

• F = (A+B) . (A’+B’)
 Simple Programmable Logic Device (SPLD)
• Programmable Array Logic (PAL)
• Generic Array Logic (GAL)
• The structure of PAL and GAL is composed of the programmable AND
followed by the programmable OR gate.
• PAL, GAL can be used to configure the Sum of Product logic circuit.

Input lines
Input buffer
A B A B A A B B
A B A B A
Fix connection
B
Product
2
X 2 X=AB+AB+AB
X=AB+AB+AB term
lines
2

Fuse blown Fuse intact

(noconnection) (connection)
Example of PAL configuration
PAL /GAL
Macrocell
Or array
I1
OR Output
I2 Programmable logic O1
GATE
I3 logic array

PAL: one time OR Output

programmable GATE logic O2

GAL:
reprogrammable
OR Output
logic O3
GATE

In-1 OR Output
In logic Om
GATE
Macrocell

Tristate control Tristate control

From Output/input
From output and gate
and gate array
array

Tristate control
From Output/input
and gate
array
Programmable fuse
Complex Programmable Logic Device (CPLD)
• CPLD is consist of SPLDs

Logic Array Logic Array

I/O block (LAB) block (LAB) I/O
SPLD SPLD

Logic Array Logic Array

I/O block (LAB) block (LAB) I/O
PIA
SPLD SPLD
Programmable
Interconnect
Logic Array array Logic Array
I/O block (LAB) block (LAB) I/O
SPLD SPLD

Logic Array Logic Array

I/O block (LAB) block (LAB) I/O
SPLD SPLD
Field Programmable Gate Array)

Programmable Configurable Logic Block (CLB)

interconnections
IO IO IO IO
block block block block
IO IO
block block

CLB CLB CLB CLB

IO IO
block block

CLB CLB CLB CLB

IO IO
block block

CLB CLB CLB CLB

IO IO
block block

IO IO IO IO
block block block block
FPGA
CLB

CLB CLB
Logic module Logic module

Logic module Logic module

Logic module Logic module

Local Local
interconnect interconnect

Logic module Logic module

Global column
Global row
interconnect
interconnect
Logic Module – Lookup table (LUT)

Logic section LUT

Memory cells
A 2A1A0 1
A0 SOP
A 2A1A0 0
A1 output
I/O A 2A1A0 0
A2 LUT Associated A0 A 2A1A0 1 SOP
logic A1
A2 A 2A1A0 0 output
An-1
Logic module A 2A1A0 1
A 2A1A0 0
A 2A1A0 1 A2 A1 A0  A2 A1 A0  A2 A1 A0  A2 A1 A0
LUT

A2 A1 A0  A2 A1 A0  A2 A1 A0  A2 A1 A0  A2 A1 A0

Logic section LUT

Memory cells
A2A1A0 0
A2A1A0 1
A2A1A0 0
A0 A2A1A0 1
A1 SOP
A2 A2A1A0 1 output
A2A1A0 1
A2A1A0 1
A2A1A0 0
Chapter 3: Verilog HDL

Trương Ngọc Sơn, Ph.D

 What is Verilog

• Hardware Description Language (HDL)

• Hardware description languages such as Verilog
HDL and VHDL became popular
• Developed in 1983
• Standard: IEEE 1364, Dec 1995
• Hardware Description Languages (HDLs)

2 Verilog HDL Basics

Design flow

3 Verilog HDL Basics

 Popularity of Verilog

 Verilog HDL is a general-purpose hardware

description language that is easy tolearn and easy to
use
 Verilog HDL allows different levels of abstraction to
be mixed in the same model: gates, RTL, or behavioral
code
 Most popular logic synthesis tools support Verilog
HDL
 All fabrication vendors provide Verilog HDL libraries
for postlogic synthesis simulation
4 Verilog HDL Basics
Abstraction Levels in Verilog

Behavioral

RTL

Gate

5 Verilog HDL Basics

 Design Methodologies
 Top-down design methodology: we define the top-
level block and identify the sub-blocks necessary to
build the top-level block

6 Verilog HDL Basics

 Design Methodologies
 Bottom-up design methodology: we first identify the
building blocks that are available to us. We build
bigger cells, using these building blocks

7 Verilog HDL Basics

 Main Language Concepts (i)

• Concurrency

• Structure

8 Verilog HDL Basics

4 bit counter

9 Verilog HDL Basics

4 bit counter, top-down design

10 Verilog HDL Basics

 Module

 A module is the basic building block in Verilog.

 A module can be an element or a collection of lower-
level design blocks
 A module provides the necessary functionality to the
higher-level block through its port interface (inputs
and outputs)

11 Verilog HDL Basics

 Module
module <module_name> (<module_terminal_list>);
...
<module internals>
...
endmodule

12 Verilog HDL Basics

 Module
Specifically, the T-flipflop could be defined as a module
as follows:
module T_FF (q, clock, reset);
clock q
.
reset
.
<functionality of T-flipflop>
.
.
endmodule

13 Verilog HDL Basics

 Instances
module ripple_carry_counter(q, clk, reset);
output [3:0] q;. q[0] q[1] q[2] q[3]
input clk, reset; clk clock q clock q clock q clock q

T_FF tff0(q[0],clk, reset); reset reset reset reset

T_FF tff1(q[1],q[0], reset); reset

T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule

14 Verilog HDL Basics

 Instances
module T_FF(q, clk, reset);
output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q);
endmodule

15 Verilog HDL Basics

16 Verilog HDL Basics
 User Identifiers
• Formed from {[A-Z], [a-z], [0-9], _, $}, but ..
• .. can’t begin with $ or [0-9]
– myidentifier □
– m_y_identifier □
– 3my_identifier □
– $my_identifier □
– _myidentifier$ □
• Identifiers are case sensitive
– myid  Myid

17 Verilog HDL Basics

 Comments

• // The rest of the line is a comment

• /* Multiple line
comment */

• /* Nesting /* comments */ do NOT work */

18 Verilog HDL Basics

 Verilog Value Set

• 0 represents low logic level or false condition

• 1 represents high logic level or true condition

• x represents unknown logic level

• z represents high impedance logic level

19 Verilog HDL Basics

 Numbers in Verilog (i)

<size>’<radix> <value>

No of Binary  b or B Consecutive chars

bits Octal  o or O 0-f, x, z
Decimal  d or D
Hexadecimal  h or H

– 8’h ax = 1010xxxx
– 12’o 3zx7 = 011zzzxxx111

20 Verilog HDL Basics

 Numbers in Verilog (ii)

• You can insert “_” for readability

– 12’b 000_111_010_100
– 12’b 000111010100 Represent the same number

– 12’o 07_24
• Bit extension
– MS bit = 0, x or z  extend this
• 4’b x1 = 4’b xx_x1
– MS bit = 1  zero extension
• 4’b 1x = 4’b 00_1x

21 Verilog HDL Basics

 Numbers in Verilog (iii)

• If size is ommitted it
– is inferred from the value or
– takes the simulation specific number of bits or
– takes the machine specific number of bits

• If radix is ommitted too .. decimal is assumed

– 15 = <size>’d 15

22 Verilog HDL Basics

 Parameters in Verilog (iii)

• A parameter associates an identifier name with a

constant. Let the Verilog code include the following
declarations:
parameter n = 4;
parameter S0 = 2’b00, S1 = 2’b01, S2 = 2’b10, S3
= 2’b11;

23 Verilog HDL Basics

 Signal in Verilog code
• In Verilog, a signal in a circuit is represented as a net
or a variable with a specific type. The term net is
derived from the electrical jargon, where it refers to
the interconnection of two or more points in a circuit.
A net or variable declaration has the form

type [range] signal_name{, signal_name};

24 Verilog HDL Basics

 Nets (i)
• Can be thought as hardware wires driven by logic
• Equal z when unconnected
• Various types of nets
– wire
– wand (wired-AND)
– wor (wired-OR)
– tri (tri-state)
• In following examples: Y is evaluated,
automatically, every time A or B changes
25 Verilog HDL Basics
 Nets (ii)
A wire Y; // declaration
Y assign Y = A & B;
B

wand Y; // declaration
assign Y = A;
A assign Y = B;
Y
B
wor Y; // declaration
assign Y = A;
assign Y = B;

dr
tri Y; // declaration
A Y
assign Y = (dr) ? A : z;

26 Verilog HDL Basics

 Registers
• Variables that store values
• Do not represent real hardware but ..
• .. real hardware can be implemented with registers
• Only one type: reg
reg A, C; // declaration
// assignments are always done inside a procedure
A = 1;
C = A; // C gets the logical value 1
A = 0; // C is still 1
C = 0; // C is now 0
• Register values are updated explicitly!!
27 Verilog HDL Basics
 Vectors
• Represent buses
wire [3:0] busA;
reg [1:4] busB;
reg [1:0] busC;

• Left number is MS bit

• Slice management
busC[1] = busA[2];
busC = busA[2:1]; 
busC[0] = busA[1];

• Vector assignment (by position!!)

busB[1] = busA[3];
busB[2] = busA[2];
busB = busA; 
busB[3] = busA[1];
busB[4] = busA[0];
28 Verilog HDL Basics
 Integer & Real Data Types

• Declaration
integer i, k;
real r;
• Use as registers (inside procedures)
i = 1; // assignments occur inside procedure
r = 2.9;
k = r; // k is rounded to 3

• Integers are not initialized!!

• Reals are initialized to 0.0
29 Verilog HDL Basics
 Time Data Type

• Special data type for simulation time measuring

• Declaration
time my_time;

• Use inside procedure

my_time = $time; // get current sim time

• Simulation runs at simulation time, not real time

30 Verilog HDL Basics

 Arrays (i)
• Syntax
integer count[1:5]; // 5 integers
reg var[-15:16]; // 32 1-bit regs
reg [7:0] mem[0:1023]; // 1024 8-bit regs
• Accessing array elements
– Entire element: mem[10] = 8’b 10101010;
– Element subfield (needs temp storage):
reg [7:0] temp;
..
temp = mem[10];
var[6] = temp[2];

31 Verilog HDL Basics

 Arrays (ii)

• Limitation: Cannot access array subfield or entire

array at once
var[2:9] = ???; // WRONG!!
var = ???; // WRONG!!

• No multi-dimentional arrays
reg var[1:10] [1:100]; // WRONG!!

• Arrays don’t work for the Real data type

real r[1:10]; // WRONG !!

32 Verilog HDL Basics

 Strings
• Implemented with regs:
reg [8*13:1] string_val; // can hold up to 13 chars
..
string_val = “Hello Verilog”;
string_val = “hello”; // MS Bytes are filled with 0
string_val = “I am overflowed”; // “I ” is truncated

• Escaped chars:
– \n newline
– \t tab
– %% %
– \\ \
– \“ “

33 Verilog HDL Basics

 Logical Operators

• &&  logical AND

• ||  logical OR
• !  logical NOT
• Operands evaluated to ONE bit value: 0, 1 or x
• Result is ONE bit value: 0, 1 or x
A = 6; A && B  1 && 0  0
B = 0; A || !B  1 || 1  1
C = x; C || B  x || 0  x but C&&B=0

34 Verilog HDL Basics

 Bitwise Operators (i)

• &  bitwise AND

• |  bitwise OR
• ~  bitwise NOT
• ^  bitwise XOR
• ~^ or ^~  bitwise XNOR

• Operation on bit by bit basis

35 Verilog HDL Basics

 Bitwise Operators (ii)
c = ~a; c = a & b;

• a = 4’b1010;
b = 4’b1100;

c = a ^ b;

• a = 4’b1010;
b = 2’b11;

36 Verilog HDL Basics

 Reduction Operators
• &  AND
• |  OR
• ^  XOR
• ~&  NAND
• ~|  NOR
• ~^ or ^~  XNOR

• One multi-bit operand  One single-bit result

a = 4’b1001;
..
c = |a; // c = 1|0|0|1 = 1

37 Verilog HDL Basics

 Shift Operators

• >>  shift right

• <<  shift left

• Result is same size as first operand, always zero filled

a = 4’b1010;
...
d = a >> 2; // d = 0010
c = a << 1; // c = 0100

38 Verilog HDL Basics

 Concatenation Operator
• {op1, op2, ..}  concatenates op1, op2, .. to single number
• Operands must be sized !!
reg a;
reg [2:0] b, c;
..
a = 1’b 1;
b = 3’b 010;
c = 3’b 101;
catx = {a, b, c}; // catx = 1_010_101
caty = {b, 2’b11, a}; // caty = 010_11_1
catz = {b, 1}; // WRONG !!
• Replication ..
catr = {4{a}, b, 2{c}}; // catr = 1111_010_101101
39 Verilog HDL Basics
 Relational Operators
• >  greater than
• <  less than
• >=  greater or equal than
• <=  less or equal than

• Result is one bit value: 0, 1 or x

1 > 0 1
’b1x1 <= 0 x
10 < z x
40 Verilog HDL Basics
 Equality Operators
• ==  logical equality
Return 0, 1 or x
• !=  logical inequality
• ===  case equality
Return 0 or 1
• !==  case inequality

– 4’b 1z0x == 4’b 1z0x x

– 4’b 1z0x != 4’b 1z0x  x
– 4’b 1z0x === 4’b 1z0x  1
– 4’b 1z0x !== 4’b 1z0x  0

41 Verilog HDL Basics

 Conditional Operator

• cond_expr ? true_expr : false_expr

• Like a 2-to-1 mux ..

A
1
Y
Y = (sel)? A : B;
B 0
sel

42 Verilog HDL Basics

 Arithmetic Operators (i)
• +, -, *, /, %

• If any operand is x the result is x

• Negative registers:
– regs can be assigned negative but are treated as unsigned
reg [15:0] regA;
..
regA = -4’d12; // stored as 216-12 = 65524
regA/3 evaluates to 21861

43 Verilog HDL Basics

 Arithmetic Operators (ii)

• Negative integers:
– can be assigned negative values
– different treatment depending on base specification or not
reg [15:0] regA;
integer intA;
..
intA = -12/3; // evaluates to -4 (no base spec)
intA = -’d12/3; // evaluates to 1431655761 (base spec)

44 Verilog HDL Basics

Operator Precedence

Use parentheses to
enforce your
priority

45 Verilog HDL Basics

 Hierarchical Design

Top Level
E.g.
Module

Full Adder
Sub-Module Sub-Module
1 2

Half Adder Half Adder

Basic Module Basic Module Basic Module
1 2 3

46 Verilog HDL Basics

 Module
module my_module(out1, .., inN);
out1 output out1, .., outM;
in1 my_module
out2 input in1, .., inN;
in2

f .. // declarations
inN outM .. // description of f (maybe
.. // sequential)

endmodule

Everything you write in Verilog must be inside a module

exception: compiler directives

47 Verilog HDL Basics

 Example: Half Adder

A module half_adder(S, C, A, B);

S
output S, C;
B input A, B;
C
wire S, C, A, B;

assign S = A ^ B;
A S
Half assign C = A & B;
B Adder C
endmodule

48 Verilog HDL Basics

 Example: Full Adder
in1 A Half S I1 A Half S sum
Adder 1 Adder
in2 B C I2 B C I3
ha1 ha2 cout

cin
module full_adder(sum, cout, in1, in2, cin);
output sum, cout;
input in1, in2, cin;

wire sum, cout, in1, in2, cin;

Module wire I1, I2, I3; Instance
name name
half_adder ha1(I1, I2, in1, in2);
half_adder ha2(sum, I3, I1, cin);

assign cout = I2 || I3;

endmodule
49 Verilog HDL Basics
 Hierarchical Names

ha2.A

in1 A Half S I1 A Half S sum

Adder 1 Adder
in2 B C I2 B C I3
ha1 ha2 cout

cin

Remember to use instance names,

not module names

50 Verilog HDL Basics

 Port Assignments

module
• Inputs reg or net net

module

• Outputs reg or net net

module
net net
• Inouts

51 Verilog HDL Basics

 Continuous Assignements
a closer look
• Syntax:
assign #del <id> = <expr>;

optional net type !!

• Where to write them:
– inside a module
– outside procedures
• Properties:
– they all execute in parallel
– are order independent
– are continuously active
52 Verilog HDL Basics
 Structural Model (Gate Level)

• Built-in gate primitives:

and, nand, nor, or, xor, xnor, buf, not, bufif0,
bufif1, notif0, notif1

• Usage:
nand (out, in1, in2); 2-input NAND without delay
and #2 (out, in1, in2, in3); 3-input AND with 2 t.u. delay
not #1 N1(out, in); NOT with 1 t.u. delay and instance name
xor X1(out, in1, in2); 2-input XOR with instance name

• Write them inside module, outside procedures

53 Verilog HDL Basics

 Example: Half Adder,
2nd Implementation
A module half_adder(S, C, A, B);
S
output S, C;
B input A, B;
C
wire S, C, A, B;

xor #2 (S, A, B);

and #1 (C, A, B);
Assuming:
• XOR: 2 t.u. delay endmodule
• AND: 1 t.u. delay

54 Verilog HDL Basics

 Behavioral Model - Procedures (i)
• Procedures = sections of code that we know they
execute sequentially
• Procedural statements = statements inside a
procedure (they execute sequentially)
• e.g. another 2-to-1 mux implem:
begin
if (sel == 0)
Execution Y = B;
Flow Procedural assignments:
else
Y must be reg !!
Y = A;
end
55 Verilog HDL Basics
 Behavioral Model - Procedures (ii)

• Modules can contain any number of procedures

• Procedures execute in parallel (in respect to each
other) and ..
• .. can be expressed in two types of blocks:
– initial  they execute only once
– always  they execute for ever (until simulation finishes)

56 Verilog HDL Basics

 “Initial” Blocks
• Start execution at sim time zero and finish when
their last statement executes
module nothing;

initial
$display(“I’m first”); Will be displayed
at sim time 0
initial begin
#50;
$display(“Really?”); Will be displayed
end at sim time 50

endmodule

57 Verilog HDL Basics

 “Always” Blocks
• Start execution at sim time zero and continue until
sim finishes

58 Verilog HDL Basics

 Events (i)
• @
always @(signal1 or signal2 or ..) begin
..
end execution triggers every
time any signal changes
always @(posedge clk) begin
.. execution triggers every
end
time clk changes
from 0 to 1
always @(negedge clk) begin
.. execution triggers every
end time clk changes
from 1 to 0

59 Verilog HDL Basics

 Examples

• 3rd half adder implem • Behavioral edge-triggered

module half_adder(S, C, A, B); DFF implem
output S, C; module dff(Q, D, Clk);
input A, B; output Q;
input D, Clk;
reg S,C;
wire A, B; reg Q;
wire D, Clk;
always @(A or B) begin
S = A ^ B; always @(posedge Clk)
C = A && B; Q = D;
end
endmodule
endmodule

60 Verilog HDL Basics

 Events (ii)

• wait (expr)
always begin
wait (ctrl) execution loops every
#10 cnt = cnt + 1; time ctrl = 1 (level
#10 cnt2 = cnt2 + 2; sensitive timing control)
end

• e.g. Level triggered DFF ?

61 Verilog HDL Basics

 Example

always @(res or posedge clk) begin

res if (res) begin
a Y = 0;
b Y W = 0;
end
else begin
c W Y = a & b;
W = ~c;
clk end
end

62 Verilog HDL Basics

 Timing (i)

d
initial begin
#5 c = 1; c
#5 b = 0;
#5 d = c; b
end
0 5 10 15
Time
Each assignment is
blocked by its previous one

63 Verilog HDL Basics

 Timing (ii)

d
initial begin
fork c
#5 c = 1;
#5 b = 0; b
#5 d = c;
join 0 5 10 15
end Time

Assignments are
not blocked here

64 Verilog HDL Basics

 Procedural Statements: if
E.g. 4-to-1 mux:
module mux4_1(out, in, sel);
output out;
if (expr1) input [3:0] in;
true_stmt1; input [1:0] sel;

reg out;
else if (expr2) wire [3:0] in;
wire [1:0] sel;
true_stmt2;
.. always @(in or sel)
if (sel == 0)
else out = in[0];
def_stmt; else if (sel == 1)
out = in[1];
else if (sel == 2)
out = in[2];
else
out = in[3];
endmodule
65 Verilog HDL Basics
 Procedural Statements: case
E.g. 4-to-1 mux:
module mux4_1(out, in, sel);
case (expr) output out;
input [3:0] in;
input [1:0] sel;
item_1, .., item_n: stmt1;
reg out;
item_n+1, .., item_m: stmt2; wire [3:0] in;
.. wire [1:0] sel;

default: def_stmt; always @(in or sel)

case (sel)
0: out = in[0];
endcase 1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule

66 Verilog HDL Basics

 Procedural Statements: for
for (init_assignment; cond; step_assignment)
stmt;
E.g.
module count(Y, start);
output [3:0] Y;
input start;

reg [3:0] Y;
wire start;
integer i;

initial
Y = 0;

always @(posedge start)

for (i = 0; i < 3; i = i + 1)
#10 Y = Y + 1;
endmodule

67 Verilog HDL Basics

 Procedural Statements: while
E.g.
module count(Y, start);
output [3:0] Y;
input start;

reg [3:0] Y;
wire start;
integer i;
while (expr) stmt;
initial
Y = 0;

always @(posedge start) begin

i = 0;
while (i < 3) begin
#10 Y = Y + 1;
i = i + 1;
end
end
endmodule
68 Verilog HDL Basics
 Procedural Statements: repeat

E.g.
module count(Y, start);
output [3:0] Y;
input start;

repeat (times) stmt; reg [3:0] Y;

wire start;

initial
Can be either an Y = 0;
integer or a variable
always @(posedge start)
repeat (4) #10 Y = Y + 1;
endmodule

69 Verilog HDL Basics

 Procedural Statements: forever

Typical example:
clock generation in test modules
module test;

reg clk; Tclk = 20 time units

forever stmt;
initial begin
clk = 0;
forever #10 clk = ~clk;
Executes until sim end
finishes
other_module1 o1(clk, ..);
other_module2 o2(.., clk, ..);

endmodule

70 Verilog HDL Basics

 Mixed Model
Code that contains various both structure and behavioral styles
module simple(Y, c, clk, res);
output Y;
input c, clk, res;

reg Y;
wire c, clk, res;
res wire n;
c n Y not(n, c); // gate-level
clk
always @(res or posedge clk)
if (res)
Y = 0;
else
Y = n;
endmodule
71 Verilog HDL Basics
 System Tasks
Always written inside procedures

• $display(“..”, arg2, arg3, ..);  much like printf(), displays formatted string
in std output when encountered
• $monitor(“..”, arg2, arg3, ..);  like $display(), but .. displays string each
time any of arg2, arg3, .. Changes
• $stop;  suspends sim when encountered
• $finish;  finishes sim when encountered
• $fopen(“filename”);  returns file descriptor (integer); then, you can use
$fdisplay(fd, “..”, arg2, arg3, ..); or $fmonitor(fd, “..”, arg2, arg3, ..); to write
to file
• $fclose(fd);  closes file
• $random(seed);  returns random integer; give her an integer as a seed

72 Verilog HDL Basics

$display & $monitor string format

73 Verilog HDL Basics

 Compiler Directives
• `include “filename”  inserts contents of file into current file; write it
anywhere in code ..

• `define <text1> <text2>  text1 substitutes text2;

– e.g. `define BUS reg [31:0] in declaration part: `BUS data;

• `timescale <time unit>/<precision>

– e.g. `timescale 10ns/1ns later: #5 a = b;

50ns

74 Verilog HDL Basics

 Parameters
in[3:0] p_in[3:0]
out[2:0]
wu
A. Implelementation
without parameters
wd
clk
module dff4bit(Q, D, clk); module dff2bit(Q, D, clk);
output [3:0] Q; output [1:0] Q;
input [3:0] D; input [1:0] D;
input clk; input clk;

reg [3:0] Q; reg [1:0] Q;

wire [3:0] D; wire [1:0] D;
wire clk; wire clk;

always @(posedge clk) always @(posedge clk)

Q = D; Q = D;

endmodule endmodule
75 Verilog HDL Basics
 Parameters (ii)
module top(out, in, clk);
output [1:0] out;
A. Implelementation input [3:0] in;
input clk;
without parameters (cont.)
wire [1:0] out;
wire [3:0] in;
wire clk;

wire [3:0] p_in; // internal nets

wire wu, wd;

assign wu = p_in[3] & p_in[2];

assign wd = p_in[1] & p_in[0];

dff4bit instA(p_in, in, clk);

dff2bit instB(out, {wu, wd}, clk);
// notice the concatenation!!

endmodule
76 Verilog HDL Basics
 Parameters (iii)
module top(out, in, clk);
B. Implelementation output [1:0] out;
with parameters input [3:0] in;
input clk;
wire [1:0] out;
module dff(Q, D, clk); wire [3:0] in;
wire clk;
parameter WIDTH = 4;
output [WIDTH-1:0] Q; wire [3:0] p_in;
input [WIDTH-1:0] D; wire wu, wd;
input clk;
assign wu = p_in[3] & p_in[2];
reg [WIDTH-1:0] Q; assign wd = p_in[1] & p_in[0];
wire [WIDTH-1:0] D;
wire clk; dff instA(p_in, in, clk);
// WIDTH = 4, from declaration
always @(posedge clk) dff instB(out, {wu, wd}, clk);
Q = D; defparam [Link] = 2;
// We changed WIDTH for instB only
endmodule
endmodule
77 Verilog HDL Basics
 Testing Your Modules

Input output

Testbench Verilog Module

78 Verilog HDL Basics

 Testing Your Modules
module top_test;
wire [1:0] t_out; // Top’s signals
reg [3:0] t_in;
reg clk;

top inst(t_out, t_in, clk); // Top’s instance

initial begin // Generate clock

clk = 0;
forever #10 clk = ~clk;
end

initial begin // Generate remaining inputs

$monitor($time, " %b -> %b", t_in, t_out);
#5 t_in = 4'b0101;
#20 t_in = 4'b1110;
#20 t_in[0] = 1;
#300 $finish;
end

endmodule

79 Verilog HDL Basics

 The Veriwell Simulator
• Assuming that modules dff, top and top_test reside in
files dff.v, top.v and top_test.v respectively, run:
~hy225/veriwell/sparc_bin/veriwell dff.v top.v top_test.v

• result:
.. (initial messages)
0 xxxx -> xx
5 0101 -> xx
25 1110 -> xx
30 1110 -> 00
45 1111 -> 00
50 1111 -> 10
70 1111 -> 11
.. (final messages)

80 Verilog HDL Basics

Chapter 4: Combinational-Circuits

Trương Ngọc Sơn, Ph.D

 Combinational circuit
• Full adder

2 Combinational circuit
Multiplexers

3 Combinational circuit
 Multiplexers
• Verilog HDL

4 Combinational circuit
DeMultiplexers

5 Combinational circuit
 DeMultiplexers
• Verilog HDL

6 Combinational circuit
Multiplexers

7 Combinational circuit
Decoders

8 Combinational circuit
Decoders

9 Combinational circuit
Encoder

10 Combinational circuit
Decoder for 7-seg LED

11 Combinational circuit
 Decoder for 7-seg LED
• Verilog HDL

12 Combinational circuit
Chapter 5: Sequential Circuits

Trương Ngọc Sơn, Ph.D

RS Latch

2 Combinational circuit
 RS Latch
• Verilog HDL
module RS_LATCH(
input wire R,S,CLK,
output reg Q,Qb
);
always @(R,S,CLK) begin
if/*((CLK==1)&&(S==0)&&(R==1))*/({CLK,S,R}
==3'b101) begin Q=0;Qb=1;end
else if ((CLK==1)&&(S==1)&&(R==0)) begin
Q=1;Qb=0;end
end
endmodule
3 Combinational circuit
 JK Flip Flop
Input Output
Pre CLR CLK J K Q QD
0 0 x x x 1 1
0 1 x x x 1 0
1 0 x x x 0 1
1 1 0 x x Qo QDo
1 1 0 0 Qo QDo
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 NOT Q NOT QD

4 Combinational circuit
 JK Flip Flop
• Verilog HDL

5 Combinational circuit
D Latch

6 Combinational circuit
 D Latch
• Verilog HDL

7 Combinational circuit
D Flip-Flop

8 Combinational circuit
 D Flip-Flop
• The difference between a latch and a flip-flop is
that a latch is asynchronous, and the outputs can
change as soon as the inputs do (or at least after a
small propagation delay). A flip-flop, on the other
hand, is edge-triggered and only changes state
when a control signal goes from high to low or
low to high

9 Combinational circuit
10 Verilog HDL Basics
T Flip-Flop

11 Combinational circuit
 T Flip-Flop

module T_FF(
input wire t, clk,
output reg q, qb );
initial
begin
q=1 ;
qb=0;
end
always @( posedge clk)
if (t) begin
q = ~q ;
qb = !qb;
end
endmodule

12 Combinational circuit
Shift Register

13 Combinational circuit
 Shift Register
• Instance shift register using D-FF.
module DFF(
input wire d,clk,
output reg q );
always @(posedge clk)
q=d;
endmodule
// Serial input - serial output using DFF
module SISO(
input wire in, clk,
output wire out) ;
// signal declaration
wire q1,q2,q3 ;
//module instance
DFF ff1 (in,clk,q1);
DFF ff2 (q1,clk,q2);
DFF ff3 (q2,clk,q3);
DFF ff4 (q3,clk,out);
endmodule
14 Combinational circuit
 Module instance review
• Modules can be instantiated from within other modules.
When a module is instantiated, connections to the ports
of the module must be specified.
• There are two ways to make port connections.
– Connection by name, in which variables connected to each of
module inputs or outputs are specified in a set of parenthesis
following the name of the ports. In this method order of
connections is not significant.
– Ordered connection. In this method the order of the ports must
match the order appearing in the instantiated module.

15 Combinational circuit
 Module instance review
• Connection by name
module dff (
input wire clk, d,
output reg q );
top
always @(posedge clk) q = d; d_in
endmodule Inst_1 q_out
Inst_2
n1
d q d q
module top (
clk
input wire d_in, clk, clk clk
output wire q_out);

wire n1;
dff Inst_1 (.d(d_in), .q(n1), .clk(clk));
dff Inst_2 (.clk(clk), .d(n1), .q(q_out));
endmodule

16 Combinational circuit
 Module instance review
• Connection by order
module dff (
input wire clk, d,
top
output reg q );
d_in
always @(posedge clk) q = d;
Inst_1 q_out
Inst_2
endmodule n1
d q d q
module top ( clk
input wire d_in, clk, clk clk
output wire q_out);
wire n1;

dff Inst_1 (clk, d_in, n1);

dff Inst_2 (clk, n1, q_out);
endmodule

17 Combinational circuit
Thanasis Oikonomou 18 Verilog HDL Basics
Shift Register – Serial input, parallel outputs
• Instance the shift register using D-FF

19 Combinational circuit
Shift Register – Serial input parallel outputs
module DFF(
input wire d,clk,
output reg q );
always @(posedge clk)
q=d;
endmodule
// Serial input - parallel output using DFF
module SIPO(
input wire in, clk,
output wire [3:0] q) ;
// signal declaration

//module instance
DFF ff1 (in,clk,q[0]);
DFF ff2 (q[0],clk,q[1]);
DFF ff3 (q[1],clk,q[2]);
DFF ff4 (q[2],clk,q[3]);
endmodule

20 Combinational circuit
Counter

21 Combinational circuit
Asynchronous Counter

22 Combinational circuit
 Counter
• Instance counter with T-FF

23 Combinational circuit
 Synchronous counter

Thanasis Oikonomou 24 Verilog HDL Basics

 Counter
• Instance counter with T-FF

25 Combinational circuit
26 Verilog HDL Basics
 Homework
• Design a circuit to control 8 LEDs
– Light LEDS sequentially from left to right then turn 8
LEDs off sequentially from left to right (one-by-one).
– The frequency is adjusted by two switches
– The input clock is 50Mhz

27 Verilog HDL Basics

Chapter 6: Synchronous Sequential
Circuits
Trương Ngọc Sơn, Ph.D
 Synchronous sequential circuit
• Combinational logic circuits: The outputs are determined
fully by the present values of inputs
• Flip-flop: The output depends on the state of the flip-flop
rather than the value of its inputs at any given time; the
inputs cause changes in the state
• Sequential circuit: The outputs depend on the past behavior
of the circuit, as well as on the present values of inputs
• Synchronous sequential circuit: clock signal is used to
control the operation of a sequential circuit
• The alternative, in which no clock signal is used, is called
an asynchronous sequential circuit

2
 Synchronous sequential circuit
• A sequential circuit is a circuit with memory, which
forms the internal state of the circuit.
• Unlike a combinational circuit, in which the output is a
function of input only, the output of a sequential circuit
is a function of the input and the internal state. The
synchronous design methodology is the most commonly
used practice in designing a sequential circuit. In this
methodology, all storage elements are controlled (i.e.,
synchronized) by a global clock signal and the data is
sampled and stored at the rising or falling edge of the
clock signal

3
 Review of Verilog assignment and
procedure

Thanasis Oikonomou 4 Verilog HDL Basics

 Continuous Assignments
review

• Continuously assigns right side of expression to left

side.
• Limited to basic Boolean and ? operators. For
example a 2:1 mux:
– ? operator
assign D = (A= =1) ? B : C; // if A then D = B else D = C;

– Boolean operators
assign D = (B & A) | (C & ~A); // if A then D = B else D = C;
 Procedural Assignments

• Executes a procedure allowing for more powerful

constructs such as if-then-else and case statement.
• For example 2:1 mux:
– if-else
if (A) D = B else D = C;
– case This is obviously much easier
case(A) to implement and read then
1'b1 : D = B; Boolean expressions!!
1'b0 : D = C;
endcase
 Always Block

• An always block is an example of a procedure.

• The procedure executes a set of assignments when
a defined set of inputs change.
 2:1 mux Always Block
Module mux_2_1(a, b, out, sel); Declare Module and IO as before.
input a, b, sel;
output out; All data types in always blocks must be
declared as a ‘reg’ type.
reg out; This is required even if the data type is for
always @ (a or b or sel) combinational logic.
begin
if (sel) out = a; The always block ‘executes’ whenever
else out = b;
signals named in the sensitivity list
change.
end
endmodule Literally: always execute at a or b or
sel.
Sensitivity list should include
wire out; conditional (sel) and right side (a, b)
assign out =(sel==1)?a:b; assignment variables.
 As Easier Way to Implement the
Sensitivity List
• Recent versions of Verilog provides a means to
implement the sensitivity list without explicitly
listing each potential variable.
• Instead of listing variables as in the previous
example
always @ (a or b or sel)
Simply use The * operator will automatically
identify all sensitive variables.
always @*
 Blocking vs Non-Blocking Assignments
• Blocking (=) and non-blocking (<=) assignments are provided to
control the execution order within an always block.

• Blocking assignments literally block the execution of the next

statement until the current statement is executed.
– Consequently, blocking assignments result in ordered
statement execution.
For example:

assume a = b = 0 initially;
a = 1; //executed first
b = a; //executed second
then a = 1, b = 1 after ordered execution
 Blocking vs Non-Blocking Cont

• Non-blocking assignments literally do not block the execution of the next

statements. The right side of all statements are determined first, then the left
sides are assigned together.
– Consequently, non-blocking assignments result in simultaneous or
parallel statement execution.

For example:

assume a = b = 0 initially;
a <= 1;
Execute together (in parallel)
b <= a;
then a = 1, b = 0 after parallel execution
Result is different from ordered exec!!! Does not preserve logic flow
 To Block or Not to Block ?

• Ordered execution mimics the inherent logic flow of

combinational logic.
• Hence blocking assignments generally work better for
combinational logic.
• For example:

x=a&b y=x|b

logic flow
 To Block or Not to Block ? cont
Module blocking(a,b,c,x,y);
input a,b,c; Blocking behavior a b c x y
output x,y;
reg x,y;
Initial values 1 1 0 1 1
always @* a changesàalways block execs 0 1 0 1 1
begin
x = a & b; x = a & b; //make assignment 0 1 0 0 1
y = x | c; y = x | c; //make assignment 0 1 0 0 0
end
endmodule
Non-blocking behavior a b c x y
Module nonblocking(a,b,c,x,y); Initial values 1 1 0 1 1
input a,b,c;
output x,y; a changesàalways block execs 0 1 0 1 1
reg x,y;
x = a & b; 0 1 0 1 1
always @*
begin y = x | c; //x not passed from here 0 1 0 1 1
x <= a & b;
make x, y assignments 0 1 0 0 1
y <= x | c;
end
endmodule non-blocking behavior does not preserve
logic flow!!
 Synchronous sequential circuit

State register: a collection of D FFs controlled by the same clock

signal
Next-state logic: combinational logic that uses the external input and
internal state (i.e., the output of register) to determine the new value
of the register
Output logic: combinational logic that generates the output signal

14
Design of synchronous counter

15
 Design of synchronous counter
• Sample code
module Counter
#(parameter N= 8)
( input wire clk, reset,
output wire [N-1:0] q );
// signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// body, register
always @(posedge clk, posedge reset)
if (reset)
r_reg <= 0;
else
r_reg<=r_next; // <= is non-blocking statement
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg;
endmodule
Thanasis Oikonomou 16 Verilog HDL Basics
 Up/ down counter
• Design 8-bit synchronous up/down counter

17 Verilog HDL Basics

 8-bit up/down counter
module CounterUD
( input wire clk,reset,ud,
output wire [7:0] q );
// signal declaration
reg [7:0] r_reg;
wire [7:0] r_next;
// body, register
always @(posedge clk, posedge reset)
if (reset)
r_reg<=0;
else
r_reg<=r_next;
// next state logic
assign r_next = (ud==1)?r_reg + 1:r_reg - 1;
// output logic
assign q=r_reg;
endmodule

18 Verilog HDL Basics

 Register
• A register is a collection of D FFs that are controlled
by the same clock and reset signals
• Serial In – Serial Out (SISO) shift register. The block
diagram of 4-bit SISO shift register is shown in the
following figure.

19
 Register
• Sample code
module Shift_SISO

#(parameter N= 4) // 500,000,000 for 0.1Hz

( input wire clk,reset,s_in,
output wire s_out
);
// signal declaration

reg [N-1:0] r_reg;

wire [N-1:0] r_next;
// body, register
always @(posedge clk, posedge reset)
r_reg<=r_next;
// next state logic
assign r_next = {s_in,r_reg[N-1: 1]};
// output logic
assign s_out= r_reg[0];
endmodule
20
Serial input – parallel output shift register

21
 Register
• Sample code
module Shift_SIPO
(
input wire clk,s_in,
output wire [7:0] q_out );
// signal declaration
reg [7:0] r_reg;
wire [7:0] r_next;
// body, register
always@(negedge clk)
r_reg<=r_next;
// next state logic
assign r_next = {s_in,r_reg[7:1]};
// output logic
assign q_out= r_reg;

22
Serial input – parallel output shift register

23
24 Verilog HDL Basics
 Synchronous sequential circuit
Finite state machine (FSM)

• Synchronous sequential circuits are realized using combinational logic and

one or more flip-flops.
• The circuit has a set of primary inputs, W , and produces a set of outputs, Z.
The stored values in the flip-flops are referred to as the state, Q, of the circuit
• Under control of the clock signal, the flip-flops change their state as
determined by the combinational logic that feeds the inputs of these flip-
flops. the circuit moves from one state to another
25
 Moore and Mealy type of FSM

• Mealy type: The outputs are a function of the present state of the
flip-flops and of the primary inputs
• Moore type: The outputs always depend on the present state,
they do not necessarily have to depend directly on the primary
inputs
• that sequential circuits whose outputs depend only on the state of
the circuit are of Moore type, while those whose outputs depend
on both the state and the primary inputs are of Mealy type
• Sequential circuits are also called
26 finite state machines (FSMs)
 State Machine
• The first step in designing a finite state machine is
to determine how many states are needed and
which transitions are possible from one state to
another

27
 State Machine
module simple (Clock, Resetn, w, z);
input Clock, Resetn, w; output z;
reg [2:1] y, Y;
parameter [2:1] A = 2’b00, B = 2’b01, C = 2’b10;
// Define the next state combinational circuit
always @(w, y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2’bxx;
endcase
// Define the sequential block
always @(negedge Resetn, posedge Clock)
if (Resetn == 0) y < = A;
else y < = Y;
// Define output
assign z = (y == C); 28
Endmodule
FSM

29
 FSM
module fsm-eg-mult-seg SO: if(a)
( if(b)
input wire clk , reset , state_next=S2;
input wire a , b , else
output wire yo, y l ); state_next=Sl;
//symbolic state declaration else
localparam [1:0] S0 = 2’b00; S1 = 2'b01 , state_next=S0;
S2=2'b10; Sl: if(a)
// signal declaration state_next=S0;
reg [1 : 0] state_reg,state_next ; else
// state register state_next=S1;
always @ (posedge clk ,posedge reset) S2: state_next=S0;
i f (reset) default: state_next=S0;
state_reg<=S0; endcase
else //Moore outputlogic
state_reg<=state_next; assign yl=(state_reg==S0)||(state_reg==Sl);
//next_state logic //Mealy outputlogic
always @* assign y0=(state_reg==SO)&a&b;
case (state_reg) endmodule

30
Design of Counter Using Sequential Circuit

31
Design of Counter Using Sequential Circuit

32
Design of Counter Using Sequential Circuit
• Sample code

33
 Homework #1
• Design the up/down counter. The input clock is
50Mhz. The circuit count up or down, with the
frequency is selected by two switches (f,2*f,4*f,8*f,
where f is less than fclk). The block diagram is shown
as follows
CLR

CK_50M f<0> q<0>

CK_50M
f<1>

f<2>
q<7>
f<3>

S0

S1

U_D
34
Chapter 7: ASIC/FPGA Chip Design
Verilog for Synthesis
Assoc. Prof. Truong Ngoc Son
ASIC / FPGA Design Flow

2
Synthesis

3
Synthesis

4
Synthesis in Different Levels

5
Synthesis

6
Synthesis

7
Synthesis

8
Synthesis Tools

9
Synthesis

10
Synthesis is Constraint-Driven

11
Synthesis Tools

12
Divide and Conquer for Optimal Synthesis

13
Partitioning

14
Partitioning in Verilog

15
Good Partitioning (Partition at
Register Boundaries)

16
Poor Partitioning (Partition at
Combinational Logic)

17
Good Partitioning (Avoid Glue Logic)

18
HDL for Synthesis

19
HDL for Synthesis (General Guidelines)

20
HDL for Synthesis (General Guidelines)

21
Synthesizable Constructs

22
Non-Synthesizable Constructs

23
Design for Synthesis (No Timing Loop)

24
Latch Inference in Combinational Logic

25
Avoid Latch Inference in If-else Statements

26
Avoid Latch Inference in Case Statements

27
Clock

28
Clock (No Internally Generated Clock)

29
Clock (No Gating)

30
Clock (No Gating)

31
Clock (No Gating)

32
Clock

33
Architectural Techniques : Critical Path

34
Digital Design Metrics

35
Digital Design Metrics

36
Maximum Clock Frequency: Critical Path

37
Pipelining (to Improve Throughput)

38
Architectural Techniques :Pipelining

39
40