Synthesis of Sequential Circuits: Flip-Flops
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ScribdTranslationsSynthesis of Sequential Circuits: Flip-Flops
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ScribdTranslationsAbou Bekr Belkaid University of Tlemcen Level: L2-TTL
Faculty of Technology Subject: TS412
Department of Telecommunications
April 2023
TP N°04: Synthesis of sequential circuits: Synchronous flip-flops and
Asynchronous
For certain logic circuits, the output state depends not only on the
combination applied to the input (combinational logic) but also to the previous state of
circuit outputs: they are called sequential and have a 'memory' effect. The logic
sequential is therefore a combinatory logic with output memorization. This
Memory is accomplished by what is called a flip-flop; it is an organ of
unit memorization (memorization of a single piece of data).
I. Objectf :
The purpose of this lab is to practically design the various RS, D, JKH, and T flip-flops.
starting from the DL3155M19 module of LORENZO GROUP.
II. Theoretical reminder
II.1 Scales RS
It is a flip-flop that has two outputs (Q and ) and Q
two inputs R (for Reset) and S (for
Set).
Symbolic diagram
- Truth table: (with Q+ this is the future state, and Q: past state)
If S=0 and R=0, the flip-flop keeps its previous state (Q+= Q)
If S=0 and R=1, the flip-flop goes to zero (Q+= 0)
If S=1 and R=0, the flip-flop goes to a (Q+= 1)
If S=1 and R=1, forbidden combination ((Q+=Φ)
The reduced truth table is illustrated opposite:
Then we draw the following truth table.
Logical equation
According to the truth table of the RS flip-flop, we have:
Q+¿=S RQ+ S R Q +SR Q =S R Q + S R =R ( S+ S Q) =R ( S+Q ) ¿
S+Q ) = R(S +Q )=R +(S +Q )¿
Q+¿=R (
The logic circuit of the RS flip-flop with NOR gates is as follows:
In the same way, we express the equation of the RS latch using only NAND gates and
we obtain :
Q+¿=S (R Q)¿
The logic diagram of the RS flip-flop with NAND gates is as follows:
III.
IV.
V.
II.2 Synchronous RSH Bascule
The RSH flip-flop is an RS flip-flop synchronized by a clock signal H. When H=0,
the flip-flop is in memory state. When H=1, the flip-flop operates like a flip-flop
RS.
Symbolic scheme
Its operation can be summarized as follows:
The corresponding flowchart:
Example of a timeline
The timing diagram of an RSH flip-flop on the rising edge, with the state
initial Q = 0 is illustrated by the following figure:
II.3 Synchronous JK Flip-Flop (JKH)
It is a flip-flop that resembles the RS flip-flop. It has two outputs (Q and and twoQ
inputs J and K. The JK flip-flop takes care of the indeterminate case of the RS flip-flop, its
The operation is defined by the following table:
With Qn+1is the future state, and Qnprevious state
Its truth table is therefore:
Equation logique :L’équation logique simplifiée par le tableau de Karnaugh en
encircling the 1 :
Qn+ 1=G1+ G2=[Link] +[Link]
Qn+ 1=[Link] +[Link]
¿ J.Q n+ [Link] +Qn Q n
¿ J.Q n+Q n .( K +Q n)
¿ J.Q n+Q n .( [Link] )
¿ J.Q n . Q n.( K.Q n )
The JKH logic diagram using only NAND gates is the same as that of JK.
multiplied by the input H, as indicated by the following logic circuit:
VI.
The limitation of the JKH is when J = 1 and K = 1: The output oscillates between 0 and 1 throughout
the duration of the high state of the clock signal, for this we use a JK flip-flop with
triggering on front (rising or falling).
Another solution is to use a Master-Slave JK flip-flop.
II.4 D Latch
The D flip-flop is the fundamental memory cell used in the vast majority of
The flip-flop copies the input D to the output Q when the clock is active H = 1.
When the clock is inactive H = 0, the flip-flop retains the previous state. At level 1 (high) we
can write:
Logical equation: Qn+ 1=[Link] + H. D.
Note:
One can realize the D flip-flop from the RS flip-flop with R = D, Sit is represented
as follows:
Or also, based on the JK flip-flop, it is represented by:
The flowchart of the 'D latch'
The logic circuit of the 'D latch' from a JK flip-flop (using the gates)
NAND only) is as follows:
The 'D latch' flip-flop is widely used in synchronous counters.
Example: The operation timeline of a D flip-flop on the rising edge, with
initially Q = 0 :
II.5 Drawbridge T
The T flip-flop for 'toggle'. If its T input is active, it toggles on every pulse.
of the clock from where its name comes. If its input T is inactive, it maintains its state. It can be
make with a D flip-flop by connecting the output Qn+1 at entry D, or with the help of a JK flip-flop
by connecting J and K to create the T input. As the T flip-flop has the property of toggling every
clock pulse, it thus performs a frequency division by 2; it will also serve as
base for the realization of meters.
The flowchart of the synchronous T flip-flop from a JKH flip-flop (with NAND gates)
only) is:
Example: The operating timeline of a T flip-flop on the rising edge, with
initially Q = 0.
It is noted that the output signal frequency (Q) is divided by two compared to that
from the lever T (fQ= fT/2), since the period of Q is double the period of the
bascule T (TQ= 2 · fT).
III. Practical implementation of the scales
III.1 Bascule RS
1. Assemble the RSH balance using the DL3155M19 from LORENZO
GROUP.
2. Test all possible combinations and deduce the simplified truth table.
3. Complete the following timeline by analyzing the operation of the assembly:
III.2 Bascule D
1. Provide the diagram of a synchronous D flip-flop using only the RSH flip-flop.
2. Provide the flowchart for this assembly, indicating the pinout of the component used.
3. Carry out the assembly of the synchronous D toggle and test all combinations.
possibilities.
4. Provide the assembly timeline and the simplified truth table.
III.3 Bascule JK
1. Build the JK flip-flop circuit.
2. Test its operation and compare it to the truth table.
3. Create a frequency divider by two using the JK flip-flop.