REVIEW doi:10.

1038/nature10679

Tunnel field-effect transistors as

energy-efficient electronic switches
Adrian M. Ionescu1 & Heike Riel2

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy
needed for switching, but the field-effect transistors (FETs) in today’s integrated circuits require at least 60 mV of gate
voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using
quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device
channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction
over complementary metal–oxide–semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology
could improve low-power integrated circuits.

R
educing the size of complementary metal–oxide–semiconductor As the transistor gate length is reduced, improved performance
(CMOS) field-effect transistors (FETs) has enabled extraordi- requires the supply voltage, VDD, and simultaneously the threshold volt-
nary improvements in the switching speed, density, functional- age, VT, to be lowered to keep the overdrive factor (VDD – VT) high. As a
ity and cost of microprocessors. But advanced CMOS technology now consequence, the leakage current, IOFF, increases exponentially (see the
faces two problems1 that together result in high power consumption: the vertical intercept of I–V plots in Fig. 1a) because the S of a MOSFET is
increasing difficulty in further reducing the supply voltage, and stopping not scalable but has a minimum value of 60 mV per decade (that is, it
the rising leakage currents that degrade the switching ratio of ‘on’ and takes 60 mV to increase the current by one order of magnitude) at room
‘off ’ currents (ION/IOFF). Recent reviews2,3 have highlighted the need for temperature. Typical values of S in advanced CMOS technology are
new devices that can compete with or complement CMOS transistors. close to 100 mV per decade; by lowering VDD from 500 mV to 250 mV
Here we review the physics, design and optimization of one such while preserving the overdrive, the leakage power has been shown to
device, the tunnel FET (TFET), and consider the potential and draw- increase unacceptably by a factor of 275 in a 45-nm bulk CMOS tech-
backs of this energy-efficient device that could bring the voltage supply nology6.
of integrated circuits below 0.5 V. We discuss the technology boosters Another way of reducing the voltage supply without performance
needed to increase its performance, the reduced sensitivity of its direct loss is to increase the turn-on steepness, which means decreasing the
current characteristics to gate length, and the variability of its electrical average subthreshold swing, Savg7,8, defined as:
characteristics to changes in conditions. Finally, we compare its perfor-
mance in various material systems — silicon, group III–V compounds Savg = VT – VGOFF ≈ VDD (2)
and carbon — and discuss the related problems. log IT log ION
IOFF IOFF
The quest for an energy-efficient switch Therefore, devices with a steep S, called steep-slope switches, are
In a metal–oxide–semiconductor FET (MOSFET), the current- expected to enable VDD scaling.
switching process involves the thermionic (temperature-dependent) Figure 1b shows a qualitative comparison of some major candi-
injection of electrons4,5 over an energy barrier. This sets a fundamental dates to improve the characteristics of bulk silicon MOSFET switches:
limit to the steepness of the transition slope from the off to the on state. multigate devices for improved electrostatics; high-mobility chan-
The gate voltage required to change the drain current by one order of nels exploiting group III–V and SiGe materials; and TFETs that use
magnitude when the transistor is operated in the subthreshold region quantum-mechanical tunnelling. At moderate performance require-
is reflected in the expression of the subthreshold swing, S: ments, such as operation point A, TFETs offer not only improved ION/
IOFF, but also superior performance (higher ION at the same voltage) or
S = dVG dΨ S , c 1 + Cd m ln 10 kT power savings at the same performance (lower voltage for the same ION)
YdΨ S d (log I
1 44 2 44 3
10
D) Cox q
over MOSFETs. However, when a much higher performance is required,
m n (1)
such as at operation point B, a MOSFET is the better solution.
" kT ln10 , 60 mV decade –1 ; T = 300 K The energy efficiency of a logic operation can be evaluated by
q
analysing its switching energy diagram9,10 (Fig. 1c), showing the bal-
where VG is the gate voltage, ID is the drain current, kT/q is the thermal ance of the dynamic, Edynamic, and the leakage, Eleakage, components of the
voltage, and Cd and Cox are the depletion and the oxide capacitances, total switching energy, E, versus the VDD:
respectively. The term m is the transistor body factor, and n is a fac-
Etotal = Edynamic + Eleakage = α LdCVDD 2 + LdIOFFVDDτ delay
tor that characterizes the change of the drain current with the surface
potential, ΨS, reflecting the conduction mechanism in the channel. A . α LdCVDD 2 = LdCVDD 2 IOFF = LdCVDD 2 c α + IOFF m (3)
subthermal S would be less than kT/q ln10 and could be obtained by ION ION
. LdCVDD ^α + 10 S h
–V
using new physical principles rather than thermionic injection.
DD
2

1
Ecole Polytechnique Fédérale Lausanne, 1015 Lausanne, Switzerland. 2IBM Research – Zurich, 8803 Rüschlikon, Switzerland.

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 INSIGHT REVIEW

a b High mobility (III–V, SiGe) Figure 1 | Power challenge and main characteristics of an
ION Ideal energy-efficient tunnel FET. a, Transfer characteristics (drain
current, ID, and gate voltage, VG) of a MOSFET switch showing
TFET B an exponential increase in IOFF (more than tenfold increase for
Drain current, log lD

Drain current, log lD

∝ (VDD – VT)2 A every 60 mV at room temperature) because of an incompressible
Bulk Si subthreshold swing, S. Here the simultaneous scaling down
MOSFET
of both the supply voltage, VDD, and the threshold voltage, VT,
MuG
VT maintains the same performance (ION) by keeping the overdrive
∝ exp
S kT/q (VDD - VT) constant. b, Qualitative comparison of three
S = 60 mV decade–1
engineering solutions to improve the characteristics of the bulk
silicon MOSFET switch (red): a multigate device (MuG, blue) for
VDD – VT
IOFF
improved electrostatics; a high-mobility channel (purple) using
group III–V and SiGe materials; and a TFET (green), which has
0 VA VDD a steep off–on transition and the lowest IOFF. At operation point
Gate voltage, VG
A, because of its subthermal subthreshold swing, the TFET offers
Gate voltage, VG
not only an improved ION/IOFF but also a superior performance
and a power saving at the same performance as a MOSFET. At
c d operation point B, corresponding to higher performance, the
MOSFET switch becomes the better solution. c, Comparison
of the minimum switching energy, Emin, and the corresponding
voltage supply, VDDmin, for a subthermal swing device (S < 60 mV
Energy per cycle, E

Ideal MOSFET decade–1, green curve) and the ideal MOSFET (S = 60 mV

decade–1, red) at the same ION/IOFF. d, Comparison between
Energy

Bulk Si MOSFET
switching energy and performance for a MOSFET and a TFET.
The steep-swing TFET offers better energy efficiency at lower or
moderate performance level.
Emin
Subthermal TFET
swing device
VDDmin
0
0
Voltage supply, VDD Performance

where Ld is the logic depth, C is the switched capacitance, τdelay is the the electrical and the mechanical force are used to define super-abrupt
delay time and α is the logic activity factor (typically ~0.01). The opera- transitions between the off and on states. Experimentally, an S of less
tion frequency, f, can be expressed as than 2 mV per decade has been demonstrated18, but electromechanical
devices have their own limitations, such as voltage-scaling limitations,
f= 1
(4) reliability issues and a stringent need for a controlled environment for
Ld τ delay
robust operation.
and in modern technologies can be considered empirically as being In this review, we concentrate on the TFET. The gated p-i-n struc-
proportional to VDD (ref. 11). Therefore the power dissipation, P, is ture, comprising a p- and an n-doped region on either side of a gated
intrinsic region, was proposed in 1978 by Quinn et al.21. Banerjee
P = α LdCVDD 2f = IOFFVDD . KCVDD = IOFFVDD3 (5) et al.22 studied the behaviour of a three-terminal silicon TFET, and
Takeda et al.23 explored various aspects specifically related to the
Consequently, a technology that would enable a fivefold voltage scal- scaling down. Baba24 fabricated TFETs called surface tunnel transis-
ing (from 1.0 V to 0.2 V) with a negligible leakage power could offer a tors in group III–V materials. In 1995, Reddick and Amaratunga25
125-fold power dissipation reduction. From equation (3), it seems that reported experiments on silicon surface tunnel transistors. In 1996,
CMOS logic has a lower limit in energy per operation, Emin, owing to the Koga and Toriumi26 proposed a three-terminal ‘forward-biased’ sili-
exponential increase of the subthreshold leakage, IOFF, with VDD scal- con tunnelling device as a post-CMOS switch candidate. In 2000,
ing (see Fig. 1c). Hanson et al.10 showed that Emin is proportional to the Hansch et al.27 published experimental results on a reverse-biased
switched capacitance multiplied by the square of the S, C × S2, whereas vertical silicon TFET that had a highly doped boron delta-layer fab-
VDDmin is proportional to S. Nose and Sakurai12 demonstrated that for an ricated by molecular beam epitaxy. Aydin et al.28 processed lateral
optimized CMOS circuit design, the ratio of leakage to dynamic energy TFETs on silicon-on-insulator (SOI) in 2004, which in principle were
is approximately 0.3–0.5 across a wide range of parameters. similar to TFETs without an intrinsic region. The gate over a p–n
Equation (3) shows that at the same performance (ION and f), any junction was intended to reduce the gate capacitance to increase the
device that can offer the required ION/IOFF at a lower VDD (based on a speed. Recently, TFETs fabricated in various material systems (carbon,
smaller S) will always be more energy efficient (lower Emin and VDDmin). silicon, SiGe and group III–V materials)29–33 have emerged experi-
This is depicted in Fig. 1d, which compares the switching energy for a mentally as the most promising candidates for switches with ultralow
TFET and a MOSFET as a function of the performance required. standby power and sub-0.5 V logic operation.
Many device innovations to lower S below the MOSFET thermal
limit, by decreasing the factors m and n in equation (1), have been pro- The physics of TFETs
posed. Reducing n to achieve a subthermal S involves a modification In contrast to MOSFETs, in which charge carriers are thermally injected
of the carrier-injection mechanism. For this, impact ionization13 and over a barrier, the primary injection mechanism in a TFET is interband
quantum-mechanical band-to-band tunnelling (BTBT)14 in TFETs have tunnelling, whereby charge carriers transfer from one energy band into
been proposed. Another alternative to decrease S is to reduce the body another at a heavily doped p+–n+ junction. This tunnelling mechanism
factor, m, to a value smaller than 1. This can be achieved by using the was first identified by Zener14 in 1934. In a TFET, interband tunnelling
recently proposed negative-capacitance FET (NC-FET)15–17 or micro- or can be switched on and off abruptly by controlling the band bending in
nano-electromechanical (M/NEM) movable electrodes in M/NEM- the channel region by means of the gate bias. This function can be real-
FET or NEM relay devices18–20, in which the instability points between ized in a reverse-biased p-i-n structure (Fig. 2a). In principle, the TFET

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 REVIEW INSIGHT

is an ambipolar device, showing p-type behaviour with dominant hole a VG < 0

conduction and n-type behaviour with dominant electron conduction. Vs VD < 0
However, by designing an asymmetry in the doping level or profile,
or by restricting the movement of one type of charge carrier using het- n+ i p+
erostructures, the tunnelling barrier at the drain can be widened to sup-
press the ambipolarity8,34. The asymmetry also achieves a low off-state
current3. In the TFET off state (dashed blue line in Fig. 2b), the valence
band edge of the channel is located below the conduction band edge of b On
EC c
λ
the source, so BTBT is suppressed, leading to very small TFET off-state Off 60 mV decade–1
currents that are dictated by the reverse-biased p-i-n diode. Applying a q∆VG EV
negative gate voltage (solid red curve in Fig. 2b) pulls the energy bands EF

VG (a.u.)
up. A conductive channel opens as soon as the channel valence band
EF ∆Φ
has been lifted above the source conduction band because carriers can
now tunnel into empty states of the channel. Because only carriers in the
energy window ∆Φ can tunnel into the channel, the energy distribution
of carriers from the source is limited; the high-energy part of the source log lD (a.u.)
Source Channel Drain
Fermi distribution is effectively cut off 35, as shown in Fig. 2b. Thus the
electronic system is effectively ‘cooled down’, acting as a conventional
MOSFET at a lower temperature. This filtering function makes it pos- Figure 2 | Principle of operation of a TFET. a, Schematic cross-section of
sible to achieve an S of below 60 mV per decade (Fig. 2c). However, the p-type TFET with applied source (VS), gate (VG) and drain (VD) voltages. b,
Schematic energy band profile for the off state (dashed blue lines) and the on
channel valence band can be lifted by a small change in gate voltage, and
state (red lines) in a p-type TFET. In the off state, no empty states are available
the tunnelling width can effectively be reduced by the gate voltage36,37. in the channel for tunnelling from the source, so the off current is very low.
As a consequence of the BTBT mechanism, S in a TFET is not constant, Decreasing VG moves the valence band energy (EV) of the channel above the
but depends on the applied gate–source bias, as indicated in Fig. 2c, conduction band energy (EC) of the source so that interband tunnelling can
increasing with the gate-to-source bias. The key to the better voltage occur. This switches the device to the on state, in which electrons in the energy
scaling of a TFET than a MOSFET is that S remains below 60 mV per window, ∆Φ (green shading), can tunnel from the source conduction band
decade over several orders of magnitude of drain current. into the channel valence band. Electrons in the tail of the Fermi distribution
One challenge in TFETs is to realize high on currents because ION crit- cannot tunnel because no empty states are available in the channel at their
ically depends on the transmission probability, TWKB, of the interband energy (dotted black line), so a slope of less than 60 mV decade–1 can be
tunnelling barrier. This barrier can be approximated by a triangular achieved. This is indicated in the schematic transfer characteristics shown in c.
In contrast to a conventional MOSFET, a TFET has a slope that is not linear on
potential, as indicated by the grey shading in Fig. 2b, so T can be calcu- a logarithmic scale, which can be explained by the complex dependency of the
lated using the Wentzel–Kramer–Brillouin (WKB) approximation4,36: tunnel current on the transmission probability through the barrier, as well as
on the number of available states determined by the source and channel Fermi
functions. The BTBT can be approximated by the triangular potential barrier
. exp e – o
4λ 2m* Eg 3
T WKB
3q ħ ^Eg + ∆Φ h
(6) indicated in grey. Because the tunnel current depends on the transmission
probability through the barrier, as well as on the number of available states
determined by the source and channel Fermi functions, the resultant slope
where m* is the effective mass and Eg is the bandgap. Here, λ is the is not linear on a logarithmic scale, which it is for a conventional MOSFET.
screening tunnelling length and describes the spatial extent of the transi- λ, screening tunnelling length. a.u., arbitrary units; EF, Fermi energy.
tion region at the source–channel interface (Fig. 2b); it depends on the
specific device geometry. In a TFET, at constant drain voltage, VD, the To realize a high tunnelling current and a steep slope, the transmis-
VG increase reduces λ and increases the energetic difference between sion probability of the source tunnelling barrier should become close
the conduction band in the source and the valence band in the chan- to unity for a small change in VG. The WKB approximation, shown in
nel (ΔΦ), so that in a first approximation the drain current is a super- equation (6), suggests that the bandgap (Eg), the effective carrier mass
exponential function37 of VG. As a result, in contrast to the MOSFET, (m*) and the screening tunnelling length (λ) should be minimized for
the point subthreshold swing of the TFET is no longer a constant but high barrier transparency. Whereas Eg and m* depend solely on the
strongly depends on VG. The smallest subthermal values occur at the material system, λ is strongly influenced by several parameters, such
lowest gate voltages. A high on current requires a high transparency of as the device geometry, dimensions, doping profiles and gate capaci-
the tunnelling barrier, thus maximizing TWKB, which in the best case tance3,39,40. A small λ results in a strong modulation of the channel bands
should be unity. Equation (6) suggests optimized design approaches by the gate. This requires a high-permittivity (high-κ) gate dielectric8
to boost the on current. Luisier and Klimeck38 found that the WKB with as low an equivalent oxide thickness as possible. Furthermore,
approximation works properly in direct bandgap semiconductors, such the body thickness of the channel should be minimized, showing in
as InAs (if one single imaginary path connecting the valence band and the best case one-dimensional electronic transport behaviour36,39. The
the conduction band dominates the tunnelling process), but has limited abruptness of the doping profile at the tunnel junction is also impor-
accuracy for Si and Ge structures or when quantum effects and phonon- tant. To minimize the tunnelling barrier, the high source doping level
assisted tunnelling become dominant. must fall off to the intrinsic channel in as short a width as possible. This
requires a change in the doping concentration of about 4–5 orders of
Fundamental performance boosters magnitude within a distance of only a few nanometres40,41. Increasing
The goals for TFET optimization are to simultaneously achieve the the source doping reduces λ and may lead to a slightly smaller energy
highest possible ION, the lowest Savg over many orders of magnitude barrier at the tunnel junction because of bandgap narrowing40. How-
of drain current, and the lowest possible IOFF. To outperform CMOS ever, the energy filtering effect described above becomes effective only
transistors, the target parameters for TFETs are: ION in the range of if the Fermi energy in the source is not too large36.
hundreds of milliamperes; Savg far below 60 mV per decade for five TFETs do not follow the same scaling rules as MOSFETs, in which
decades of current; ION/IOFF > 105; and VDD < 0.5 V. Because S decreases many parameters must be scaled simultaneously to keep the same elec-
with the VG (Fig. 2c), TFETs are naturally optimized for low-voltage tric field throughout the device42. In a TFET, the high electric fields
operation. exist only at the junctions. The current is determined by the screening

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 INSIGHT REVIEW

a b c
1.0 Channel Drain 1.0 Channel Drain
n-type TFET
0.5 Off 0.5 On
VG > 0

Energy (eV)
Energy (eV)
0.0 0.0
Conduction
Vs VD > 0 –0.5 Ge band –0.5 Ge
Si Si
–1.0 –1.0
p++ n– n+
–1.5 Valence –1.5
Source Channel band
–2.0 –2.0 Source Channel
–40 –20 0 20 40 –40 –20 0 20 40
Position, x (nm) Position, x (nm)

d e f Source Channel
2.0 Source Channel 2.0
p-type TFET InAs InAs
1.5 Off 1.5 On
Si Si

Energy (eV)

Energy (eV)
VG < 0 1.0 1.0
0.5 0.5
Vs VD < 0
0.0 0.0
n++ p– p+ –0.5 –0.5
–1.0 Channel Drain –1.0 Channel Drain

–40 –20 0 20 40 –40 –20 0 20 40

Position, x (nm) Position, x (nm)

Figure 3 | Band diagrams of heterostructure C-TFETs. C- TFET device Si channel for the n-type switch and an InAs source and silicon channel for the
n-type (a–c) and p-type (d–f) architectures (a, b) and related band diagrams p-type switch (solid lines). Band diagrams correspond to device architectures
in the off (b, e) and on (c, f) state for two major implementations: all-silicon with a channel length of 50 nm and a high-κ dielectric thickness of 3 nm. The
n- and p-type devices (dashed lines) and heterostructures with a Ge source and graphs show the conduction band (blue) and the valence band (red).

tunnelling length, so that the length of the intrinsic region has little and high ION can been achieved with moderate doping and a staggered
effect on the device characteristics, as long as the length is above some band lineup (S = 33 mV per decade and an intrinsic cutoff frequency
critical length, Lcrit (~20 nm for silicon TFETs42), at which p-i-n leakage of 4.74 THz)47. Koswatta et al.48 included electron–phonon scattering
becomes predominant. Experimental results43 confirmed the lack of in the transport model and found the best TFET performance for a
dependence of ION on TFET length. broken-gap heterojunction.
Device optimization should apply to both n- and p-type TFETs Another optimization criterion is maximizing the gate modulation
simultaneously, to offer a complementary TFET (C-TFET) technol- of the tunnelling barrier width by an appropriate alignment of the tun-
ogy for logic circuits. In a heterostructure TFET, the materials are nelling path with the direction of the electric field modulated by the
chosen such that the source material has a small bandgap, so that the gate. By overlapping the gate with the tunnelling region, or designing
width of the energy barrier at the source junction is reduced in the a source region covered with an epitaxial intrinsic channel layer under
on state, whereas the drain material has a large bandgap, which cre- the top gate, ION can be improved by a factor of more than 10 and a low
ates the largest possible energy barrier width at the drain side in the Savg can be obtained49–52.
off state to keep the off current low. The way in which the bands line The effect of a staggered bandgap at the TFET source-to-channel
up with each other at the heterojunction is also crucial44,45. Knoch46 junction as a technology booster is shown in Fig. 3. The aim is to find
suggested that although a broken line-up yields the best ION, only a solution for an optimized C-TFET. The simulated devices have a
S ≥ 60 mV per decade is obtained; therefore, a combination of steep S silicon channel length of 50 nm, a 20-nm-thick film and asymmetric

a 14 b
Si
Ge 10–4
Minimum tunnelling length (nm)

12 InAs
Drain current, IDS (A µm–1)

MOSFET
10–6 Ge
10 TFET

10–8
8
InAs
6 10–10
TFET

4 10–12 All-Si
VDS = 100 mV TFET

2 10–14 VDS = 1 V

0.0 0.2 0.4 0.6 0.8 1.0 –0.8 –0.4 0.0 0.4 0.8
Gate voltage, |VG| (V) Gate voltage, VGS (V)

Figure 4 | Importance of the material system on TFET performance. a, the tunnelling length in the off and the on state reflects an improved ION/IOFF.
Modulation of the minimum screening tunnelling length with the applied b, Corresponding transfer characteristics of a state-of-the-art 65-nm CMOS
gate voltage in all-silicon (black), Ge-source (red) and InAs-source (blue) transistor (black), complementary Ge/InAs TFET (green) and complementary
TFETs, showing the beneficial effect of a higher tunnelling rate due to the all-Si TFET (blue). The complementary Ge/InAs TFET achieves the best
shorter tunnelling length in a heterostructure TFET with a low bandgap trade-off between a low IOFF, a steep subthreshold swing and performance. IDS,
source material compared with silicon. By contrast, a higher ratio between drain-to-source current; VDS, drain-to-source voltage; VGS, gate voltage at source.

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 REVIEW INSIGHT

doping to avoid ambipolarity. The cross-section and bands in the off a SiN protection layer
and the on state of the n-type TFET are shown in Fig. 3a–c. Chang-
50 nm
ing the source material from Si to Ge considerably improves λ and NiSi
ΔΦ at the same applied VG in the on state. A similar band-engineering NiSi
optimization performed for the p-type device with an InAs source is
shown in Fig. 3d–f. The corresponding reduction of the screening tun- Spacers Gate
nelling length and its dependence on the VG when the source bandgap is
Poly Si
changed is depicted in Fig. 4a. The simulated ID versus VG characteristics NiSi NiSi
of a 65-nm CMOS technology node with 50-nm all-Si C-TFETs and TiN
HfO2 Source
50-nm Ge/InAs C-TFETs are compared in Fig. 4b. At VD = VG = 1 V, the Drain
tSi
Ge and InAs TFETs have on currents of 244 μA μm–1 and 83 mA mm–1, LG
HDD LDD HDD
respectively, which means improvements by factors of 480 and 162,
respectively, over their all-Si TFET counterparts, and much lower IOFF
and ION/IOFF than the 65-nm CMOS device. Their average swing over b 10–7
VDS: –0.1/–0.2/–0.4/
three decades of drain current is close to 60 mV per decade, showing –0.6/–0.8/–1V
10–8
that further optimization is needed. Heterostructure TFETs33,45,46,53

Drain current, ID (A wfm–1)

similar to those reported here can offer viable solutions for on currents
10–9
higher than 100 μA μm–1, ION/IOFF > 107 and VDD smaller than 0.5 V. The
all-Si C-TFETs have the lowest IOFF and average subthreshold swings 10–10
of less than 40 mV per decade, but their ION is not a good trade-off for
performance compared with CMOS transistors. 10–11

Band-to-band tunnelling 10–12 Point slope

The fundamental performance boosters of TFETs described before 42 mV decade–1 VSD: 0.1/0.2/
require engineering solutions concerning their design, choice of mate- 10–13 0.4/0.6/0.8/1V
rials and integration with advanced silicon platforms. In this section –2 –1 0 1 2 3
we discuss existing and state-of-the-art research efforts aimed at TFET VGS (V) VGD (V)
optimization, design and implementation, together with their experi-
mental or predicted electrical performance. c 10–5
P
On current, ION (A wfm–1)

All-silicon TFETs P ×2,700 N

10–6
TFETs offer the potential for a low off current and a small S, but they
generally have a lower on current than conventional MOSFETs, so a N ×335
10–7
smart design strategy could achieve a small Savg and a high ION with- N
N
out degrading IOFF. As with CMOS technology boosters, performance
boosters for TFETs should not be suggested independently. Instead, an 10–8 P
additive strategy of boosters for the same device should be applied, so P
that improvements in device performance are cumulative54. The major 10–9
technology boosters for all-silicon TFETs include54,55 the use of a high-κ SOI SGOI 15% SGOI 30% GeOI
gate dielectric, a more abrupt doping profile at the tunnel junction, a
thinner body, higher source doping, a double gate, a gate oxide aligned Figure 5 | Implementation of all-Si technology boosters. a, Scanning
with the intrinsic region, and a shorter intrinsic region (and gate) length. electron micrograph showing the cross-section of an SOI TFET from CEA-Leti
that implemented some major technology boosters. Image reprinted, with
The physics of TFETs are governed by the BTBT rate, so they differ permission, from ref. 31. b, ID-VG characteristics of the all-silicon TFET,
from those of conventional MOSFETs. It is therefore likely that the sen- showing a subthreshold swing at room temperature of 42 mV decade–1 and
sitivity of the device’s characteristics to variations in the technology an IOFF smaller than 100 fA μm–1 at VDS = 1 V (different colours correspond
parameters will differ too, which can imply new technology challenges. to different values of VD). c, A major improvement in ION obtained in an
Boucart56 predicted that TFET performance will be much less sensi- all-silicon C-TFET by applying the same design and fabrication of TFET on
tive to doping fluctuations and gate length scaling than in conventional Si1–xGexOI (molar fraction x = 0, 15% and 30%). Note the 335-fold and 2,700-
CMOS transistors. By contrast, control of the high-κ gate process, the fold improvements for the n-TFET (N) and p-TFET (P), respectively, for the
abruptness of doping at the tunnel junction, and the film thickness in SiGeOI over the SOI TFET. VDS, drain-to-source voltage; VGD, gate voltage at
ultrathin-body SOI devices, with significantly less parameter varia- drain; VGS, gate voltage at source; VSD, source-to-drain voltage.
tion than that required by CMOS devices, is crucial for building future
TFETs with reproducible characteristics. optimizations of an all-silicon TFET58, values of ION close to 100 μA μm–1
Figure 5a shows a recent all-silicon lateral TFET fabricated on fully in sub-60-nm devices were obtained.
depleted silicon with a silicon film thickness of 20 nm and a gate length
of 100 nm31,57 that benefits from some major technology boosters and Group III–V-semiconductor-based TFETs
from advanced engineering of the contacts. The device includes a high-κ A further strategy to improve ION and S is to use low-bandgap and low-
gate stack (3 nm HfO2, and 3 nm and 10 nm TiN), a double epitaxi- effective-mass materials and band engineering to increase BTBT. For
ally raised Si source–drain, and an asymmetric n+ source and p+ drain this, group III–V materials are very attractive as they can provide small
achieved in two successive lithography and implantation steps. This tunnelling mass and allow different band-edge alignments.
all-silicon TFET shows extremely low IOFF values (~10–100 fA μm–1; Simulation showed that by reducing only the bandgap of the TFET
Fig. 5b), but ION is less than 0.1 μA mm–1 at a VDD of 1 V. By applying material from Si to InAs or InSb, the ION increases by several orders of
the same process and design to Si1–xGexOI substrates (x = 0, 15% or magnitude and can be reached at lower electric fields3. Recent experi-
30%), extraordinary improvements in ION can be obtained57: a 335-fold mental results for InGaAs TFETs indicate that a higher ION at a lower
improvement for the n-TFET and a 2,700-fold improvement for the VG than with Si TFETs seems possible59,60. The first InGaAs TFET by
p-TFET, compared with the SOI TFET counterparts (Fig. 5c). In recent Mookerjea et al.59 achieved an on current of 20 μA μm–1 with an S of

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 INSIGHT REVIEW

250 mV per decade, whereas Zhao et al.60 improved ION to 50 μA μm–1 ‘gate-all-around’ (GAA) architecture, in which the gate is wrapped
with an S of around 90 mV per decade, which is the best local swing around the cylindrical nanowire channel to provide the best electrostatic
achieved so far for III–V-based TFETs but is still above the thermal control. Simulations have shown that λ is reduced three- to fourfold
limit of MOSFETs. The degraded S is attributed to parasitic tunnelling when using the GAA nanowire architecture compared with using a
mechanisms involving traps in the source tunnel junction61. single-gate device with a channel thickness or diameter of 10 nm68. The
The effective bandgap for tunnelling can be decreased even further cross-section of a recently fabricated vertical n-i-p InAs–Si–Si nanowire
by using heterostructures. Although there is not yet full agreement on heterojunction TFET with InAs as a low-bandgap source69 is shown in
whether a staggered or a broken gap alignment works best, all theor­ Fig. 6b. The single-nanowire TFET exhibits switching operation under
etical studies predict that the TFET performance can be significantly reverse-bias conditions with an S of ~220 mV per decade and a drive
enhanced compared with homojunctions45–47,62. The first experimental current of ~0.4 μA μm–1 (see Fig. 6d). This first InAs-source, Si-channel
implementations of III–V heterojunction TFETs have only recently been TFET implementation needs further optimization. It is anticipated that
demonstrated63,64. To reduce the tunnelling barrier, InAs and GaAsSb the drive current can be improved by introducing n-type doping in the
were chosen for the source, with AlGaSb and InGaAs for the channel. InAs wire, by scaling the equivalent oxide thickness, and by reducing
Another reason for selecting these materials is that they allow lattice- the contact resistance.
matched growth, and thus the use of conventional III–V growth and
processing technologies. Carbon-based TFETs
For the C-TFET technology, the combination of an InAs source with Carbon nanotubes and graphene nanoribbons are appealing materials
a Si drain and channel yields the best on-state performance for the for use in TFETs. The light effective mass of their charge carriers, their
p-TFET45. However, InAs and Si possess a lattice mismatch of about small and direct bandgap, and their excellent electrostatic control of the
11%, which results in highly defective material growth and prevents gate over the channel owing to the ultrathin body make them among
integration onto Si in a conventional approach. This challenge can be the best choices in terms of both materials and device geometry. The
met by using grown nanowires. They are attractive materials as they first ever TFET demonstrating an S of less than 60 mV per decade was
can be grown epitaxially via metal–organic chemical vapour deposition achieved with a carbon nanotube structure by Appenzeller et al.29 in
directly on Si(111) (refs 65, 66). 2004. In their device, the electrostatics in the carbon nanotube were
A comprehensive study has experimentally investigated67 the quality controlled by two independent gates. A common back gate electrostati-
and suitability of the InAs–Si heterojunction, which is a key element cally doped both the source and drain, and another gate allowed control
for high-performance TFETs. In particular, studying highly doped p–n of the channel bands, creating a p-i-p FET device. Although the on cur-
junctions (so-called Esaki tunnel diodes) provides insight into the tunnel rent was low because the carriers had to tunnel through two barriers,
process, and thus the limits of the TFET drive can be explored. Figure 6a an S of 40 mV per decade was achieved for the first time. Furthermore,
shows a schematic cross-section of such an InAs–Si heterostructure simulation and temperature-dependent measurements provided clear
nanowire device in which the tunnel junction is located between the evidence that a carbon nanotube TFET had indeed been realized29,35.
n-type InAs nanowire and the p-type Si substrate. The highest Si doping More advantageous would be the implementation of a p-i-n-structured
of 1020 atoms cm–3 produced tunnel diodes with current densities as high carbon nanotube TFET. Progress has been hampered by the difficulty of
as 250 kA cm–2 at 0.5 V reverse bias (see Fig. 6c). The high tunnel cur- establishing appropriately doped carbon nanotube regions and abrupt
rents and the observed negative differential resistance are indications of junctions. So far there has been little experimental verification of carbon
a well-defined and abrupt Si–InAs heterojunction66. nanotube TFETs, but several theoretical studies have been conducted70.
Moreover, the vertical nanowire provides an optimal geom- The influence of electron–phonon scattering on the performance of
etry for minimizing the screening tunnelling length, λ, by using a carbon nanotube TFETs has also been investigated71, and there is strong

a b 102 Figure 6 | InAs–Si heterojunction diodes and

Metal 1 × 1020 atoms cm–3
contact
TFETs for improved performance. a, Left,
101
schematic cross-section of an InAs–Si
100 4 × 1019 atoms cm–3 heterostructure nanowire diode. Right, scanning
electron micrograph of an InAs nanowire grown
JD (kA cm–2)

Isolating 10–1
epitaxially on Si. b, Current density–voltage
spacer 10–2 (JD-V) characteristics of Si–InAs heterojunction
InAs

layer
10–3 single-nanowire tunnel diodes. The high
1 × 1019 atoms cm–3
tunnel current densities required for TFETs
10–4
are achieved for high doping levels. Different
10–5 1 × 1016 atoms cm–3 colours refer to different doping densities. c, Left,
SiO2 200 nm Forward Reverse
p++-Si 10–6
schematic cross-section of a vertical InAs–Si
0.50 0.25 0.00 –0.25 –0.50 heterostructure nanowire TFET. Right, scanning
VD (V) electron micrograph showing a cross-section of
the fabricated TFET. The InAs nanowire has a
c d diameter of 100 nm, and the undoped Si channel
10–7
VD = 0.2–1.0 V on the p-type substrate is 150 nm long. d, Transfer
10–8 characteristics, ID-VG, for various source–drain
Source biases of the TFET shown in c.
InAs 10–9
ID (A)

10–10

i-Si 10–11
Gate
10–12
p-Si

400 nm 10–13
Drain Si(111) –2 –1 0 1 2
VG (V)

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 REVIEW INSIGHT

evidence that BTBT is dominated by optical phonon-assisted inelastic a

transport, which can lead to a degradation of the S. 1.00 30

Gain = dVOUT / dVIN

Furthermore, simulations have shown that the specific energy depen- 24
dence of the one-dimensional density of states (which arises because 0.75 18
the nanowire radius is so small) can be exploited to reach the quantum 12
capacitance limit, resulting in better control of the channel potential.

VOUT (V)
0.50 6
In this regime, the quantum capacitance, Cq, which is determined by CMOS
0
the change of the charge in the channel resulting from a change in gate All-Si TFET
0.4 0.5 0.6
Ge/InAs TFET
potential, is far smaller than the oxide capacitance, Cox, due to the BTBT, 0.25 VIN (V)
and thus almost equals the total capacitance. This leads to a reduced
total capacitance and improves the gate delay72. 0
TFETs based on graphene nanoribbons theoretically offer the same
benefits as carbon nanotube TFETs and may also provide planar pro- 0.0 0.2 0.4 0.6 0.8 1.0
cessing compatibility. But so far, only theoretical studies have been VIN (V)
performed, and these demonstrate the high potential of graphene b 1 10
nanoribbons in significantly improving ION to several hundred μA μm–1, VDD
with an IOFF of only a few pA μm–1 and a slope of less than 20 mV per U
decade73.
However, for a practical implementation using graphene

Switching energy, U (fJ)

1
nanoribbons, the influence of the line edge roughness on the bandgap
and the transport properties, and thus on the TFET performance, must FinFET

VDD (V)
be considered. Luisier and Klimeck74 found that with rougher edges, the
off current significantly increases because of a lowering of the graphene
0.1 0.1
nanoribbon bandgap and an increase in the source-to-drain tunnelling
leakage through the gate potential barrier. This leads to a deteriora- TFET
tion of S and ION/IOFF, which are no longer sufficient and thus limit the
switching performance of graphene nanoribbon TFETs. The theoretical
investigations done so far show that graphene nanoribbon TFETs have 0.01
great potential, although for a practical implementation, significant
technical challenges need to be met. Fiori and Iannaccone75 suggested 107 108 109 1010
using bilayer graphene to fabricate TFETs, presenting an attractive alter- Clock frequency (Hz)
native to graphene nanoribbons. The benefit of this approach is that the
required energy gap is opened by applying a vertical electric field to the Figure 7 | Circuit-level characteristics of low-power TFETs. a, Comparison
graphene bilayer, rather than by preparing small ribbons, which would of the voltage transfer characteristics, VOUT-VIN, of CMOS and TFET inverters
require single-atom precision patterning. corresponding to the complementary device characteristics in Fig. 4b. The Ge/
InAs C-TFET inverter has the most abrupt transition from the 1 to the 0 state
Energy-efficient integrated circuits with the highest differential gain, dVOUT/dVIN (inset) and best noise margins.
The 65-nm CMOS transistor and the 50-nm C-TFET in both silicon b, Switching energy, U (red), and power supply voltage, VDD (blue), against clock
frequency simulated with a calibrated compact model for a heterostructure
and Ge/InAs can be compared directly by simulating the main charac- (In,Al)As/(Ga,Al)Sb TFET (filled symbols) and a silicon FinFET with a 20-nm
teristics of inverter cells (the basic building blocks of a circuit) operating channel length (open symbols); 16 cores of 1.5 × 106 circuits each are assumed.
at the same VDD. Figure 7a shows the voltage transfer characteristics of The total chip power was constrained, and VDD, channel length, threshold
inverters in these three implementations. The Ge/InAs C-TFET inverter voltage (VT), Fermi energy level in the source (Ve), width and design were
has the most abrupt transition between the 1 and 0 states because it has optimized to maximize the clock frequency79. Figure reprinted, with permission,
a steep slope combined with a reasonably high ION, which results in from ref. 79.
the best noise margins and the highest dVOUT/dVIN gain. However, the
transient response of the Ge/InAs C-TFET inverter is worse than that proposed a performance comparison between p-i-n TFETs with a car-
of the CMOS at a VDD of 1 V (or even 0.5 V) with an associated delay of bon nanotube channel and conventional thermionic silicon MOSFETs.
358 ps. The advantages of TFET logic should be explored at lower fre- Their choice of a carbon nanotube channel is motivated by its direct
quencies corresponding to low-power and low-standby-power CMOS energy bandgap and small carrier mass. They based their study on a
specifications76, especially in terms of power savings. comprehensive simulation framework and on experimental results. Spe-
A specific characteristic of TFETs that influences their transient cifically, they investigated the delay time, τ, and the switching energy
response was reported by Mookerjea et al.77, who were the first to observe calculated as the power-delay product. They found the intrinsic delay
that in a TFET the gate capacitance, CGG , is dominated by the gate-to- to be similar for both devices, but the TFET became much slower when
drain capacitance, CGD, under all bias conditions. This is in strong contrast load capacitance was considered. They also reported that phonon scat-
to a MOSFET, where the CGD and the gate-to-source capacitance, CGs, have tering degrades τ for both devices, but this increase is more important
relatively balanced contributions to the gate capacitance. In a TFET, CGD for TFETs. When operated under the quantum capacitance limit, TFETs
predominates even near the off state because the source-to-channel bar- have smaller switching energies than MOSFETs.
rier resistance is large and the channel-to-drain barrier resistance is low. Until recently, investigations of circuit performance have been limited
Therefore, the effective load capacitance for unloaded TFET inverters can by the lack of availability of accurate compact models for TFETs cali-
be more than twice the gate capacitance because of the enhanced Miller brated on fabricated n- and p-type TFETs. One way to circumvent this
effect (an increase in the equivalent input capacitance of an inverting problem was to build look-up table (LUT) models for current–voltage
voltage amplifier resulting from the amplification of capacitance between and capacitance–voltage characteristics using simulation data. One such
the input and output terminals) and the effective drive current. This can study6 used a LUT model for a type II heterojunction tunnel transistor
degrade the delay time of TFET inverters and generate current overshoots. (HETT) and compared its power reduction with a commercial bulk
In general, there is an agreement in all published studies that TFETs CMOS 45-nm technology in simulated ring oscillators. At VDD = 1 V,
are attractive for low-standby-power applications. Koswatta et al.78 a high-performance CMOS ring oscillator has a period of 450 ps and

1 7 NOV E M B E R 2 0 1 1 | VO L 4 7 9 | NAT U R E | 3 3 5
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 INSIGHT REVIEW

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