SCL (Serial Clock Line):
It is the clock signal that is generated by the master device to synchronize the data transfer between the master and the slave devices.
SDA (Serial Data Line):
It carrIes the data being transmitted between devices.
The SDA line is bidirectional, meaning both the master and slave devices can drive data onto the bus, but only one device can transmit data at a time, while
others can only listen.
Application Report
SLVA704 – June 2015
Understanding the I2C Bus
Jonathan Valdez, Jared Becker
2 wire protocol => uses only 2 wires => SCL and SDA
ABSTRACT
2
The I C bus is a very popular and powerful bus used for communication between a master (or multiple
masters) and a single or multiple slave devices. Figure 1 illustrates how many different peripherals may
share a bus which is connected to a processor through only 2 wires, which is one of the largest benefits
that the I2C bus can give when compared to other interfaces.
This application note is aimed at helping users understand how the I2C bus works.
Figure 1 shows a typical I2C bus for an embedded system, where multiple slave devices are used. The
microcontroller represents the I2C master, and controls the IO expanders, various sensors, EEPROM,
ADCs/DACs, and much more. All of which are controlled with only 2 pins from the master.
VCC VCC
VCC
I/O LED I/O
Expanders Blinkers Expanders
RP SCL0 Hub
Repeater
SDA0 Buffer
SCL VCC
Microcontroller Multiplexer /
or Processor SDA Switch
SCL1
SDA1
Data Temperature
EEPROM LCD Driver
Converter Sensor
Figure 1. Example I2C Bus
Trademarks
I²C is a simple, two-wire protocol used for communication between a master (microcontroller) and multiple slave
devices (like sensors, memory chips, and display drivers). The microcontroller controls the communication by
sending addresses and data over the SCL and SDA lines, while each device listens for its address and
responds accordingly. The pull-up resistors ensure proper signal levels, and components like multiplexers and
buffers help manage multiple devices and signal integrity.
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Open-Drain (or Open-Collector): This is a type of output used in digital circuits. When a device wants to send a low signal
(logical 0), it pulls the line to ground. When it wants to send a high signal (logical 1), it doesn't drive the line high but simply "
releases" it, allowing the line to be pulled high by an external resistor (the pull-up resistor).
Electrical Characteristics [Link]
1 Electrical Characteristics
I2C uses an open-drain/open-collector with an input buffer on the same line, which allows a single data line
to be used for bidirectional data flow.
1.1 Open-Drain for Bidirectional Communication
Open-drain refers to a type of output which can either pull the bus down to a voltage (ground, in most
cases), or "release" the bus and let it be pulled up by a pull-up resistor. In the event of the bus being
released by the master or a slave, the pull-up resistor (RPU) on the line is responsible for pulling the bus
voltage up to the power rail. Since no device may force a high on a line, this means that the bus will never
run into a communication issue where one device may try to transmit a high, and another transmits a low,
causing a short (power rail to ground). I2C requires that if a master in a multi-master environment transmits
a high, but see's that the line is low (another device is pulling it down), to halt communications because
another device is using the bus. Push-pull interfaces do not allow for this type of freedom, which is a
benefit of I2C. When no device is actively pulling the line
low, the pull-up resistor ensures that the bus
Slave or Master line is pulled up to the power rail (high
voltage, often referred to as VCC).
RPU
Logic
Figure 2. Basic Internal Structure of SDA/SCL Line
Figure 2 shows a simplified view of the internal structure of the slave or master device on the SDA/SCL
lines, consisting of a buffer to read input data, and a pull-down FET to transmit data. A device is only able
to pull the bus line low (provide short to ground) or release the bus line (high impedance to ground) and
allow the pull-up resistor to raise the voltage. This is an important concept to realize when dealing with I2C
devices, since no device may hold the bus high. This property is what allows bidirectional communication
to take place.
1.1.1 Open-Drain Pulling Low
As described in the previous section, the Open-Drain setup may only pull a bus low, or "release" it and let
a resistor pull it high. Figure 3 shows the flow of current to pull the bus low. The logic wanting to transmit a
low will activate the pull-down FET, which will provide a short to ground, pulling the line low.
SDA/SCL
Slave or Master
RPU
VBUS
VBUS
Logic
V
Time
Figure 3. Pulling the Bus Low With An Open-Drain Interface
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I²C (Inter-Integrated Circuit)
I²C is a two-wire, synchronous, serial communication protocol used for short-distance, low-speed communication between chips on the same board.
Uses SCL (clock) and SDA (data) shared by multiple devices.
Supports multi-master, multi-slave, and address-based communication.
Data is transferred in 8-bit frames with ACK/NACK after each byte.
Bus uses open-drain lines with pull-up resistors allows multiple devices to pull the line low safely.
[Link] I2C Interface
Advantages
Only 2 wires for any number of devices.
1.1.2 Open-Drain Releasing Bus
Supports multiple masters and multiple slaves.
Simple hardware implementation.
When the slave or master wishes to transmit a logic high, it may only release the bus by turning off the
Supports ACK/NACK, making communication reliable.
pull-down FET. This leaves the bus floating, and the pull-up resistor will pull the voltage up to the voltage
Disadvantages
rail, which will be interpreted as a high. Figure 4 shows the flow of current through the pull-up resistor,
Slow data rate (typically up to 400 kHz, some variants up to MHz).
which pulls the bus high.
Requires pull-up resistors power consumption.
Why We Use I²C
For low-speed devices where fast transfer is unnecessary: SDA/SCL
Sensors (temperature, accelerometer)
Saves pins (only 2 wires connect everything).
Important I²C Concepts Interviewers Ask
Slave or Master
1. SDA & SCL (mandatory question)
SDA = Data line
SCL = Clock line RPU
Both are open-drain, require pull-up resistors.
VBUS
VBUS
2. Start & Stop Conditions
START: SDA goes LOW while SCL HIGH
Logic
STOP: SDA goes HIGH while SCL HIGH
V
3. ACK/NACK
After every 8-bit data byte, receiver pulls SDA LOW for ACK.
NACK (SDA HIGH) means data not accepted.
4. Arbitration
Time
If multi-master: Figure 4. Releasing the Bus With An Open-Drain Interface
Master that tries to pull SDA HIGH but sees LOW loses arbitration.
5. Addressing
7-bit or 10-bit 2
address.
2 I C Interface
First byte: Address + R/W bit.
2.1 General I2C Operation
6. Clock stretching
The I2C bus is a standard bidirectional interface that uses a controller, known as the master, to
Slave can hold SCL LOW to slow down the master.
communicate with slave devices. A slave may not transmit data unless it has been addressed by the
Most Important I²C Signals/Symbols
master. Each device on the I2C bus has a specific device address to differentiate between other devices
SDA – Serial Data
that are on the same I2C bus. Many slave devices will require configuration upon startup to set the
SCL – Serial Clock
START / STOP
behavior of the device. This is typically done when the master accesses the slave's internal register maps,
ACK / NACK
R/W bit
which have unique register addresses. A device can have one or multiple registers where data is stored,
written, or read.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and
SCL lines must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is
determined by the amount of capacitance on the I2C lines (for further details, refer to I2C Pull-up Resistor
Calculation (SLVA689). Data transfer may be initiated only when the bus is idle. A bus is considered idle if
both SDA and SCL lines are high after a STOP condition.
The general procedure for a master to access a slave device is the following:
1. Suppose a master wants to send data to a slave:
• Master-transmitter sends a START condition and addresses the slave-receiver
• Master-transmitter sends data to slave-receiver
• Master-transmitter terminates the transfer with a STOP condition
2. If a master wants to receive/read data from a slave:
• Master-receiver sends a START condition and addresses the slave-transmitter
• Master-receiver sends the requested register to read to slave-transmitter
• Master-receiver receives data from the slave-transmitter
• Master-receiver terminates the transfer with a STOP condition
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Inter-Integrated Circuit. Advanced eXtensible Interface
I2C Interface [Link]
2.1.1 START and STOP Conditions
2
I C communication with this device is initiated by the master sending a START condition and terminated
by the master sending a STOP condition. A high-to-low transition on the SDA line while the SCL is high
defines a START condition. A low-to-high transition on the SDA line while the SCL is high defines a STOP
condition.
SCL
ye bana dena bade bhai sanyam
impress ho jaayega maa ki chut
SDA
START Data Transfer STOP
Condition Condition
Figure 5. Example of START and STOP Condition
2.1.2 Repeated START Condition
A repeated START condition is similar to a START condition and is used in place of a back-to-back STOP
then START condition. It looks identical to a START condition, but differs from a START condition
because it happens before a STOP condition (when the bus is not idle). This is useful for when the master
wishes to start a new communication, but does not wish to let the bus go idle with the STOP condition,
which has the chance of the master losing control of the bus to another master (in multi-master
environments).
2.2 Data Validity and Byte Format
One data bit is transferred during each clock pulse of the SCL. One byte is comprised of eight bits on the
SDA line. A byte may either be a device address, register address, or data written to or read from a slave.
Data is transferred Most Significant Bit (MSB) first. Any number of data bytes can be transferred from the
master to slave between the START and STOP conditions. Data on the SDA line must remain stable
during the high phase of the clock period, as changes in the data line when the SCL is high are
interpreted as control commands (START or STOP).
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very very important hai bade bhai
[Link] I2C Interface
SDA line stable while SCL line is high is transmission
SCL
1 0 1 0 1 0 1 0 ACK
SDA
MSB Bit Bit Bit Bit Bit Bit LSB ACK
Byte: 1010 1010 ( 0xAAh )
Figure 6. Example of Single Byte Data Transfer
2.3 Acknowledge (ACK) and Not Acknowledge (NACK)
Each byte of data (including the address byte) is followed by one ACK bit from the receiver. The ACK bit
allows the receiver to communicate to the transmitter that the byte was successfully received and another
byte may be sent.
Before the receiver can send an ACK, the transmitter must release the SDA line. To send an ACK bit, the
receiver shall pull down the SDA line during the low phase of the ACK/NACK-related clock period (period
9), so that the SDA line is stable low during the high phase of the ACK/NACK-related clock period. Setup
and hold times must be taken into account.
When the SDA line remains high during the ACK/NACK-related clock period, this is interpreted as a
NACK. There are several conditions that lead to the generation of a NACK:
1. The receiver is unable to receive or transmit because it is performing some real-time function and is
not ready to start communication with the master.
2. During the transfer, the receiver gets data or commands that it does not understand.
3. During the transfer, the receiver cannot receive any more data bytes.
4. A master-receiver is done reading data and indicates this to the slave through a NACK.
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