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EC-1 Microprocessor Lab Overview

The document outlines a lab project focused on designing and testing the EC-1 microprocessor using the Logisim simulator. It details the construction of the datapath and control unit subcircuits, along with the execution of instructions like JNZ. The lab provided practical experience in microprocessor architecture and troubleshooting circuit issues.

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Than ZIN Thway
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0% found this document useful (0 votes)
7 views5 pages

EC-1 Microprocessor Lab Overview

The document outlines a lab project focused on designing and testing the EC-1 microprocessor using the Logisim simulator. It details the construction of the datapath and control unit subcircuits, along with the execution of instructions like JNZ. The lab provided practical experience in microprocessor architecture and troubleshooting circuit issues.

Uploaded by

Than ZIN Thway
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

EC-1 Microprocessor Lab

Subject: 010153521 Microprocessors


Topic: Designing EC-1 microprocessor

Objective: The objective of this lab is to build, simulate, and test the simple EC-1 general-purpose
microprocessor from scratch using the Logisim digital logic simulator. By the end of this lab, you
will have a functional model of the EC-1, a deep understanding of its datapath and control unit,
and practical experience in translating a microprocessor architecture into a working digital circuit.

Members: Hnin Nu Aye, Theint Watty Htoo, Than Zin Thway

Submitted by

Name: Hnin Nu Aye Name: Theint Watty Htoo Name: Than Zin Thway
Student ID: 6701013610159 Student ID: 6601013620210 Student ID: 6701013610175
Date: 22 Jul 2025 Date: 22 Jul 2025 Date: 22 Jul 2025
Part 1: Building the Datapath Subcircuit

The function of datapath subcircuit


The datapath subcircuit of the EC-1 microprocessor serves as the backbone for instruction
execution, connecting components like the Program Counter (PC), Instruction Register (IR),
Register A, and the ALU. It uses control signals such as IRload, PCload, Aload, INmux, and JNZmux
to direct data flow and operations. Data input and output are handled through multiplexers and
the OutE signal, while ROM provides the instruction stream. Clock and Reset ensure synchronized
operation, and conditional logic like A ≠ 0 supports branching instructions such as JNZ. This
configuration enables step-by-step execution within the EC-1's architecture.
Part 2: Building the Control Unit Subcircuit

The function of control unit


The control unit subcircuit manages instruction execution by generating control signals based on
the current instruction and state. It uses IR bits, clock, and reset inputs to coordinate signals like
IRload, PCload, Aload, INmux, JNZmux, OutE, and Halt. Through its state transitions and logic
components, it directs the datapath to perform fetch, decode, and execute cycles smoothly.
Part 3: Top-Level Integration and Simulation

Description
The EC-1 microprocessor is a general-purpose system built in Logisim, featuring a simple 3-stage
control system (Fetch, Decode, Execute). Its architecture includes a datapath with key
components like the Program Counter (PC), Instruction Register (IR), Register A, ALU, and
Input/Output registers. A finite state control unit generates signals—such as IRload, PCload,
Aload, INmux, JNZmux, OutE, and Halt—based on the current state and instruction bits.
Instructions are stored in a 16×8 ROM and executed synchronously using clock and reset logic.

The way the EC-1 executes the JNZ (Jump Not Zero) instruction
The EC-1 microprocessor executes the JNZ (Jump Not Zero) instruction by first entering the 110
control state, where the control unit activates the JNZmux signal. This signal checks whether the
value in Register A is non-zero using the A ≠ 0 condition. If true, PCload is asserted, causing the
Program Counter (PC) to load the jump target address from the instruction. If false, the PC simply
increments to the next instruction. This conditional branching enables loops and decision-making
in EC-1 programs, making JNZ a key instruction for control flow.

If you want to check how our circuit is running, you can check by our testing video.
Register and Signal Values During Single-Step Execution

step state PC IRload PCload INmux Aload JNZmuz Out Halt

0 Fetch 0000 1 1 0 0 0 0 0
000
1 Decode 0001 0 0 0 0 0 0 0
001
2 Input 0001 0 0 1 1 0 0 0
011
3 Output 0001 0 0 0 0 0 1 0
100
4 Dec 0001 0 0 0 1 0 0 0
101
5 JNZ 0001 0 1 0 0 1 0 0
110 If A != 0
6 Halt 0001 0 0 0 0 0 0 1
111

Conclusion
This lab gave us useful experience building and testing the EC-1 microprocessor in Logisim. We
connected key parts like the datapath, control unit, and ROM, and used single-step simulation to
see how each instruction worked. We learned how JNZ uses control signals and checks if Register
A is not zero to control program flow. During the lab, we had some problems with the circuit
showing wrong numbers. With help from friends, we found out it was caused by using incorrect
reset buttons and mistakes in our logic equations. After fixing those, the circuit worked correctly.
Overall, the lab helped us apply what we learned in class to a working digital system.

If you want to explore more, such as circuit and source files, visit here >>

Submitted on
22 Jul 2025

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