Combinational Circuit Design Exercises
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Exercise-4.1
Let there be a combinational circuit with 5 input lines and 3 output lines, as shown in the figure.
below.
The operation is as follows:
When a single input line among E, E, E, E is at a high level, its number is
0 1 2 3
coded in binary on outputs BA.
If multiple lines are simultaneously at a high level, the circuit encodes the highest number.
If all input lines are at low level, the circuit codes BA=00, but is indicated by E =1
OUT
that this code is not validated. In all other cases E =0.
OUT
The operation described so far was observed when E = 1.
IN
If E = 0, we have: B = A = E =0.
IN OUT
1- Provide the truth table of the encoder.
2- Donner les expressions logiques des sorties A, B et E depending on the inputs of E ...E and
OUT 0 3
E .
IN
3- Deduce the logical circuit of the encoder.
4- How can an 8-input priority encoder be obtained from two encoders and some
necessary logic gates.
Solution
1) The truth table of the encoder:
2) The logical expressions of outputs A, B, and E OUT according to the inputs
And ... and and :
0 3 IN
3) The flowchart of the encoder is provided by the applet.
[Link]
4) One can obtain an 8-input and 3-output encoder by cascading
two coders, connecting the output EOUT of one to the input EIN of the other with 3
logic gates at the outputs, as shown in the figure below:
- If E IN
= 0, the encoder-2 is invalid, its output E OUT2=0 makes the encoder-1 invalid
also. At the output Z=Y=X=0.
1, the encoder-2 is validated, its output EOUT2=0 makes the coder-1 invalid. If
If E = IN
a touch of the coder-2 is activated, we get its code at the output: Z=1, Y=B 2
X=A2.
If E =IN
1, the encoder-2 is validated, but none of its input keys is activated.
so E OUT2=1 makes the encoder-1 valid. If a key on the encoder-1 is activated, we
receives its code at the output: Z=0, Y=B,1 X=A. 1If no keys from both
the coders are not activated, we get the output: Z=Y=X=0
Exercise-4.2
How can we obtain a 24-output decoder using three 74138 decoders with 8 outputs?
do not use any outside door.
Solution
By using the validation inputs of the 74138 decoder, one can obtain a
24-output decoder. The table below shows the validation of the decoders in
function of high weight bits E and D.
[Link]
Exercise-4.3
Consider the arrangement of the figure below, made from three multiplexers MUX-1, MUX-2 and
MUX-3 each with 4 inputs.
1-Give the logical expression of Z in terms of A, B, C, D, and E.
2-Write this expression using only exclusive ORs.
Solution
Exercise-4.4
We want to create an electronic die with LED diodes arranged as shown in figure-1.
The different display combinations of the electronic die are represented in Figure-2.
For example, if you want to display 2, you need to light up the diodes a and g.
We want to create the logical control circuit to turn on the diodes. This circuit must contain 7
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outputs, one output per diode (a, b, c, d, e, f, g) and 3 inputs A, B, C for the binary code.
1- Determine the truth table.
2- Determine the simplified expressions of the outputs (a, b, c, d, e, f, g) in terms of inputs A, B and
C.
3- Provide the logical control circuit.
Solution
1- The truth table
It is noted that for the input combinations 0 (000) and 7 (111), no diode should be
to be lit.
2- We simplify the logical expressions of a, b, c, d, e, f, and g with
the Karnaugh table.
Exercise-4.5
Figure-1 represents a comparator of two binary numbers x and y of 1 bit.
i i
1- Carry out the synthesis of this logic circuit.
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2- We want to create a comparator for two binary numbers of three bits X=x x x and Y=y y y, whose
2 1 02 1 0
The synoptic diagram is given by figure 2. It is noted that x and y are the most significant bits.
0 0
weak.
a- Donner les expressions logiques des sorties S, I et E en fonction des sorties S , I , E avec i=0, 1, 2
i i i
the 1-bit comparator.
b- Deduce the internal diagram of the 3-bit comparator.
3- We want to display the outputs of the comparator (S, I, E) on a 7-segment display with cathodes.
communicate using a transcoder, as shown by the figure-3a, and this to obtain the display
given by figure-3b.
a- Provide the transcoding table for converting the S, I, E code to the 7-segment code.
B-- Deduce the internal diagram of the transcoder.
Solution
1- The truth table of a comparator for two binary numbers x and
i y,
i each 1 bit, is
the following:
[Link]
The logical expressions of the comparator outputs based on the inputs xi and yi
are:
Based on the above expressions, the logical circuit of the 1-bit comparator is
given by the applet
2-a- To compare two 3-bit binary numbers X=x x x2 and 1 0 Y=y y 2y,1 you
0 need to
compare bit by bit, starting with the most significant bits, if they are
we move to the bits of immediately lower weight and so on.
- X>Y if :
x2 > y2 ( 2S = 1)
or x 2 = y2 ( E
2 = 1) and
1 x1 > 1y ( S = 1)
you x2 = 2y ( 2E = 1) and
1 x1 = 1y ( E = 0 1) 0and 0 x > y ( S = 1)
from: S = S +2 E . S2 + 1E2. E1. S0
- X<Y if :
x2 < y2 ( 2I = 1)
or x 2 = y2 ( E
2 = 1) and
1 x1 < 1 y ( I = 1)
x = 2y ( 2 E =2 1) and 1x =1 y 1( E = 1)0 and0 x 0 < y (I = 1)
from: I = I +2 E .I2+ E
1 2.E .I1 0
- X = Y if :
x2 = y2 ( 2E = 1) and
1 x1 = 1y ( E =0 1) 0and0 x = y ( S = 1)
where: E = E2 .E1.E 0
The internal diagram of the 3-bit comparator is provided by the applet.
3-a- The transcoding table:
[Link]
The expressions of a, b, c, d, e, f, g in terms of S, I, E can be derived from the table of
transcoding as follows:
a=d=g=S+E=
b=0
c=S
e=I+E=
f=S+I+E=1
The following applet provides the complete schematic of the 3-bit comparator along with its circuit.
display