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RISC vs CISC: Key Differences Explained

The document compares Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computer (CISC) architectures, highlighting their fundamental differences in instruction complexity and execution. RISC simplifies hardware with fewer, simpler instructions that execute in a single clock cycle, while CISC uses complex instructions that can perform multiple tasks but may take longer to execute. Both architectures aim to enhance CPU performance, with RISC focusing on reducing cycles per instruction and CISC minimizing the number of instructions per program.

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Mridul Ghosh
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5 views2 pages

RISC vs CISC: Key Differences Explained

The document compares Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computer (CISC) architectures, highlighting their fundamental differences in instruction complexity and execution. RISC simplifies hardware with fewer, simpler instructions that execute in a single clock cycle, while CISC uses complex instructions that can perform multiple tasks but may take longer to execute. Both architectures aim to enhance CPU performance, with RISC focusing on reducing cycles per instruction and CISC minimizing the number of instructions per program.

Uploaded by

Mridul Ghosh
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd

RISC and CISC

Reduced Set Instruction Set Architecture (RISC) –


The main idea behind is to make hardware simpler by using an instruction set
composed of a few basic steps for loading, evaluating and storing operations just like
a load command will load data, store command will store the data.
Complex Instruction Set Architecture (CISC) –
The main idea is that a single instruction will do all loading, evaluating and storing
operations just like a multiplication command will do stuff like loading data,
evaluating and storing it, hence it’s complex.
Both approaches try to increase the CPU performance
 RISC: Reduce the cycles per instruction at the cost of the number of
instructions per program.
 CISC: The CISC approach attempts to minimize the number of instructions per
program but at the cost of increase in number of cycles per instruction.
Earlier when programming was done using assembly language, a need was felt to make
instruction do more task because programming in assembly was tedious and error prone
due to which CISC architecture evolved but with uprise of high level language dependency
on assembly reduced RISC architecture prevailed

Characteristic of RISC –
1. Simpler instruction, hence simple instruction decoding.
2. Instruction come under size of one word.
3. Instruction take single clock cycle to get executed.
4. More number of general purpose register.
5. Simple Addressing Modes.
6. Less Data types.
7. Pipeling can be achieved.
Characteristic of CISC –
1. Complex instruction, hence complex instruction decoding.
2. Instruction are larger than one word size.
3. Instruction may take more than single clock cycle to get executed.
4. Less number of general purpose register as operation get performed in memory
itself.
5. Complex Addressing Modes.
6. More Data types.
Example – Suppose we have to add two 8-bit number:
 CISC approach: There will be a single command or instruction for this like ADD
which will perform the task.
 RISC approach: Here programmer will write first load command to load data in
registers then it will use suitable operator and then it will store result in desired
location.
So, add operation is divided into parts i.e. load, operate, store due to which RISC
programs are longer and require more memory to get stored but require less
transistors due to less complex command.
Difference –
RISC CISC

Focus on software Focus on hardware

Uses both hardwired and micro

Uses only Hardwired control unit programmed control unit

Transistors are used for storing

Transistors are used for more complex

registers Instructions

Fixed sized instructions Variable sized instructions

Can perform only Register to Register Can perform REG to REG or REG to

Arthmetic operations MEM or MEM to MEM

Requires more number of registers Requires less number of registers

Code size is large Code size is small

A instruction execute in single clock Instruction take more than one clock

cycle cycle

Instruction are larger than size of one

A instruction fit in one word word

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