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EE8461 Integrated Circuits Lab Exam 2024

The document outlines the practical end semester examination for the B.E/B.Tech/B.Arch Fourth Semester in April/May 2024, specifically for the EE8461 Linear and Digital Integrated Circuits Laboratory. It includes a list of questions that require students to design and implement various digital circuits and systems using logic gates and flip-flops, with a maximum score of 100 marks. The examination consists of practical tasks such as creating multiplexers, counters, and converters, along with verification of truth tables and circuit functions.

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15 views2 pages

EE8461 Integrated Circuits Lab Exam 2024

The document outlines the practical end semester examination for the B.E/B.Tech/B.Arch Fourth Semester in April/May 2024, specifically for the EE8461 Linear and Digital Integrated Circuits Laboratory. It includes a list of questions that require students to design and implement various digital circuits and systems using logic gates and flip-flops, with a maximum score of 100 marks. The examination consists of practical tasks such as creating multiplexers, counters, and converters, along with verification of truth tables and circuit functions.

Uploaded by

vijayarunagiri2383
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd

B.E / [Link]./[Link].

PRACTICAL END SEMESTER EXAMINATIONS, APRIL / MAY 2024


Fourth Semester

EE8461 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

(Regulations 2017)

Time : 3 Hours Answer any one Question Max. Marks 100

Aim/Principle/Apparatus Tabulation/ Calculation Viva-Voce Record Total


required/Procedure Circuit/Program/ & Results
Drawing
30 30 20 10 10 100

[Link]. Questions

1. Simplify the following logical description using K-map and implement using any suitable logic
gates

F (A,B,C,D) = Σ (3,4,5,7,9,13,14,15)

2. (a) Design and implement 4x1 Multiplexer by using suitable logic gates & verify its truth table

(b) Design and construct Full adder by using suitable logic gates & verify its truth table.

3. (a) Design and implement 1x4 demultiplexer by using suitable logic gates & verify its truth table

(b) Design and construct Full subtractor by using suitable logic gates & verify its truth table.

4. (a) Design and implement a binary to gray code converter using suitable logic gates and verify their
function.

(b) Design and implement 4x2 encoder using suitable logic gates and verify its truth table.

5. (a) Design and implement a gray to binary code converter using suitable logic gates and verify their
function.

(b) Design and implement 2x4 decoder using suitable logic gates and verify its truth table.

6. Design and implement an asynchronous/ripple 4-bit binary up counter using JK flip flops.

7. Design and implement an asynchronous/ripple 4-bit binary down counter using JK flip flops.

8. Design and implement an asynchronous/ripple 4-bit decimal (BCD) up counter using JK flip flops.

9. Design and implement an asynchronous/ripple 4-bit decimal (BCD down counter using JK flip flops.

10. Design and implement a 4 bit synchronous binary up counter using JK flip flops.
11. Design and implement a 4 bit synchronous binary down counter using JK flip flops.

12. (a) Design & construct a 4 bit Serial in serial out shift register.

(b) Design and implement a Differentiator using an op-amp.

13. (a) Design & construct a 4 bit Serial in parallel out shift register.

(b) Design and implement Integrator using an op-amp.

14. Design & construct a 4 bit Parallel in serial out shift register.

15. Design & construct a 4 bit Parallel in parallel out shift register.

16. (a) Design and verify the experimental and theoretical loop gains of amplifiers using IC 741 in the
inverting and non-inverting modes.

(b) Design and implement a circuit and study the operation of 741 op-amp as comparator.

17. Design and implement Differentiator and Inverting summing amplifier.

18. Construct Astable multivibrator using IC555 timer & to generate a 1KHz square waveform.

19. Construct a circuit Operate the IC555 timer in Monostable mode to generate a 1KHz square
waveform.

20. Construct a circuit to study the operation of NE565 PLL and to use it as frequency multiplier.

21. Design and implement a digital to analog converter using weight resistor method and R-2R ladder
method.

INTERNAL EXAMINER EXTERNAL EXAMINER

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