Scribd
Upload
9 views13 pages

Verilog Behavioral Modeling Guide

The document provides an overview of Verilog behavior modeling, detailing various modeling styles including structural, data-flow, and behavior models. It explains structured procedures, sensitivity lists, procedural assignments, and various procedural statements such as if-else, case, and loops. Additionally, it includes examples of a multiplexer, D flip-flop, and counter, along with resources for further learning.

Uploaded by

Soumick Chakraborty
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
9 views13 pages

Verilog Behavioral Modeling Guide

The document provides an overview of Verilog behavior modeling, detailing various modeling styles including structural, data-flow, and behavior models. It explains structured procedures, sensitivity lists, procedural assignments, and various procedural statements such as if-else, case, and loops. Additionally, it includes examples of a multiplexer, D flip-flop, and counter, along with resources for further learning.

Uploaded by

Soumick Chakraborty
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Verilog: Behavior modeling

Neeraj Goel
Verilog Modelling style
• Structural model
• Data-flow model
• Behavior model
Structured procedures
• Behavior statement can appear only in
structured procedures
– always
• Either sensitivity list
• Or delay in statements
– initial
• Statements are executed sequentially
Example
initial
clock = 1’b0;

always
#10 clock = ~clock;

initial
#1000 $finish
Sensitivity list
• When should always always @(events) begin
...
block trigger //list of statements
...
– List of events end

• Events always @(a)

– Signal name always @(posedge a)

– posedge/negedge always @(a or b)

– or operator
– @(*)
Procedure assignments
• Data-types that can be updated (written)
– reg, int, real, time, or memory element
• Two type of assignments
– Blocking assignments
• Variable_lvalue = [delay] expression
• Example: sum = #10 a ^ b ^ c;
– Non-blocking assignment
Example:
Sum <= #10 a ^ b ^ c
Cout <= #12 (a & b) | (a & c) | (b & c)
Procedural statements: if else
Type 1 Type 3
if( alu_control == 0)
if( !lock) buffer = data;
y = x + y;
if( enable) out = in; else if(alu_control == 1)
Type 2 y = x –y;
if(number_queue < DEPTH) else if(alu_control == 2)
y = x+1;
begin
else
data_queue = data; $display(“Invalid
number_queue = control”);
number_queue + 1;
end
Procedural statement: case
case(alu_control) Use of “begin” and “end”
2’b00: y = x + y; - When multiple statements are to be grouped
Default:
2’b01: y = x – y; - There is a possibility of x and z in alu_control
2’b10: y = x + 1;
casex and casez
2’b11: y = y + 1; case items can have x or z for don’t cares
default:
endcase
Procedural statements: loops
• While loop • Repeat loop
Count = 0; Count =0;
While(count < 128) begin repeat(128) begin
Count = Count + 1; Count = Count + 1;
$display(“%d”, count); $display(“%d”, Count);
end end
• For loop • Forever loop
for(count =0; count < 128; initial begin
count = count + 1) clock = 1’b0;
$display(“%d”, count); forever #10 clock = ~clock;
end
Example: Multiplexer
module(out,i0, i1, i2, i3, s0, s1);
output out;
input i0, i1, i2, i3, s0, s1;
reg out;
always @(*) begin
case ({s1,s0} )
2b’00: out = i0;
2b’01: out = i1;
2b’10: out = i2;
2b’11: out = i3;
Default: out = 1’bx
endcase
end
endmodule
Example: D flip-flop
//level sensitive latch with //positive edge triggered DFF
asynchronous reset with asynchronous reset
always @(reset, clock, d) always @(posedge clock or
negedge reset)
begin
begin
if(reset) if(!reset)
q = 1’b0; q = 1’b0;
else if(clock) else
q = d; q = d;
end end
Example: counter
module counter(Q, clock, clear)
output [3:0] Q;
input clock, clear;
reg [3:0] Q;
always @(posedge clear or negedge clock)
begin
if(clear)
Q <= 4’d0;
else
Q <= Q + 1;
end
endmodule
Summary
• Where to use behavior procedures
• Synthesizable constructs
• Verilog vs C programming
• More resources
– [Link]
– [Link]
esign_verilog_introduction.htm
– [Link]

You might also like