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MODULE 5
Sequential Circuit Design
Asynchronous inputs allow the flip-flop to be directly set or directly cleared
without having to wait for the active edge of the clock
They are generally provided in a flip-flop for the sake of initialisation (after
switching on the d-c power supply) and for other asynchronous
requirements.
A given flip-flop may have one or both of these asynchronous inputs, which
are generally labelled as SD (Set Direct) and RD (cleaR Direct).
The positive-logic and negative-logic conventions are followed for these
inputs also as for the clock input, a negative-logic input being indicated by a
small circle at the respective input(s) in the flip-flop symbol.
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Clear/reset/RD preset/set/SD
Clear and Preset set flip-flop to a known state
Used at startup, reset
Clear or Reset to a logic 0
Asynchronous: Q=0 when reset is asserted
Doesn't wait for clock
Quick but dangerous
Preset or Set the state to logic 1
Asynchronous: Q=1 when reset is asserted
Doesn't wait for clock
Quick but dangerous
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positive-logic
negative-logic
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Qn+1
𝑫 𝑫 S R
0 0 x x NOT ALLOWED
0 1 x x 1
1 0 x x 0
1 1 S R NORMAL OPERATION
OF FLIP FLOP
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S R NORMAL OPERATION
SD RD OF FLIP FLOP
0 0 S R NORMAL
OPERATION OF
FLIP FLOP
0 1 x x 0
1 0 x x 1
1 1 x x NOT ALLOWED
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𝑺𝑫
𝑅𝑫
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J K Qn+1
0 0 HOLD ( 𝒏)
0 1 0
1 0 1
Negative
Logic Clock 1 1 TOGGLE ( 𝒏
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Q(n+1) = JQn’ + K’Qn
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Timing Diagram for
Timing Diagram for
negative-edge triggered
positive-edge triggered
J-K flip-flop
J-K flip-flop
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In the level triggered JK when, when both J and K input are 1 and
when the ON time of the clock is more than the propagation delay of
the flip-flop then the output of the flip-flop will toggle continuously
between ‘1’ and ‘0’.
And because of that, it is difficult to predict the output once the clock
becomes low.
The race around condition in undesirable condition and should be
avoided to get the reliable output.
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The problem of race-around condition and the uncertainty of output can be avoided by:
i) Increasing the delay of the flip-flops. For that, the delay of the flip-flops must be greater than
the duration of the clock signal, i.e. Δt > T.
ii) In another way, the duration of the applied clock signal (T) must be reduced to make it
less than the delay of the flip-flops (Δt).
However, the increase in the delay of the flip-flops is not a good practice because it decreases
the speed of the system.
On the other hand, it is also quite difficult to decrease the duration of the clock pulse (T)
beyond the delay of the flip-flops (Δt). This is because, the delay of the JK flip-flops (Δt) is of
the order of nanoseconds.
Hence, the most practical way to solve the problem of race-around condition in JK is to use
the JK flip-flops in the Master and Slave Mode.
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• Above figure, it consist of two gated latches.
• The first latch act as a master latch and the second latch act as a slave latch.
• The output of the master latch is connected to the slave latch.
• The Q’ output of the slave latch is connected back to the master latch where J input is
applied and similarly, Q output is connected back where the K input is applied.
• The clock signal to the slave latch is applied through an inverter.
• When clock signal is high then master is enabled and slave is disabled. And similarly,
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when clock is low then slave is active and master is disabled.
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slave latch is following the master output during
the off time of the clock
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Full name: Toggle flip-flop
Output toggles when input is asserted
If T=1, then Q Q' when CLK
If T=0, then Q Q when CLK
Input Q Input(t) Q(t) Q(t +1)
T Q
0 0 0
> 0 1 1
1 0 1
CLK 1 1 0
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• For many applications, e.g. ripple counters one needs the actions dependent on Qn.
• The T flip-flop utilises half of the capability of a J-K flip-flop, operating only
either in the HOLD mode or in the TOGGLE MODE.
T Qn+1
0 Hold (Qn)
Negative Edge
TOGGLE (
Triggered T 1
flip-flop and
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T Qn+1
0 Hold Qn
TOGGLE (
1
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Timing Diagram of a POSTIVE-edge triggered T flip-flop
1 1 1
0
1 1 1 1 1
0 0 0
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Qn Qn+1 J K Qn Qn+1 S R
0 0 0 X 0 0 0 X
0 1 1 X 0 1 1 0
1 0 X 1 1 0 0 1
1 1 X 0 1 1 X 0
Qn Qn+1 D Qn Qn+1 T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
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• The J-K flip-flop is the most versatile and is as such most widely used in a variety of applications.
• The S- R flip-flop finds limited use as it can always be replaced by a J-K flip-flop.
• The D flip-flop is extensively used for data storage (hence the name D), as the data applied at D is
directly stored at every clock pulse.
• The T f lip-flop is convenient for making simple counters, as its output can toggle for every clock
pulse, thus keeping track of the number of clock pulses received.
• Flip-Flops can be positive edge triggered or negative edge triggered.
• Latches can be Active High or Active Low enabled.
• There are asynchronous inputs SD or RD or both and can be active high or active low.
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Feature Edge-Triggered Flip-Flop Master-Slave Flip-Flop
Behaves as edge-triggered
Responds on clock edge
Triggering using two latches (master-
(rising or falling)
slave)
Faster, as it is a single- Slower, as it involves two
Speed
stage mechanism stages
Higher power consumption
Power Consumption Lower power consumption
due to two latches
More complex (two-stage
Design Complexity Simpler (single-stage) with master and slave
latches)
High, as it ignores input Higher due to two-stage
Noise Immunity
during clock levels latching
Used when precise edge
Used in high-speed circuits,
Application triggering and stability are
synchronous systems
required
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