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Switching Theory Exam Paper May 2025

This document is an examination question paper for the Switching Theory and Logic Design course, intended for II B.Tech I Semester students, with a maximum score of 70 marks. It consists of two parts: Part A with 10 short answer questions and Part B with 5 long answer questions, covering various topics such as Boolean functions, circuit design, and flip-flops. The exam is scheduled for May 2025 and includes specific instructions for answering the questions.

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JYOTHI S
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10 views2 pages

Switching Theory Exam Paper May 2025

This document is an examination question paper for the Switching Theory and Logic Design course, intended for II B.Tech I Semester students, with a maximum score of 70 marks. It consists of two parts: Part A with 10 short answer questions and Part B with 5 long answer questions, covering various topics such as Boolean functions, circuit design, and flip-flops. The exam is scheduled for May 2025 and includes specific instructions for answering the questions.

Uploaded by

JYOTHI S
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

SRK23 SET - 1

Sub Code: 23EC3T03


II [Link] I Semester Regular Examinations, May-2025
SWTCHING THEORY AND LOGIC DESIGN
(ECE)
Time: 3 hours Max Marks: 70M
----------------------------------------------------------------------------------------------
Note: 1. Question paper consists of two parts (Part A and Part B)
2. Answer all the questions from Part A
3. From Part-B, Answer Five Questions and One Question from Each Unit
PART – A 10 X 2 = 20 M
CO BTL Marks
Simplify the following:
i) F = (A+ AC + B)
1. a) CO1 L4 2M
ii) F = AB(C +C) + AB
iii) F = (X +Y )(X + Z )
b) State De-Morgan theorems CO1 L1 2M
c) Write Excess-3 code for decimal 7 CO2 L1 2M
d) Write advantages of parallel adder. CO2 L1 2M
e) Difference between PROM and PLA? CO3 L4 2M
f) Define a combinational logic circuit CO3 L1 2M
g) What is a race-around condition in JK flip-flop CO4 L2 2M
Write the difference between Serial – in – serial – out and parallel – in
h) CO4 L1 2M
–parallel – out registers.
i) What is a state diagram? CO5 L2 2M
j) Define an ASM chart. CO5 L1 2M
PART – B 5 X 10 = 50 M
UNIT - I
Simplify the Boolean function using K map technique draw the circuit
2. CO1 L3 10 M
with NOR only. F = π M (3, 4, 6, 7, 11, 12, 13, 14, 15).
(OR)
Given the 4 bit data word 1011, generate the hamming code that
3. corrects and detects single errors and also explain the error correction CO1 L4 10 M
capability
UNIT – II
Draw the circuit diagram of a 4-bit adder-subtractor and briefly
4. CO2 L3 10 M
describe its functional principles.
(OR)
5. Design a code converter from Binary to Gray code. CO2 L6 10 M
UNIT – III
6. Design a priority encoder using logic gates. CO3 L6 10 M

Page 1 of 2
(OR)
Explain the working of a Multiplexer& De-multiplexer with the help
7. CO3 L2 10 M
of an example.
UNIT – IV
a) Explain about the master – slave JK flip flop. CO4 L2 7M
8. Draw and explain the characteristic table and equation of a SR flip-
b) CO4 L3 3M
flop
(OR)
9. Explain the operation of a 4-bit shift register CO4 L2 10 M
UNIT – V
10. Design a sequence generator that produces a given binary sequence
(e.g., 1011). CO5 L6 10 M

(OR)
11. Draw and explain the state diagram of a JK flip-flop. CO5 L3 10 M

*** End of the Question Paper ***

Page 2 of 2

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