Sequential Logic Circuit

Digital logic Design  The logic circuits whose outputs at any instant of time depend on the present
inputs as well as on the past outputs are called sequential circuits.
Chapter Five  In sequential circuits, the output signals are fed back to the input side.
 A memory element is a medium in which one bit of information (0 or 1) can

Sequential Logic Circuit be stored. or retained until necessary, and thereafter its contents can be
replaced by a new value.
The contents of memory elements can be changed by the outputs of
by combinational circuits
Dagnachew M. that are connected to its input

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Sequential Circuits Latches and Flip-Flop

 Asynchronous 
3 Basic 1-bit digital memory circuit is known as a flip flop.
Inputs Outputs
Combinational  It can have only two states, either the 1 state or the 0 state.
Circuit
Memory
Elements  A flip-flop is also known as a bistable multi vibrator.

 Flip-flops can be obtained by using NAND or NOR gates.

 Synchronous
 Flip-flop is It has one or more inputs and two outputs.
Inputs Outputs
Combinational
Circuit  The two outputs are complementary to each other.
Flip-flops
Clock

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 Latches and Flip-Flop…. . Latches
 Q and Q' cannot be at the same state simultaneously.
 SR Latch
S R Q0 Q Q’
 If it happens by any chance, it violates the definition of a flip-flop
0 0 0 0 1
Q = Q0
and hence is called an undefined condition. 0 0 1 1 0
0 1 0 0 1
 The state of Q is called the state of the flip-flop, whereas the
1 10 0 1 1 0 1
Q=0

1 0 0 1 0
Q=1
state of Q' is called the complementary state of the flip-flop. 1 0 1 1 0
1 1 0 0 0 Q = Q’
 Latch are basically similar to flip-flop. 1 1 1 0 0 Q = Q’

 The difference between latch and flip-flop is in the method used 1 0

for changing their state.

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Latches Latches

 SR Latch  SR Latch
S R Q S R Q
0 0 Q0 No change 0 0 No change
Q0
0 1 0 Reset 0 1 0 Reset
1 0 1 Set 1 0 1 Set
1 1 Q=Q’=0 Invalid 1 1 Q=Q’=0 Invalid

S R Q S’ R’ Q
0 0 Q=Q’=1 Invalid 1 1 Q0 No change
0 1 1 Set 1 0 0 Reset
1 0 0 Reset 0 1 1 Set
1 1 Q0 No change 0 0 Q=Q’=1 Invalid
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 Controlled Latches Controlled Latches

 SR Latch with Control Input  D Latch (D = Data) Timing Diagram

C

C S R Q t
0 x x Q0 No change C D Q
Output may
1 0 0 Q0 No change 0 x Q0 No change change
1 0 1 0 Reset 1 0 0 Reset
1 1 0 1 Set 1 1 1 Set
1 1 1 Q=Q’ Invalid
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Controlled Latches The difference between latch and flip flop

 D Latch (D = Data) Timing Diagram  Controlled latches are level-triggered

C
C
D

Q  Flip-Flops are edge-triggered

CLK Positive Edge

C D Q Output may
0 x Q0 No change change
CLK Negative Edge
1 0 0 Reset
1 1 1 Set

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 Flip-Flops Flip-Flops
Master-Slave D Flip-Flop
 Master-Slave D Flip-Flop
 The construction of a D flip-flop with two D latches and an inverter is
shown in Fig. below D D Q D Q Q
D Latch D Latch
The first latch is called the master and the second the slave. (Master) (Slave)
C C
 When the clock is 0, the output of the inverter is 1. The slave latch is
Master Slave
enabled, and its output Q is equal to the master outputY . The master latch CLK
CLK
is disabled because Clk = 0.

 When the input pulse changes to the logic-1 level, the data D
from the external D input are transferred to the master. The slave, Looks like it is negative
edge-triggered QMaster
however, is disabled as long as the clock remains at the 1 level, because its
enable input is equal to 0. QSlave
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Flip-Flops Flip-Flops

Characteristic equation of a D flip-flop is  JK Flip-Flop

C D Q

0 x Q0 Q(t+1) = D.
1 0 0
1 1 1

J Q
D = JQ’ + K’Q
K Q
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 Flip-Flops Flip-Flop Characteristic Tables

 T Flip-Flop D Q(t+1)
D Q
0 0 Reset
Q 1 1 Set
T J Q T D Q
J K Q(t+1)
Q J Q 0 0 Q(t) No change
K Q
0 1 0 Reset
K Q 1 0 1 Set
T Q 1 1 Q’(t) Toggle
D = JQ’ + K’Q
T Q T Q(t+1)
D = TQ’ + T’Q = T  Q Q
0 Q(t) No change
Q Toggle
1 Q’(t)
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Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations

D Q(t+1)
 Analysis / Derivation
D Q
0 0 Q(t+1) = D J K Q(t) Q(t+1)
Q 1 1 0 0 0 0 No change
J Q 0 0 1 1
J K Q(t+1) 0 1 0 0
J Q Reset
0 0 Q(t) 0 1 1 0
0 1 0 Q(t+1) = JQ’ + K’Q K Q
1 0 0 1 Set
K Q 1 0 1 1 0 1 1
1 1 Q’(t) 1 1 0 1 Toggle
T Q 1 1 1 0
T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q
1 Q’(t)
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 Flip-Flop Characteristic Equations Excitation Table of a Flip-Flop

 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
J Q 0 0 1 1 K
0 1 0 0 0 1 0 0
0 1 1 0 J 1 1 0 1
K Q Q
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Q(t+1) = JQ’ + K’Q

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INTERCONVERSION OF FLIP-FLOPS Example 1

Convert S-R Flip-flop to D Flip-flop

 In many applications, we are being given a type of flip-flop, whereas we may

require some other type.

 To design the conversion logic we need to combine the excitation table

for both flip-flops and make a truth table with data input(s) and Q as the

inputs and the input(s) of the given flip-flop as the output(s)

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Example 2 Convert S-R Flip-flop to a J-K Flip-flop Example 3 Convert S-R Flip-flop to a T Flip-flop

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Exercise
1. Convert D Flip-flop to an S-R, to J-K and to T Flip-flop

2. Convert J-K Flip-flop to a D and T Flip-flop

3. Convert T Flip-flop to an S-R, to J-K and to D Flip-flop

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