University of Diyala
College of Science
Department of Computer Science
Computer Organization
and Architecture
Second Class
Second Term
Chapter THREE
I/O ORGANIZATION
Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
3-1 Introduction
The important components of any computer system are processor, memory, and
I/O devices (peripherals). The processor fetches instructions (opcodes and
operands/data) from memory, processes them and stores results in memory. The other
components of the computer system (I/O devices) may be loosely called the Input/
Output system. The main function of I/O system is to transfer information between
processor or memory and the outside world.
The important point to be noted here is, I/O devices (peripherals) cannot be
connected directly to the system bus. The reasons are discussed here.
• A variety of peripherals with different methods of operation are available. So it
would be impractical to incorporate the necessary logic within the processor to
control a range of devices.
• The data transfer rate of peripherals is often much slower than that of the memory
or processor. So it is impractical to use the high speed system bus to communicate
directly with the peripherals.
• Generally, the peripherals used in a computer system have different data formats
and word lengths than that of processor used in it.
So to overcome all these difficulties, it is necessary to use a module in between
system bus and peripherals, called I/O module or I/O system.
The Input /Output system has two major functions:
• Interface to the processor and memory via the system bus,
• Interface to one or more I/O devices by tailored data links
For clear understanding refer Figure 3.1, Links to peripheral devices are used to
exchange control, status and data between the I/O system and the external devices.
An important point that is to be noted here is, an I/O system is not simply mechanical
connectors for connecting different devices required in the system to the system bus.
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
Figure 3.1 Generic Model of computer system
It contains some logic for performing function of communication between the
peripheral (I/O device) and the bus. The I/O system must have an interface internal
to the computer (To the processor and memory) and an interface external to the
computer (to the external I/O devices).
3-2 Requirements of I/O System
The I/O system if nothing but the hardware required to connect an I/O device to the
bus. It is also called I/O interface. The major requirements of an I/O interface are:
1. Control and timing
2. Processor communication
3. Device communication
4. Data buffering
5. Error detection
All these requirements are explained here. The I/O interface includes a control and
timing requirements to co-ordinate the flow of traffic between internal resources
(memory system bus) and external devices. Processor communication involves
different types of signal transfers such as
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
• Processor sends commands to the I/O system which are generally the control
signals on the bus.
• Exchange of data between the processor and the I/O interface over the data bus.
• The data transfer rate of peripherals is often much slower than that of the processor.
So it is necessary to check whether peripheral is ready or not for data transfer. If
not, processor must wait. So it is important to know the status of I/O interface. The
status signals such as BUSY, READY can be used for this purpose.
• A number of peripheral devices may be connected to the I/O interface. The I/O
interface controls the communication of each peripheral with processor. So it must
recognize one unique address for each peripheral connected to it.
The I/O interface must able to perform device communication which involves
commands, status information and data. Data buffering is also an essential task of an
I/O interface. Data transfer rates of peripheral devices are quite high than that of
processor and memory. The data coming from memory or processor are sent to an
I/O interface, buffered and then sent to the peripheral device at its data rate. Also,
data are buffered in I/O interface so as not to tie up the memory in a slow transfer
operation. Thus the I/O interface must be able to operate at both peripheral and
memory speeds. I/O interface is also responsible for error detection and for reporting
error detection and for reporting errors to the processor. The different types of errors
are mechanical, electrical malfunctions reported by the device such as bad disk track,
unintentional changes to the bit pattern, transmission errors etc. To fulfill all these
requirements the important blocks necessary in any I/O interface are shown in Figure
3.2.
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
Figure 3.2: Block diagram of I/ O interface
As shown in the Figure 3.2, I/O interface consists of data register, status control
register, address decoder and external device interface logic. The data register holds
the data being transferred to or from the processor. The status/control register
contains information relevant to the operation of the I/O device. Both data and status
/control registers are connected to the data bus. Address lines drive the address
decoder. The address decoder enables the device to recognize its address when
address appears on the address lines. The external device interface logic accepts
inputs from address decoder, processor control lines and status signal from the I/O
device and generates control signals to control the direction and speed of data transfer
between processor and I/O devices.
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
(a) I/O interface for input device
(b) I/O interface for output device
Figure 3.3: I /O Interface
The Figure [Link] the I/O interface for input device and output device. Here, for
simplicity block schematic of I/O interface is shown instead of detail connections.
The address decoder enables the device when its address appears on the address lines.
The data register holds the data being transferred to or from the processor. The status
register contains information relevant to the operation of the I/O device. Both the data
and status registers are assigned with unique addresses and they are connected to the
data bus.
3-3 I/O Interfacing Techniques
The most of the processors support isolated I/O system. It partitions memory from
I/O, via software, by having instructions that specifically access (address) memory
and others that specifically access I/O. When these instructions are decoded by the
processor, an appropriate control signal is generated to active either memory or I/O
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
operation. I/O devices can be interfaced to a computer system I/O in two ways, which
are called interfacing techniques,
• Memory mapped I/O
• I/O mapped I/O
3-3-1 Memory mapped I/O
In this technique, the total memory address space is partitioned and part of this space
is devoted to I/O addressing as shown in Figure 3.4
Figure 3.4 Address space
When this technique is used, a memory reference instruction that causes data to be
fetched from or stored at address specified, automatically becomes an I/O instruction
if that address is made the address of an I/O port. The usual memory related
instructions are used for I/O instructions are not required Figure 3.5, gives the I/O
with memory I/O.
Figure 3.5 Programmed I/ O with memory mapped I /O
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
3-3-2 I/O mapped I/O
If we do not want to reduce the memory address space, we allot a different I/O address
space, apart from total memory space which is called I/O mapped I/O technique as
shown in Figure 3.6
Figure 3.6 Address space
Figure 3.7 gives I/O with I/O mapped I/O technique
Here, the advantage is that the full memory address space is available. But now, the
memory related instructions do not work. Therefore, processor can only use this mode
if it has special instructions for I/O related operations such as I/O read, I/O write.
[Link] Memory mapped I/O I/O mapped I/O
1 Memory and I/O share the entire address range of Processor provides separate address range for
processor memory and IO devices
2 Usually processor provides more address lines for Usually processor provides less address lines
accessing memory. Therefore more decoding is for accessing I/O. Therefore, less decoding is
required control signals. required.
3 Control signals are used to control read and write I/O IO control signals are used to control read and
operations. write I / O operations.
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
3-4 Programmed I/O
I/O operations will mean a data transfer between an I/O device and memory or
between an I/O device and the processor. If in any computer system I/O operations
are completely controlled by the processor, then that system is said to be using
‘Programmed I/O’. When such a technique is used, processor executes programs that
initiate, direct and terminate the I/O operations, including sensing device status,
sending a read or write command and transferring the data. It is the responsibility of
the processor to periodically check the status of the I/O system until it finds that the
operation is complete. Let us consider the following example.
The processor’s software checks each of the I/O devices every so often. During this
check, the microprocessor tests to see if any device needs servicing. Figure 3.8 shows
the flow chart for this. This is simple program which services I/O ports A, B and C.
The routine checks the status of I/O ports in proper sequence. It first transfers the
status of I/O port A into the accumulator. Then the routine block checks the contents
of accumulator to see if the service request bit is set. If it is, I/O port A service routine
is called. After completion of service routine for I/O port A, the polling routine moves
on to test port B and the process is repeated. This test and service procedure continues
until all the I/O port status registers are tested and all the I/O ports requesting service
are serviced. Once this is done, the processor continues to execute the normal
programs.
The routine assigns priorities to the different I/O devices. Once the routine is started,
the service request bit at port. A is always checked first. Once port A is checked, port
B is checked, and then port C. However, the order can be changed by simply changing
the routine and thus the priorities.
When programmed I/O technique is used, processor fetches I/O related instructions
from memory and issues I/O commands to I/O system to execute the instruction. The
form of the instruction depends on the technique used for I/O addressing i.e. memory
mapped I/O or I/O mapped I/O.
As seen before, using memory mapped I/O technique, a memory reference instruction
that causes data to be fetched from or stored at address specified automatically
becomes an I/O instruction if that address is devoted to an I/O port. The usual memory
load and store instructions if that address is devoted to an I/O port. The usual memory
load and store instructions are used to transfer a word of data to an I/O port.
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
When I/O mapped I/O technique is used, separate I/O instructions are required to
activate READ I/O and WRITE I/O lines, which cause a word to be transferred
between the addressed I/O port and the processor. The processor has two separate
instructions, IN and OUT for I/O data transfer, e.g. the Intel 8085 microprocessor has
two main I/O instructions. The IN port address instruction causes a word to be
transferred from I/O port having address specified within the instruction to register
A (accumulator) of 8085. The instruction OUT port address transfers a word from
register A to I/O port having address specified within the instruction.
Figure 3.8 Flowchart for I / O service routine
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
When an I/O instruction is encountered by the processor, the addressed I/O port is
expected to be ready to respond the instruction to prevent loss of information. Thus
it is desirable for the processor to know the I/O device status (ready or not for I/O
data desirable for the processor to know the I/O device status (ready or not for I/O
data transfer). In programmed I/O systems, the processor is usually programmed to
test the I/O device status before initiating a data transfer.
3-5 Interrupt Driven I/O
When a processor allows executing its current program and calls a special routine
which “service” the interrupt. This is illustrated in Figure 3.9. The event that causes
the interruption is called interrupt and the special routine executed to service the
interrupt is called interrupt service routine (ISR). The interrupt service routine is
different from subroutine because the address of ISR is predefined or it is available
in interrupt vector table (IVT), whereas subroutine address is necessarily to be given
in subroutine CALL instruction. IRET instruction is used to return from the ISR
whereas RET instruction is used to return from subroutine. IRET instruction restores
flag contents along with CS and IP in the IA-32 architecture; however RET
instruction only restores CS and IP contents.
Figure 3.9: Interrupt Operation
Normal program can be interrupted by three ways:
1. By external signal
2. By a special instruction in the program or
3. By the occurrence of some condition.
An interrupt caused by an external signal is referred as a hardware interrupt.
Conditional interrupts caused by special are called software interrupts.
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
3-5-1 Interrupt Hardware
An I/O device requests an interrupt by activating a bus line called interrupt request
or simply interrupt. The interrupts are classified as:
1. Single level interrupts
2. Multi-level interrupts
3-5-1-1 Single Level Interrupts
In a single level interrupts there can be many interrupting devices. But all interrupt
requests are made via a single input pin of the CPU. When interrupted, CPU has to
poll the I/O ports to identify the request device. Polling software routine that checks
the logic state of each device. Once the interrupting I/O port is identified, the CPU
will service it and then return to task it was performing before the interrupt. Figure
3.10 shows single level interrupt system, in which the interrupt request from all the
devices are logically ORed and connected to the interrupt input of the processor.
Thus, the interrupt request from any device is routed to the processor interrupt input.
After getting interrupted, processor identifies requesting device by reading interrupt
status of each device.
Figure 3.10 Single level interrupt system
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
3-5-1-2 Multi-Level Interrupts
In multilevel interrupt system, when a processor is interrupted, it stops executing its
current program and calls a special routine which “services” the interrupt. The event
that causes the interruption is called interrupt and the special routine which is
executed is called interrupt service routine. When the external asynchronous input
(interrupt input) is asserted (a signal is sent to the interrupt input), a special sequence
in the control logic begins.
Figure 3.11 Multilevel Interrupt system
1. The processor completes its current its current instruction. No instruction is cut-
off in the middle of its execution.
2. The program counter’s current contents are stored on the stack. Remember, during
the execution of an instruction the program counter is pointing to the memory
location for the next instruction.
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
3. The program counter is loaded with the address of an interrupt service routine.
4. Program execution continues with the instruction taken from the memory location
pointed by the new program counter contents.
5. The interrupt program continues to execute until a return instruction is executed.
6. After execution of the RET instruction processor gets the old address (the address
of the next instruction from where the interrupt service routine was called.) of the
program counter from the stack and puts it back into the program counter. This allows
the interrupted program to continue executing at the instruction following the one
where it was interrupted. Figure 3.12 shows the response to an interrupt with the
flowchart and diagram.
Figure 3.12 Response to an interrupt with the flowchart and diagram
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 3. I/O ORGANIZATION College of Science / University of Diyala
3-6 Comparison between Programmed I/O and Interrupt Driven I/O
The Table gives the comparison between programmed I/O and interrupt I/O.
Sr. No. Programmed I/O Interrupt Driven I/O
1 In programmed I/O device in sequence and in External asynchronous input is used to tell the
effect ‘ask’ each one if it needs communication processor that I/O device needs its service and
with the processor. This checking is achieved hence processor does not have to check whether I/O
by continuous polling cycle and hence device needs it service or not.
processor cannot execute other instructions in
sequence.
2 During polling processor is busy and therefore,
In interrupt driven I/O, the processor is allowed to
has serious and decremental effect on system execute its instructions in sequence and only stop to
throughput. service I/O device when it is told to do so by the
device itself. This increase system throughput.
3 It is implemented without interrupt hardware It is implemented using interrupt hardware support.
support.
4 It does not depend on interrupt status. Interrupt must be enabled to process interrupt
driven I/O.
5 It does not need initialization of stack. It needs initialization of stack.
6 System throughput decreases as number of I/O System throughput does not depend in the system.
devices connected in the system increases.
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