University of Diyala

College of Science
Department of Computer Science

Computer Organization
and Architecture

Third Class
Second Term

Chapter TWO
COMPUTER SYSTEM
Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

2-1 Introduction
The purpose of computer organization and architecture is to prepare clear and
complete understanding of the nature and characteristics of modern-day computer
systems. We begin this text with the overview of computer organization and
architecture and structural /functional view of a computer. It is necessary to make
distinction between computer organization and architecture. Although it is difficult
to give precise definitions for these terms we define them as follows:

• Computer architecture refers to those attributes of a system visible to a

programmer. In other words, we can also say that the computer architecture refers
to the attributes that have a direct impact on the logical execution of the program.

• Computer organization refers to the operational units and their interconnections

that realize the architectural specifications.

The architectural attributes include the instruction set, data types, number of bits
used to represent data types, I/O mechanism, and techniques for addressing memory.
The organizational attributes include those hardware details transparent to
programmer, such as control signals, interfaces between the computer, memory and
I/O peripherals. For example, it is an architectural issue whether a computer will have
a multiply and division instructions. It is an organizational issue whether to
implement multiplication and division by special unit or by a mechanism that makes
repeated use of the add and subtract unit to perform multiplication and division,
respectively.

2-2 Basic Organization of Computer

The computer consists of five functionally independent unit: input, memory,
arithmetic and logic, output and control units. The Figure 2.1 shows these five
functional units of a computer, and its physical locations in the computer.

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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

Figure 2.1: Basic functional units of a computer

The input unit accepts the digital information from user with the help of input
devices such as keyboard, mouse, microphone etc. The information received from the
arithmetic and logic unit to perform the desired operation. The program stored in the
memory decides the processing steps and the processed output is sent to the user with
the help of output devices or it is stored in the memory for later reference. All the
above mentioned activities are coordinated and controlled by the control unit. The
arithmetic and logic unit in conjunction with control unit is commonly called Central
Processing Unit (CPU). Let us discuss the functional units in detail.
2-2-1 Input Unit
A computer accepts a digitally coded information through input unit using input
devices. The most commonly used input devices are keyboard and mouse. The
keyboard is used for entering text and numeric information. On the other hand mouse
is used to position the screen cursor and thereby enter the information by selecting
option. Apart from keyboard and mouse there are many other input devices are
available, which include joysticks, trackball, space ball, digitizers and scanners.

2-2-2 Memory Unit

The memory unit is used to store programs and data. Usually, two types of
memory devices are used to from a memory unit: primary storage memory device
and secondary storage memory device. The primary memory, commonly called main
memory is a fast memory used for the storage of programs and active data (the data
currently in process). The main memory consists of a large number of semiconductor
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

storage cells, each capable of storage cells, each capable of storing one bit of
information. These cells are read or written by the central processing unit in a group
of fixed size called word. The main memory is organized such that the content of one
word, contents of one word, containing n bits, can be stored or retrieved in one write
or read operation, respectively.
To access data from a particular word from main memory each word in the main
memory has a distinct address. This allows to access any word from the main memory
by specifying corresponding address. The number of bits in each word is referred to
as the word length of the computer. Typically, the word length varies from 8 to 64
bits. The number of such word in the main memory decides the size of memory or
capacity of the memory. This is one of specification of the computer. The size of
computer main memory varies from few million words to tens of million words. An
important characteristic of a memory is an access time (the time required to access
one word). The access time for main memory should be as small as possible.
Typically, it is of the order of 10 to 100 nanoseconds. This accessed time also depend
on the type of memory. In randomly accessed memories (RAMs), fixed time is
required to access any word in the memory. However, in sequential access memories
this time is not fixed. The main memory consists of only randomly accessed
memories. These memories are fast but they are small in the capacities and expensive.
Therefore, the computer user the secondary storage memories such a magnetic tapes,
magnetic disks for the storage of large amount of data.
2-2-3 Arithmetic and Logic Unit
The arithmetic and logic unit (ALU) is responsible for performing arithmetic
operations such as add, subtract, division and multiplication, and logical operations
such as ANDing, ORing, Inverting etc. To perform these operations operands from
the main memory are brought into high speed storage element called registers of the
processor. Each register can store one word of data and they are used to store
frequently used operands. The access times to registers are typically 5 to 10 times
faster than access times to memory. After performing operation the resulting is either
stored in the register or memory location.
2-2-4 Output Unit
The output unit sends the processed results to the user using output devices such
as video monitor, printer, plotter, etc. The video monitors display the output on the
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

CRT screen whereas printers and plotters, give the hard-copy output. Printers are
classified according to their printing method: Impact printers and non-impact
printers. Impact printers press formed character faces against an inked printers. Non-
impact printers and plotters use laser techniques, ink-jet sprays, xerographic
processes, electrostatic methods, and electro thermal methods to get images onto the
paper. An ink-jet printer is an example of non-impact printers.

2-2-5 Control Unit

As mentioned earlier, the control unit co-ordinates and controls the activities
amongst the functional units. The basic function of control unit is to fetch the
instructions stored in the main memory, identify the operations and the devices
involved in it, and accordingly generate control signals to execute the desired
operations. The control unit uses control signals to determine when a given action is
to take place. It controls input and output operations, data transfers between the
processor, memory and input/output devices using timing signals. The control and
the arithmetic and logic units of a computer are usually many times faster than other
devices connected to a computer system. This enables them to control a number of
external input/output devices.

2-3 Basic Operational Concept

The basic function of computer is to execute program, sequence of instructions.
These instructions are stored in the computer memory. The instructions are executed
to process data which already loaded into the computer memory through input unit.
After processing the data, the result is either stored back into the computer memory
for further reference or it is sent to the outside world through the output port.
Therefore all functional units of the computer contribute to execute program. Let us
summarize the functions of different computer units
• The input unit accepts data and instructions from the outside world to machine. It
is operate by control unit.
• The memory unit stores both, data and instructions.
• The arithmetic-logic unit performs arithmetic and logical operations.
• The control unit fetches and interprets the instructions in memory and causes them
to be executed.
• The output unit transmits final results and messages to the outside world.
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

To perform execution of instruction, in addition to the arithmetic logic unit, and

data and some special function registers, as shown in Figure 2.2. The special function
registers include program counter (PC), instruction register (IR), memory address
register (MAR) and memory data register (MDR).

Figure 2.2: Connections between the processor and the main memory

The program counter is one of the most important registers in the [Link]
mentioned earlier; a program is a series of instructions stored in the memory. These
instructions tell CPU exactly how to get the desired result. It is important that these
instructions must be executed in a proper order to get the correct result. This sequence
of instruction execution is monitored by the program counter. It keeps track of which
instruction is being executed and what the next instruction will be.
The instruction register (IR) is used to hold the instruction that is currently being
executed. The contents of IR are available to the control unit, which generate the
timing signals that control the various processing elements involved in executing the
instruction.
The two registers MAR and MDR are used to handle the data transfer between
the main memory and the processor. The MAR holds the address of the main memory
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

to or from which data is to transferred. The MDR contains the data to be written into
or read from the addressed word of the main memory.
Sometimes it is necessary to have computer system which can automatically execute
one of the collections of special routines whenever certain conditions exist within a
program or in the computer system. E.g. it is necessary that computer system should
give response to devices such as keyboard, sensor and other components when they
request for service. When the processor is asked to communicate with devices, we
say that the processor is servicing the devices. For example, each time when we type
a character on a keyboard, a keyboard service routine is called. It transfers the
character we type from the keyboard I/O port into the processor and then to a data
buffer in memory.
When you have one or more I/O devices connected to a computer system, any
one of them may demand service at a time. The processor can service these devices
in one of the two ways. One way is to use the polling routine. The other way is to use
an interrupt.
In polling the processor’s software simply checks each of the I/O devices every
so often. During this check, the processor tests to see if any device needs servicing.
A more desirable method would be the one that allows the processor to be executing
its main program and only stop to service I/O devices when it is told do so by the
device itself. In effect, the method, would provide an external asynchronous input
that would inform the processor that it should complete whatever instruction that is
currently being executed and fetch a new routine that will service the requesting
device. Once this servicing is completed, the processor would resume exactly where
it left off. This method is called interrupt method.
To provide services such as polling and interrupt processing is one of the major
functions of the processor. We known that, many I/O devices are connected to the
computer system. It may happen that more than one input devices request for I/O
service simultaneously. In such cases the I/O device having highest priority is
serviced first. Therefore, to handle multiple interrupts (more than one interrupts)
processor use priority logic. Thus, handling multiple interrupts is also a function of
the processor. The Figure 2.3 (a) shows how program execution flow gets modified
when interrupt occurs. The Figure 2.3 (b) shows that interrupt service routine itself
can be interrupted by higher priority interrupt. Processing of such interrupt is called
nested interrupt processing and interrupt is called nested interrupt.
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

(a) Program flow for single interrupt (b) Program for nested interrupt
Figure 2.3: Program for interrupts

We have seen that the processor provides the requested service by executing an
appropriate interrupt service routine. However, due to change in the program
sequence, the internal state of the processor may change and therefore, it is necessary
to save it in the memory before servicing the interrupt. Normally, contents of PC, the
general registers, and some control information are stored in memory. When the
interrupt service routine is completed, the state of the processor is restored so that the
interrupted program may continue. Therefore, saving the state of the processor at the
time of interrupt is also one of the function of the computer system. Let us see few
examples which will make you easier to understand the basic operations of a
computer.
Example 2.1: State the operations involved in the execution of ADD R1, R0
instruction.
Solution: The instruction Add R1, R0 adds the operand in R1 register to the operand
in R0 register and stores the sum into R0 register. Let us see the steps involved in the
execution of this instruction.
1. Fetch the instruction from the memory into IR register of the processor.
2. Decode the instruction.
3. Add the contents of R1 and R0 and store the result in the R0.
Example 2.2: state the operations involved in the execution of Add LOCA, R0.
Solution: The instruction Add LOCA, R0 and stores result in the register R0. The
steps involved in the execution of this instruction are:
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

1. Fetch the instruction from the memory into the IR register of the processor.
2. Decode the instruction.
3. Fetch the second operand from memory location LOCA and add the contents of
LOCA and the contents of register R0.
4. Store the result in the R0.

2-4 Bus Structures

We know that the central processing unit, memory unit and I/O unit are the
hardware components/modules of the computer. They work together with
communicating each other various modules is called the interconnection structure.
The design of this interconnection structure will depend on the exchanges that must
be made between modules. A group of wires, called bus is used to provide necessary
signals for communication between modules. A bus that connects major computer
components/ modules (CPU, memory I/O) is called a system bus. The system bus is
a set of conductors that connects the CPU, memory and I/O modules. Usually, the
system bus is separated into three functional groups:
1- Data Bus
2- Address Bus
3- Control Bus

Figure 2.4: Bus Interconnection scheme

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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

1. Data Bus:
The data bus consists of 8, 16, 32 or more parallel signal lines. The data bus
lines are bi-directional. This means that CPU can read data on these lines from
memory or from a ports, as well as send data out on these lines to a memory location
or to a port. The data bus is connected in parallel to all peripherals. The
communication between peripheral and CPU is activated by giving output enable
pulse to the peripheral. Outputs of peripherals are floated when they are not in use.

2. Address Bus:
It is an unidirectional bus. The address bus consists of 16, 20, 24 or more
parallel signal lines. On these lines the CPU sends out the address of the memory
location or I/O port that is to be written to or read from.

3. Control Bus:
The control lines regulate the activity on the CPU sends on the control bus to
enable the outputs of addressed memory devices or port devices. Typical control bus
signals are:

• Memory Read (MEMR)

• Memory Write (MEMW)
• I/O Read (IOR)
• I/O Write (IOW)
• Bus Request (BR)
• Bus Grant (BG)
• Interrupt Request (INTR)
• Interrupt Acknowledge (INTA)
• Clock (CLK)
• Reset
• Ready
• Hold
• Hold Acknowledge (HLDA)

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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

2-4-1 Single Bus Structure

Another way to represent the same bus connection scheme is shown in Figure
2.5 Here, address bus, data bus and control bus are shown by single bus called system
bus. Hence such interconnection bus structure is called single bus structure. In a
single bus structure all units are connected to common bus called system bus.
However, with single bus only two units can communicate with each other at a time.
The bus control lines are used to arbitrate multiple requests for use of the bus. The
main advantage of single bus structure is its low cost and its flexibility for attaching
peripheral devices.
The complexity of bus control logic depends on the amount of translation
needed between the system bus and CPU, the timing requirements, whether or not
interrupt management is included and the size of the overall system. For a small
system, control signals of the CPU could be used directly to reduce handshaking
logic. Also, drives and receivers would not be needed for the data and address lines.
But large system, with several interfaces would need bus driver and receiver circuits
connected to the bus in order to maintain adequate signal quality. In most of the
processors, multiplexed address and data buses are used to reduce the number of pins.
During first part of bus cycle, address is present on this bus. Afterwards, the same
bus is used for data transfer purpose.

Figure 2.5: Single Bus Structure

So latches are required to hold the address sent by the CPU initially. Interrupt priority
management is optional in a system. It is not required in systems which use software
priority management. The complex system includes hardware for managing the I/O
interrupts to increase efficiency of a system. Many manufacturers have made priority

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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

management devices. Programmable interrupt (PIC) is the IC designed to fulfill the

same task.

2-4-2 Multiple Bus Structures The performance of computer system suffers when
large numbers of devices are connected to the bus. This is because of the two major
reasons:
• When more devices are connected to the common bus we need to share the bus
amongst these devices. The sharing mechanism coordinates the use of bus to
different devices. This coordination requires finite time called propagation
delay. When control of the bus passes from one device to another frequently,
these propagation delays are noticeable and affect the performance of computer
system.
• When the aggregate data transfer demand approaches the capacity of the bus,
the bus may become a bottleneck. In such situations we have to increase the
data rate of the bus or we have to use wider bus.

Now a-days the data transfer rate for video controllers and network interfaces are
growing rapidly. The need of high speed shared bus is impractical to satisfy with a
single bus. Thus, most computer system uses the multiple buses. These buses have
the hierarchical structure.

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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

Figure 2.6: Traditional Bus Configuration

Figure 2.7: High-speed Bus Configuration

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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

Figure 2.6 shows two bus configurations. The traditional bus connection uses three
buses: local bus, system bus and expanded bus. The high speed bus configuration
uses high-speed bus along with the three buses used in the traditional bus connection.
Here, cache controller is connected to high-speed bus. This bus supports connection
high-speed LANs, such as Fiber Distributed Data Interface (FDDI), video and
graphics workstation controllers, as well as interface controllers to local peripheral
buses including SCSI and P1394.

2-4-3 Bus Design parameters In the previous section we have seen various buses
and their functions. To implement these buses in a computer system we have to
consider following parameters:
1- Type of Bus : Dedicated or multiplexed
2- Method of Arbitration : Centralized or distributed
3- Timing : Synchronous or asynchronous
4- Bus Width : Address or Data
5- Data Transfer Type: Read, write, read modify write, read-after write or block.
2-4-3-1 Bus Types
When a particular bus is permanently bus is permanently assigned to one
function or to a physical subset of computer component, it is called dedicatedbus.
As an example of functional dedication is the use of separate dedicate address and
data lines. Physical dedication gives high throughout, because there is less bus
contention. A disadvantage is the increased size and cost.

When bus is used for more than one function at different time zones, it is called
multiplexedbus. An example of multiplexed bus is the use of same bus for address
and data. At the beginning of data transfer, the address is placed on the bus along
with the address latch enable signal (ALE). At this point module has sufficient time
to latch the address with latch ICs. The address is then removed from the bus and the
same bus is used for data transfer.

2-4-3-2 Method of Arbitration

In a computer system there may be more than one bus masters such as
processor, DMA controller, etc. They share the system bus. In a centralized approach,
a single hardware device, referred to as a bus controller or arbiter, is responsible for
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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

allocating time on the bus for bus masters. In the distributed approach each bus master
contains access control logic and they act together to share the bus.

2-4-3-3 Bus Timings

Bus timing refers to the way in which events are coordinated on the bus. In
synchronous timing, the occurrence of events on the bus is determined by the clock
whereas in the asynchronous timing, the occurrence of events on the bus is
determined by the previous events on the bus.

Figure 2.8: Synchronous Timings

Figure 2.9: Asynchronous Timings

2-4-3-4 Bus Width

Bus width is nothing but the number of lines which are grouped to form a bus.
Data bus width decides the number of bits transferred at one time, whereas address
bus decides the range of location that can be accessed.

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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

2-4-3-5 Data Transfer type

As mentioned earlier, there are various data transfer types such as read, write,
read-modify write, read after write and block.
Read: In this operation address is put on the address bus and after sufficient access
time data is available on the data bus. Figure 2.10 shows read data transfer for
multiplexed address and data bus.

Figure 2.10: Read Data Transfer

Write: In this operation address is put on the multiplexed bus and then immediately
after latching period data is put on the multiplexed bus, as shown in the Figure 2.11.

Figure 2.11: Write Data Transfer

Read Modify Write: In this operation, read data transfer is followed by write data
transfer at the same address.

Figure 2.12: Read Modify Write Data Transfer

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Computer architecture Dr. Khalid Mohammed
Department of Computer Science
CHAPTER 2. COMPUTER SYSTEM College of Science / University of Diyala

Read-After Write: In this operation, write data transfer is followed by read data
transfer at the same address.

Figure 2.13: Read –After-Write Data Transfer

Block: In this operation, the address is put on the address bus and then the n numbers
of data transfer cycles are carried out.

Figure 2.14: Block Data Transfer

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