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Verilog Module Testing Simulation

This document is a Verilog testbench for a module named exercise1_3. It simulates the output of the module by varying the inputs x_1, x_2, and x_3 over time and displaying the results for each combination. The simulation runs through all possible combinations of the three inputs, outputting the corresponding values of var1_out and x_4_out.

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Treshia Jazmin Eguin
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4 views1 page

Verilog Module Testing Simulation

This document is a Verilog testbench for a module named exercise1_3. It simulates the output of the module by varying the inputs x_1, x_2, and x_3 over time and displaying the results for each combination. The simulation runs through all possible combinations of the three inputs, outputting the corresponding values of var1_out and x_4_out.

Uploaded by

Treshia Jazmin Eguin
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd

module testing_EX1_3();

reg x_1,x_2,x_3;
wire var1_out,x_4_out;

exercise1_3 tb3(var1_out,x_4_out,x_1,x_2,x_3);

initial begin
$display("Simulating output for exercise1_1");
$display("Time x_1 x_2 x_3 var1_out x_4_out");
$display("----------------------");

x_1=1'b0;x_2=1'b0;x_3=1'b0;
#10 $display("%4dns %b %b %b %b %b", $time,x_1,x_2,x_3,var1_out,x_4_out);
x_1=1'b0;x_2=1'b0;x_3=1'b1;
#10 $display("%4dns %b %b %b %b %b", $time,x_1,x_2,x_3,var1_out,x_4_out);
x_1=1'b0;x_2=1'b1;x_3=1'b0;
#10 $display("%4dns %b %b %b %b %b", $time,x_1,x_2,x_3,var1_out,x_4_out);
x_1=1'b0;x_2=1'b1;x_3=1'b1;
#10 $display("%4dns %b %b %b %b %b", $time,x_1,x_2,x_3,var1_out,x_4_out);
x_1=1'b1;x_2=1'b0;x_3=1'b0;
#10 $display("%4dns %b %b %b %b %b", $time,x_1,x_2,x_3,var1_out,x_4_out);
x_1=1'b1;x_2=1'b0;x_3=1'b1;
#10 $display("%4dns %b %b %b %b %b", $time,x_1,x_2,x_3,var1_out,x_4_out);
x_1=1'b1;x_2=1'b1;x_3=1'b0;
#10 $display("%4dns %b %b %b %b %b", $time,x_1,x_2,x_3,var1_out,x_4_out);
x_1=1'b1;x_2=1'b1;x_3=1'b1;
#10 $display("%4dns %b %b %b %b %b", $time,x_1,x_2,x_3,var1_out,x_4_out);
$finish;
end

endmodule

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