Student Name: MHD AMIN ABOU ARSHID Instructor: Mustafa Altun
Student ID: 040240927
EEF 205E: Introduction to Logic Design
Homework 1
Deadline: 31/10/2025 (before 9.00)
1. CONVERSION BETWEEN NUMBER REPRESENTATIONS
Perform the following number conversions:
a) Binary (100111,10111)2 to decimal, octal and hexadecimal.
b) Octal (72,6)8 to decimal, binary and hexadecimal.
c) Hexadecimal (C3,AD5)16 to decimal, binary and octal.
2. SIMPLIFIED SUM OF PRODUCT (SOP) EXPRESSIONS
Express the following Boolean functions in SOP forms with using minimum number literals.
Write down the total number of literals for your simplified expressions (for example, 𝑥1 ̅̅̅𝑥
𝑥2 3 +
𝑥1 𝑥
̅̅̅3 has 5 literals).
a) 𝑓1 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑥1 𝑥2 + 𝑥2 𝑥3 + 𝑥3 𝑥4
b) 𝑓2 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑥1 2 𝑥3 + 𝑥1 𝑥4
̅̅̅𝑥
c) 𝑓3 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑥1 ̅̅̅𝑥
𝑥2 3 + 𝑥1 ̅̅̅𝑥4 + 𝑥2 𝑥3 𝑥
̅̅̅4
d) 𝑓4 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑥1 𝑥2 𝑥
̅̅̅3 + 𝑥1 ̅̅̅𝑥
𝑥2 3 + ̅̅̅𝑥
𝑥1 2 𝑥3 + ̅̅̅
𝑥1 𝑥̅̅̅2 ̅̅̅
𝑥3
3. DESIGNING A 1-BIT FULL ADDER
Consider a 1-bit full adder with its circuit symbol and truth table shown below. Derive Boolean
functions both in SOP and SOP forms of the outputs in terms of the inputs, and simplify
them. There should be total of 4 expressions.
Inputs Outputs
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
4. USING K-MAP
Consider a 4-variable Boolean function f(x1, x2, x3, x4) =∑(1,3,4,5,9,11,12,13,14,15); x1 is the
most significant bit. Obtain a minimal sum-of-products (SOP) expression for f using a Karnaugh
map. Show all prime and essential prime implicants.
5. SIMULATION USING OneWare
a) Get OneWare from [Link] Install it to your computer using the
manual titled “Beginners Guide to Design Using VHDL with OneWare Studio”
distributed in Course Source Files in Ninova.
b) Take “OR_gate.vhd” and “OR_gate_tb.vhd” files from Ninova.
c) Build a new project and give a name to your project.
d) Add the files mentioned above to your project.
e) Simulate your design and take a picture of the waveform between 0 ns – 60 ns for your
homework report.
f) Produce a picture of RTL Schematic for your homework report.
g) Prepare a report which shows that you succesfully completed all the above steps.
Grading: 1)9%; 2)16%; 3)20%; 4)15%; 5)40%;
This report documents the simulation steps and results of an OR gate designed with
VHDL in OneWare Studio.
Implementation and Results
Following the assignment instructions (a-d), OneWare Studio was installed, and a
new project was created with the files.
Step e: Simulation Waveform (0-60 ns)
The design was compiled, and the waveform output for the 0-60 ns simulation range
is shown below:
Step f: RTL Schematic
The RTL schematic showing the hardware structure of the design is below:
Conclusion
All required steps (a-g) from the instructions were successfully completed, and the
simulation and RTL schematic results have been added to this report.