NCP5425

Dual Synchronous
Buck Controller
The NCP5425 is a highly flexible dual buck controller with internal
gate drivers that can be used with two input power supplies and one or
two outputs in multiple configurations. The part contains all the
circuitry required for two independent synchronous dual NFET buck [Link]
regulators utilizing a feed forward voltage mode control method. The
NCP5425 can run from a single supply ranging from 4.6 to 12 V and
support a single two phase or dual single phase outputs. When used as
20
a dual output controller, the second output tracks voltage transients
from the first. Power blanking for low noise applications is supported
as well as independent cycle−by−cycle current limiting. The part is 1
available in a 20 pin TSSOP package allowing the designer to
minimize PCB area.
TSSOP−20
DB SUFFIX
Features CASE 948E

• Operation Over 4.6 to 13.2 V

• Dual Synchronous Buck Design PIN CONNECTIONS AND
• Configurable as a Single Two Phase Output or Two Single Phase MARKING DIAGRAM
Outputs 20
1
• Programmable Power Sharing and Budgeting from Two Independent GATEH1 GATEH2
Supplies GATEL1 GATEL2
• 0.8 V "1% Reference for Low Voltage Outputs GND
BST
VCC
ROSC
NCP
• 1.5 A Peak Power Drive NC 5425 MODE
• Switch Blanking for Noise Sensitive Applications through use of NC
IS+1
ALYW G IS−2
IS+2
ROSC Pin G
IS−1 VREF2
• Programmable Frequency, 150 kHz to 750 kHz Operation VFB1 VFB2
COMP1 COMP2
• Programmable Soft−Start
• Cycle−by−Cycle Overcurrent Protection
• Independent Programmable Current Limits A = Assembly Location
• 100% Duty Cycle for Fast Transient Response L = Wafer Lot
Y = Year
• Internal Slope Compensation W = Work Week
• Out−of−Phase Synchronization between the Controllers G = Pb−Free Package
(Note: Microdot may be in either location)
• Input Undervoltage Lockout
• On/Off Enable through use of the COMP Pins ORDERING INFORMATION
• Power Supply Sequencing
Device Package Shipping †
• These are Pb−Free Devices
NCP5425DB TSSOP−20* 75 Units/Tube
Applications NCP5425DBG TSSOP−20* 75 Units/Tube
• DDR Memory Power NCP5425DBR2 TSSOP−20* 2500/Tape & Reel
• Graphics Cards
NCP5425DBR2G TSSOP−20* 2500/Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*This package is inherently Pb−Free.

© Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:

July, 2006 − Rev. 9 NCP5425/D
 NCP5425

12 V

3.3 V

+ C1 5V
220 mF
+ C12
220 mF

C6
C10 C11

0.1 mF
1 mF 1 mF
1.5 V/ R1 R2

18

4
10 A NTD60N02R NTD60N02R 1.8 V/

BST
VCC
4k 4k
5A
Q3 1 20 Q1
L2 GATE(H)1 GATE(H)2 L1
NTD110N02RT4 NTD110N02RT4 1.3 mH
1.3 mH
+ C3 Q4 Q2 + C14
2 19
680 mF1 GATE(L)1 GATE(L)2 680 mF2
14
IS+2
7 IS−2 15 R11 4K
IS+1
NCP5425
13 C9 R9
VREF2
R3 0.1 mF 0.4 k
8
IS−1
0.4 k 11
10 COMP2 R7
COMP1 C8 5k
C7 0.1 mF
0.1 mF VFB2 12
R5 9
MODE

VFB1 17
GND

ROSC
3.5 k R10 R8
R4 R6 R12 18 k 4k
3
16

15 k 4k 30.9 k

Figure 1. Application Diagram, 3.3 V to 1.5 V/10 A and 1.8 V/5.0 A Converter

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 NCP5425

MAXIMUM RATINGS
Rating Value Unit

Operating Junction Temperature, TJ 150 °C

Storage Temperature Range, TJ −65 to 150 °C

ESD Susceptibility (Human Body Model) 2.0 kV

ESD Susceptibility (Machine Model) 200 V

Thermal Resistance, Junction−to−Air 140 °C/W

Moisture Sensitivity Level (MSL) 1

Lead Temperature Soldering: Reflow: (Note 1) 260 peak °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 60 to 150 seconds maximum above 183°C, 260°C peak.

MAXIMUM RATINGS
Pin Symbol Pin Name VMAX VMIN ISOURCE ISINK

VCC IC Power Input 16 V −0.3 V N/A 2.0 A Peak

200 mA DC

COMP1, COMP2 Compensation Capacitor for 4.0 V −0.3 V 1.0 mA 1.0 mA

Channel 1 or 2

VFB1, VFB2, VREF2 Voltage Feedback Input for 6.0 V −0.3 V 1.0 mA 1.0 mA
Channel 1 or 2

ROSC Oscillator Resistor 5.0 V −0.3 V 1.0 mA 1.0 mA

GATE(H)1, GATE(H)2 High−Side FET Driver 20 V −0.3 V 2.0 A Peak 2.0 A Peak
for Channel 1 or 2 200 mA DC 200 mA DC

GATE(L)1, GATE(L)2 Low−Side FET Driver for 16 V −0.3 V 2.0 A Peak 2.0 A Peak
Channel 1 or 2 200 mA DC 200 mA DC

IS+1, IS+2 Positive Current Sense for 6.0 V −0.3 V 1.0 mA 1.0 mA
Channel 1 or 2

IS−1, IS−2 Negative Current Sense for 6.0 V −0.3 V 1.0 mA 1.0 mA
Channel 1 or 2

GND Ground 100 mV 0V 2.0 A Peak N/A

200 mA DC

BST Power Input for GATE(H)1 23 V −0.3 V N/A 2.0 A Peak

GATE(H)2 200 mA DC

MODE Dual or Single Output Select 3.5 V −0.3 V N/A N/A

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 NCP5425

ELECTRICAL CHARACTERISTICS (0°C < TJ < 125°C; ROSC = 30.9 k, CCOMP1,2 = 0.1 mF, 4.75 V < VCC < 13.2 V;
10.8 V < BST < 20 V, CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF; unless otherwise specified.)

Characteristic Test Condition Min Typ Max Unit

ERROR AMPLIFIER

VFB1 Input Bias Current VFB1 = 0 V − 0.1 1.0 mA

VFB2, VREF2 Input Bias Current VFB2, VREF2 = 0.8 V − 0.1 1.0 mA

Common Mode Input Voltage Range − 0.3 − 1.0 V

COMP1(2) Source Current COMP1(2) = 1.2 V to 2.5 V; VFB1(2) = 0.6 V 15 30 60 mA

COMP1(2) Sink Current COMP1(2) = 1.2 V; VFB1(2) = 1.0 V 15 30 60 mA

Reference Voltage COMP1 = VFB1 0.792 0.800 0.808 V

COMP1 Max Voltage VFB1(2) = 0.6 V − 2.0 2.1 V

COMP2 Max Voltage, Mode Floating VFB1(2) = 0.6 V 3.0 3.1 −
COMP2 Max Voltage, Mode = 0 VFB1(2) = 0.6 V − 2.0 2.1

COMP1(2) Min Voltage VFB1(2) = 1.2 V − 0.10 0.20 V

Open Loop Gain − 95 − dB

Unity Gain Bandwidth − 40 − kHz

PSRR @ 1.0 kHz − 70 − dB

Transconductance − − 32 − mmho

Output Impedance − − 2.5 − MW

GATE(H) AND GATE(L)

High Voltage (AC) VCC − GATE(L)1,2 − 0 0.5 V

BST − GATE(H)1,2 (Note 2)

Low Voltage (AC) GATE(L)1,2 or GATE(H)1,2 (Note 2) − 0 0.5 V

Rise Time 1.0 V < GATE(L)1,2 < VCC − 1.0 V − 25 80 ns

1.0 V < GATE(H)1,2 < BST − 1.0 V

Fall Time VCC − 1.0 > GATE(L)1,2 > 1.0 V − 25 80 ns

BST − 1.0 > GATE(H)1,2 > 1.0 V

GATE(H) to GATE(L) Delay GATE(H)1,2 < 2.0 V 20 40 80 ns

GATE(L)1,2 > 2.0 V

GATE(L) to GATE(H) Delay GATE(L)1,2 < 2.0 V 20 40 80 ns

GATE(H)1,2 > 2.0 V

GATE(H)1(2) and GATE(L)1(2) Pull−Down Resistance to GND (Note 2) 50 125 280 kW

PWM COMPARATOR

Propagation Delay COMP1(2) = 1.0 V − 200 300 ns

VFB1(2) = 0 to 1.2 V (Note 2)

PWM Comparator Offset VFB1(2) = 0 V; Increase COMP1(2) until 0.20 0.30 0.45 V
GATE(H)1(2) starts switching

Artificial Ramp Duty Cycle = 50% 55 95 150 mV

Minimum Pulse Width (Note 2) − 80 130 ns

2. Guaranteed by design, not 100% tested in production.

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 NCP5425

ELECTRICAL CHARACTERISTICS (continued) (0°C < TJ < 125°C; ROSC = 30.9 k, CCOMP1,2 = 0.1 mF, 4.75 V < VCC
< 13.2 V; 10.8 V < BST < 20 V, CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF; unless otherwise specified.)

Characteristic Test Condition Min Typ Max Unit

OSCILLATOR

Switching Frequency ROSC = 61.9 k; Measure GATE(H)1 112 150 188 kHz

Switching Frequency ROSC = 30.9 k; Measure GATE(H)1 224 300 376 kHz

Switching Frequency ROSC = 11.8 k; Measure GATE(H)1 562 750 938 kHz

ROSC Voltage ROSC = 30.9 k 0.970 1.000 1.030 V

Phase Difference − − 180 − °

Low Noise Disable Guaranteed By Design − 3.1 3.5 V

OVERCURRENT PROTECTION

OVC Comparator Offset Voltage 0 V < IS+1(2) < 5.5 V 55 70 85 mV

0 V < IS−1(2) < 5.5 V

IS+1(2) Bias Current 0 V < IS+1(2) < 5.5 V −1.0 0.1 1.0 mA
IS−1(2) Bias Current 0 V < IS−1(2) < 5.5 V −1.0 0.1 1.0 mA

OVC Common Mode Range − 0 − 5.5 V

SUPPLY CURRENTS

VCC Current COMP = 0 V (No Switching) − 16 22 mA

BST Current COMP = 0 V (No Switching) − 3.5 6.0 mA

UNDERVOLTAGE LOCKOUT

Start Threshold GATE(H) Switching; COMP1(2) Charging 3.8 4.2 4.6 V

Stop Threshold GATE(H) Not Switching; COMP1(2) Discharging 3.6 4.0 4.4 V

Hysteresis Start−Stop 0.1 0.2 0.45 V

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 NCP5425

PIN FUNCTION DESCRIPTION

Pin No. Symbol Description

1 GATE(H)1 High Side Switch FET driver pin for the channel 1 FET.

2 GATE(L)1 Low Side Synchronous FET driver pin for the channel 1 FET.

3 GND Ground. All circuits are referenced to this pin. IC substrate connection.

4 BST Power input for GATE(H)1 and GATE(H)2 pins.

5 NC No connection.

6 NC No connection.

7 IS+1 Positive input for channel 1 overcurrent comparator.

8 IS−1 Negative input for channel 1 overcurrent comparator.

9 VFB1 Error amplifier inverting input for channel 1.

10 COMP1 Channel 1 Error Amp output. PWM comparator reference input. A capacitor to GND provides Error
Amp compensation. The same capacitor provides soft−start timing for channel 1. This pin also disables
the channel 1 output when pulled below 0.2 V.

11 COMP2 Channel 2 Error Amp output. PWM comparator reference input. A capacitor to GND provides Error
Amp compensation and soft−start timing for channel 2. Channel 2 output is disabled when this pin is
pulled below 0.2 V.

12 VFB2 Error amplifier inverting input for channel 2.

13 VREF2 Error amplifier noninverting input for channel 2.

14 IS+2 Positive input for channel 2 overcurrent comparator.

15 IS−2 Negative input for channel 2 overcurrent comparator.

16 MODE Input pin used to inform internal circuitry of dual output or single output operation. Ground this pin for
dual output operation, leave open for single output operation.

17 ROSC A resistor from this pin to ground sets switching frequency.

18 VCC Input Power supply pin. Power input for GATE(L)1 and GATE(L)2 pins.

19 GATE(L)2 Low Side Synchronous FET driver pin for the channel 2 FET.

20 GATE(H)2 High Side Switch FET driver pin for the channel 2 FET.

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 NCP5425

IRAMP1
OSCILLATOR IRAMP2
AND 3.1 V
ROSC RAMP CLK1
CURRENT CLK2 IRAMP1
GENERATOR RAMP1
LNDM BST
Low noise disable mode
(pull ROSC high to activate)

3.1 V
REFERENCE
AND BIAS RAMP1
0.8 V
+ 0.3 V
GATE(H)1
3.1 V CLK1 LNDM
S Q

Reset
− PWM Dominant
+ COMP1 VCC
+ R Q LNDM
VFB1 − − GATE(L)1
−
+
0.8 V EA1
+
− COMP1 CLAMP
REFERENCE OC1 + IS+1
COMP1 − +− IS−1
70 mV

UVLO OC2 + IS+2

VCC − UVLO − +− IS−2
+ 70 mV
RAMP2
+ BST
− 4.2 V
4.0 V + 0.3 V
GATE(H)2
3.1 V CLK2 LNDM
S Q

Reset
− PWM Dominant
+ COMP2 VCC
+ R Q LNDM
VFB2 − − GATE(L)2
−
VREF2 +
EA2 3.1 V

COMP2 3.1 V 3.1 V

3.1 V
IRAMP2
GND
RAMP2
UVLO
S/D
Single
COMP2 or dual
CLAMP output
REFERENCE mode

MODE

Figure 2. Block Diagram

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 NCP5425

APPLICATIONS INFORMATION the main switch. The comparator response time and the
transition speed of the main switch determine the load
Theory of Operation transient response. Unlike traditional control methods, the
The NCP5425 is a very versatile buck controller using reaction time to the output load step is not related to the
V2t control method. It can be configured as: crossover frequency of the error signal loop. The error signal
• Dual output Buck Controller. loop can have a low crossover frequency, since the transient
• Two phase Buck Controller with current limit. response is handled by the ramp signal loop. The main
• Two phase Buck Controller with input power ratio and purpose of this ‘slow’ feedback loop is to provide DC
accuracy. Noise immunity is significantly improved, since
current limit.
the error amplifier bandwidth can be rolled off at a low
The fixed−frequency architecture, driven from a common
frequency. Enhanced noise immunity improves remote
oscillator, ensures a 180° phase differential between
sensing of the output voltage, since the noise associated with
channels.
long feedback traces can be effectively filtered. Line and
V2 Control Method load regulation are drastically improved because there are
The V2 method of control uses a ramp signal generated by two independent control loops. A voltage mode controller
the ESR (Effective Series Resistance) of the output relies on the change in the error signal to compensate for a
capacitors. This ramp is proportional to the AC current deviation in either line or load voltage. This change in the
through the main inductor and is offset by the DC output error signal causes the output voltage to change
voltage. This control scheme inherently compensates for corresponding to the gain of the error amplifier, the
variation in either line or load conditions, since the ramp consequence of which is normally specified as line or load
signal is generated from the output voltage itself. The V2 regulation. A current mode controller maintains a fixed error
method differs from traditional techniques such as voltage signal during line transients, since the slope of the ramp
mode control, which generates an artificial ramp, and signal changes in this case. However, regulation of load
current mode control, which generates a ramp using the transients still requires a change in the error signal. The V2
inductor current. method of control maintains a fixed error signal for both line
and load variation, since the ramp signal is affected by both
PWM line and load.
− GATE(H)
The stringent load transient requirements of modern
+
GATE(L) power supplies require the output capacitors to have very
low ESR. The resulting shallow slope in the output ripple
RAMP can lead to pulse width jitter and variation caused by both
Output
Voltage
random and synchronous noise. A ramp waveform
generated in the oscillator is added to the ramp signal from
Slope the output voltage to provide the proper voltage ramp at the
Compensation Error beginning of each switching cycle. This slope compensation
VFB
Amplifier increases the noise immunity, particularly at higher duty
−
COMP
+
cycle (above 50%).
Error Signal Reference
Voltage
Startup
The NCP5425 features a programmable soft−start
Figure 3. V2 Control with Slope Compensation function, which is implemented through the error amplifier
and external compensation capacitor. This feature reduces
The V2 control method is illustrated in Figure 3. The stress to the power components and limits overshoot of the
output voltage generates both the error signal and the ramp output voltage, during startup. As power is applied to the
signal. Since the ramp signal is simply the output voltage, it regulator, the NCP5425 Undervoltage Lockout circuit
is affected by any change in the output, regardless of the (UVLO) monitors the IC’s supply voltage (VCC). The
origin of that change. The ramp signal also contains the DC UVLO circuit prevents the MOSFET gates from switching
portion of the output voltage, allowing the control circuit to until VCC exceeds 4.2 V. Internal UVLO threshold
drive the main switch to 0% or 100% duty cycle as required. hysteresis of 200 mV improves noise immunity. During
A variation in line voltage changes the current ramp in the startup, the external Compensation Capacitor connected to
inductor, which causes the V2 control scheme to compensate the COMP pin is charged by an internal 30 mA current
the duty cycle. Since any variation in inductor current source. When the capacitor voltage exceeds the 0.3 V offset
modifies the ramp signal, as in current mode control, the V2 of the PWM comparator, the PWM control loop will allow
control scheme offers the same advantages in line transient switching to occur. The upper gate driver GATE(H) is now
response. A variation in load current will affect the output activated, turning on the upper MOSFET. The output current
voltage, modifying the ramp signal. A load step immediately then ramps up through the main inductor and linearly
changes the state of the comparator output, which controls powers the output capacitors and load. When the regulator

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 NCP5425

output voltage exceeds the COMP pin voltage, minus the Transient Response
0.3 V PWM comparator offset threshold and the artificial The 200 ns reaction time of the control loop provides fast
ramp, the PWM comparator terminates the initial pulse. transient response to any variations in input voltage or
output current. Pulse−by−pulse adjustment of duty cycle is
VIN provided to quickly ramp the inductor current to the required
4.2 V level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
VCOMP capacitors during the time required to slew the inductor
current. For better transient response, a combination of
0.3 V several high frequency and bulk output capacitors are
VFB typically used.

Out−of−Phase Synchronization
GATE(H)1 The turn−on of the second channel is delayed by half the
switching cycle. This delay is supervised by the oscillator,
GATE(H)2 which supplies a clock signal to the second channel that is
UVLO STARTUP ts NORMAL OPERATION 180° out of phase with the clock signal of the first channel.
Advantages of out−of−phase synchronization are many.
Figure 4. Idealized Startup Waveforms Since the input current pulses are interleaved with one
another, the overlap time is reduced. Overlap reduction
Normal Operation reduces the input filter requirement, allowing the use of
During normal operation, the duty cycle remains smaller components. In addition, since peak current occurs
approximately constant as the V2 control loop maintains during a shorter time period, emitted EMI is also reduced,
regulated output voltage under steady state conditions. potentially reducing shielding requirements. Interleaving
Variations in supply line or output load conditions will result the phases in a two phase application reduces ripple voltage
in changes in duty cycle to maintain regulation. and allows supplies with tighter tolerances to be built.

Gate Charge Effect on Switching Times Overvoltage Protection

When using the on board gate drivers, the gate charge has Overvoltage Protection (OVP) is provided as a
an important effect on the switching times of the FETs. A consequence of the normal operation of the V2 control
finite amount of time is required to charge the effective method, and requires no additional external components to
capacitor seen at the gate of the FET. Therefore, the rise and implement. The control loop responds to an overvoltage
fall times rise linearly with increased capacitive loading, condition within 200 ns, turning off the upper MOSFET and
according to the following graphs. disconnecting the regulator from its input voltage. This
results in a crowbar action to clamp the output voltage,
90 preventing damage to the load. The regulator remains in this
80 state until the overvoltage condition clears.
70 Low Noise Disable Mode
FALL/RISE TIME (ns)

Average Rise Time

60 A PWM converter operating at a constant frequency
concentrates its noise output over a small frequency band. In
50
noise−sensitive applications, this frequency can be chosen
40 to prevent interference with other system functions. Some
Average Fall Time applications may have even more stringent requirements,
30
where absolutely no noise may be emitted for a short period
20
of time.
10 The user may disable the clock during noise sensitive
0 periods to temporarily inhibit switching noise by
0 0 2 3 4 5 6 7 8 disconnecting or pulling the ROSC pin to 3.3 V. This disables
LOAD (nF) both gate drivers, leaving the switch node floating, and
Figure 5. Average Rise and Fall Times discharges the internal ramp.
The control circuitry remains enabled while the clock and
drivers are disabled, so the COMP pins will charge up to a
higher voltage. The COMP pins are clamped to prevent
excessive overshoot when switching is resumed.

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 NCP5425

Current Sharing Channel 1 is connected to the reference input of the Channel

When used in a two separate input to a single output mode, 2 error amplifier. Current information from Channel 2 is fed
the NCP5425 dual controller can provide input power back to the error amplifier’s inverting input. Channel 2 will
sharing in either of two ways: therefore act to adjust its current to match the current
• A preset ratio. For example, Channel 1 could provide information fed to its reference input from Channel 1. If this
70% of the load current, and Channel 2, the remaining information is one−half the voltage developed across the
30%. Practical ratios for Channel 1/Channel 2 Channel 1 output inductor, Channel 2 will run at half the
contribution to total load current range from 50%−50% current and supply a approximately 33% of the total load
to 80%−20%. current. This application is illustrated in Figure 7.
• A preset ratio up to a specific current contribution from In some applications the power supply designer may not
Channel 2. In excess of that limit, all of the additional only wish to draw a known percentage of power from one
load current would be supplied by Channel 1. Figure 7 source, but also limit the power drawn from that source. The
depicts the actual performance of a NCP5425 current limit amplifier on Channel 2 can be programmed to
configured in a 70%−30% share ratio, with Channel 2 budget the maximum input power into Channel 2 and all
output current limited to 5.0 Amps. power in excess of that limit will be supplied solely by
The availability both Channel 2 error amplifier inputs Channel 1. This is accomplished by setting the Channel 2
(signal and reference) at device pins is key to programmable cycle−by−cycle current limit in conjunction with
current ratio sharing. Current sense information from programming the current ratio as described above.

Vin Vin
Q1

Q3
L1 L2 Q2
Vout

R3
Q4 R1 C3 C2 R2
R
R C C R
C1
C
Master R4
Slave
Error Amp VFB1 R VFB2
− Error Amp
−
+ +
U2 U2
VREF2
Internal
Reference 0.8 V

Figure 6. Two Phase Current Sharing Circuit

14.00
INDIVIDUAL CHANNEL CURRENT, AMPS

Channel 1 output current

12.00 share begins to increase
Iout(1)
10.00

8.00 Channel 2 output current

begins to level off at 5
6.00 Amps
Iout(2)
4.00 Iin(1)

2.00 Iin(2)

0.00
0 5 10 15 20
TOTAL OUTPUT CURRENT, AMPS

Figure 7. 70%/30% Current Sharing with Channel 2 Current Limiting

NOTE: Channel 1 input voltage = Channel 2 input voltage = 5.0 V
Output voltage = 1.5 V

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 NCP5425

Inductor Current Sensing current sense signal will have the same wave shape as the
Examples of lossless current sensing across an output inductor current and the voltage signal on C1 will represent
inductor are shown in Figure 8. Lx is the output inductance the instantaneous value of inductor current. The voltage
and Rx represents its equivalent series resistance. To across C1 can be used as though it were a sense resistor with
compensate the current sense signal, the values of R1 and C1 the same value as the inductor’s ESR, thus avoiding a sense
are chosen so that Lx/Rx = R1 x C1. With these values, the resistor’s power loss.

Switch Switch
Node Node
Current Flow (IL)

Current Flow (IL)

Lx R1 Lx R1

+ls +ls
Rx + Rx +
Rx*IL*R2
C1 Rx X IL C1 R2
(R1 + R2)
_ + _ +
− −ls − −ls
DC DC
Output 70 mV Output 70 mV
(8A) (8B)

Switch Switch
Node Node
Current Flow (IL)

Current Flow (IL)

Lx R1 Lx R1

+ls +ls
Rx + Rx +

C1 Rx X IL C1 (Rx*IL) + (ER3)

_ + _ +
− −ls − −ls
DC R3 DC R3
Output 70 mV Output R4 70 mV
ER3 = (Vo*R3)/R3 + R4)
(8C) (8D)

Figure 8. Inductor Current Sensing − Circuit Configurations

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 NCP5425

Figure 8A − Basic Current Sensing Figure 8D – Decreasing the Current Threshold

Represents a basic inductor sensing configuration. When A voltage divider comprised of R3 and R4 is introduced
the voltage at pin +Is exceeds the voltage at pin –Is by 70 mV to develop, by scaling the output voltage, a small voltage
(nominal), the internal current sense comparator offset will drop across R3 that opposes the internal current sense
be overcome. For this case, the current limit threshold is comparator offset. For example, if Vout = 1.2 V, R3 = 200 W,
equal to (70 mV/Rx) amps. An obvious disadvantage of the and R4 = 11.8 K, a DC voltage drop of 20 mV will be
basic configuration is the power supply designer has no established across R3. The polarity of that voltage is such
control over the 70 mV offset, and limited control over the that it opposes the internal 70 mV offset, effectively
value of Rx. Therefore, he or she has little flexibility to set reducing it to 50 mV. The current threshold is now given by
a specific current limit. Configurations (8B) and (8D) depict (50 mV/Rx) instead of (70 mV/Rx).
techniques to increase and decrease, respectively, the
threshold current. Current Limiting
Both channels of the NCP5425 employ identical
Figure 8B – Increasing the Current Threshold
Cycle−by−Cycle current limiting. Comparators with
Addition of resistor R2 forms a voltage divider such that
internal 70 mV offsets provide the references for setting
only a portion of the voltage across Rx appears across C1.
current limit. Once a voltage greater than 70 mV is applied
If, for example, R1 = R2, it will require a 140 mV drop
to the current limiting comparator, it resets that channel’s
across Rx to overcome the internal 70 mV current sense
output RS flip flop. This terminates the PWM pulse for the
comparator offset. For optimum compensation with this
cycle and limits the energy delivered to the load. One
configuration, R1 and R2 should be selected such that Rx is
advantage of this current limiting scheme is that the
equal to their equivalent parallel resistance.
NCP5425 will limit large transient currents yet resume
Figure 8C – Bias Current Compensation normal operation on the following cycle. A second benefit
Configurations 8A, 8B and 8D all introduce a potential of limiting the PWM pulse width is, in an input power
error, since the bias currents of the current sense comparator sharing application, one controller can be current limiting
inputs flow through unbalanced resistance paths. The while the other supplies the remaining load current.
addition of R3 in configuration 8C, where R3 = R1, restores
a balanced input resistance, such that any voltage drops Output Enable
introduced by bias currents will cancel (assuming the +Is On/Off control of the regulator outputs can be
and –Is bias currents are equal). In the case of configuration implemented by pulling the COMP pins low. Driving the
8B, R3 would be made equal to the equivalent resistance of COMP pins below the 0.20 V PWM comparator offset
R1 and R2 in parallel. voltage disables switching of the GATE drivers.

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 NCP5425

DESIGN GUIDELINES Calculating Duty Cycle

The duty cycle of a buck converter (including parasitic
General losses) is given by the formula:
The output voltage tolerance can be affected by any or all
of the following: VOUT ) (VHFET ) VL)
Duty Cycle + D +
1. Buck regulator output voltage set point accuracy. VIN ) VLFET + VHFET + VL
2. Output voltage change due to discharging or where:
charging of the bulk decoupling capacitors during
VOUT = buck regulator output voltage;
a load current transient.
VHFET = high side FET voltage drop due to RDS(ON);
3. Output voltage change due to the ESR and ESL of
VL = output inductor voltage drop due to inductor wire
the bulk and high frequency decoupling capacitors,
DC resistance;
circuit traces, and vias.
VIN = buck regulator input voltage;
4. Output voltage ripple and noise.
VLFET = low side FET voltage drop due to RDS(ON).
Budgeting the tolerance is left to the designer who must
consider all of the above effects and provide an output Switching Frequency Select and Set
voltage that will meet the specified tolerance at the load. The Selecting the switching frequency is a trade−off between
designer must also ensure that the regulator component component size and power losses. Operation at higher
temperatures are kept within the manufacturer’s specified switching frequencies allows the use of smaller inductor and
ratings at full load and maximum ambient temperature. capacitor values. Nevertheless, it is common to select lower
frequency operation because a higher frequency also
Selecting Feedback Divider Resistors
diminishes efficiency due to MOSFET gate charge losses.
Additionally, low value inductors at higher frequencies
VOUT
result in higher ripple current, higher output voltage ripple,
and lower efficiency at light load currents. The value of the
R1
oscillator resistor is designed to be linearly related to the
VFB switching period. If the designer prefers not to use Figure 10
to select the appropriate resistance, the following equation
R2
is a suitable alternative:
21700 * fSW
ROSC +
2.31 fSW
Figure 9. Feedback Divider Resistors
where:
The feedback pins (VFB1(2)) are connected to external ROSC = oscillator resistor in kW;
resistor dividers to set the output voltages. The error fSW = switching frequency in kHz.
amplifier is referenced to 0.8 V and the output voltage is
determined by selecting resistor divider values. Resistor R1 800
is selected based on a design trade−off between efficiency 700
and output voltage accuracy. The output voltage error
FREQUENCY (kHz)

600
resulting from the bias current of the error amplifier can be
estimated, neglecting resistor tolerance, from the following 500
equation:
400
%Error + (100)(1 10−6)(R1)ń0.8
300
Rearranging, R1 + (%Error)(0.8)ń(1 10−4)
After R1 has been chosen, R2 can be calculated from: 200

R2 + (R1)ń((VOUTń0.8 V) * 1) 100

Example: 0
10 20 30 40 50 60 70
Assume the desired VOUT = 1.2 V, and the tolerable error
due to input bias current is 0.2%. ROSC (kW)
Figure 10. Switching Frequency vs. ROSC
R1 + (0.2)(0.8)ń(1 10−4) + 1.6 K
R2 + 1.6 Kń((1.2ń0.8) * 1) + 1.6 Kń0.5 + 3.2 K

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 NCP5425

Output Inductor Selection The number of output capacitors is determined by:

The inductor should be selected based on the criteria of ESRCAP
inductance, current capability, and DC resistance. Number of capacitors +
ESRMAX
Increasing the inductor value will decrease output voltage
ripple, but degrade transient response. There are many where:
factors to consider in selecting inductors including cost, ESRCAP = maximum ESR per capacitor
efficiency, EMI and ease of manufacture. The inductor must (specified in manufacturer’s data sheet).
be able to handle the peak current at the switching frequency The designer must also verify that the inductor value
without saturating, and the copper resistance in the winding yields reasonable inductor peak and valley currents (the
should be kept as low as possible to minimize resistive inductor current is a triangular waveform):
power loss.
DIL DIL
There are a variety of materials and types of magnetic IL(PEAK) + IOUT ) IL(VALLEY) + IOUT )
2 2
cores that could be used, such as ferrites, molypermalloy
cores (MPP), and amorphous and powdered iron cores. where:
Powdered iron cores are particularly suitable due to high IL(PEAK) = inductor peak current;
saturation flux density and low loss at high frequencies, a IL(VALLEY) = inductor valley current;
distributed gap, and they produce very low EMI. The IOUT = load current;
minimum value of inductance to prevent inductor DIL = inductor ripple current.
saturation, or exceeding the rated FET current, can be
calculated as follows: Output Capacitor Selection
These components must be selected and placed carefully
(VIN(MIN) * VOUT)VOUT
LMIN + to yield optimal results. Capacitors should be chosen to
fSW VIN(MIN) ISW(MAX) provide acceptable ripple on the regulator output voltage.
where: Key specifications for output capacitors are ESR
(Equivalent Series Resistance) and ESL (Equivalent Series
LMIN = minimum inductance value;
Inductance). For best transient response, a combination of
VIN(MIN) = minimum design input voltage;
low value/high frequency and bulk capacitors placed close
VOUT = output voltage;
to the load will be required. To determine the number of
fSW = switching frequency;
output capacitors the maximum voltage transient allowed
ISW(MAX) = maximum design switch current.
during load transitions has to be specified. The output
The inductor ripple current can then be determined by: capacitors must hold the output voltage within these limits
VOUT (1 * D) since the inductor current can not change at the required slew
DIL + rate. The output capacitors must therefore have a very low
L fSW
ESL and ESR.
where: The voltage change during the load current transient is
DIL = inductor ripple current; given by:

ǒESL ) ESR ) TR Ǔ
VOUT = output voltage; t
L = inductor value; DVOUT + DIOUT
Dt COUT
D = duty cycle;
fSW = switching frequency. where:
After inductor selection, the designer can verify if the DIOUT/DD = load current slew rate;
number of output capacitors will provide an acceptable DIOUT = load transient;
output voltage ripple (1.0% of output voltage is common). Dt = load transient duration time;
The formula below is used; ESL = Maximum allowable ESL including capacitors,
DVOUT
circuit traces, and vias;
DIL + ESR = Maximum allowable ESR including capacitors
ESRMAX
and circuit traces;
where: tTR = output voltage transient response time;
ESRMAX = maximum allowable ESR; COUT = output capacitance.
DVOUT = 1.0% ⋅ VOUT = maximum allowable output The designer must independently assign values for the
voltage ripple (budgeted by the designer); change in output voltage due to ESR, ESL, and output
DIL = inductor ripple current; capacitor discharging or charging. Empirical data indicates
VOUT = output voltage. that most of the output voltage change (droop or spike,
Rearranging, we have: depending on the load current transition) results from the
DVOUT
total output capacitor ESR.
ESRMAX +
DIL

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 NCP5425

Maximum allowable ESR can then be determined double−pole network with a slope of −2.0, a roll−off rate of
according to the formula: −40 dB/decade, and a corner frequency given by:
DVESR fC + 1
ESRMAX + ǸLC
DIOUT 2p
where: where:
DVESR =change in output voltage due to ESR L = input inductor;
(assigned by the designer) C = input capacitor(s).
Once the maximum allowable ESR is determined, the
POWER FET SELECTION
number of output capacitors can be calculated:
ESRCAP FET Basics
Number of capacitors + The use of a MOSFET as a power switch is compelled by
ESRMAX
two reasons: 1) high input impedance; and 2) fast switching
where: times. The electrical characteristics of a MOSFET are
ESRCAP = maximum ESR per capacitor considered to be nearly those of a perfect switch. Control
(specified in manufacturer’s data sheet); and drive circuitry power is therefore reduced. Because the
ESRMAX = maximum allowable ESR. input impedance is so high, it is voltage driven. The input of
The actual output voltage deviation due to ESR can then the MOSFET acts as if it were a small capacitor, which the
be verified and compared to the value assigned by the driving circuit must charge at turn on. The lower the drive
designer: impedance, the higher the rate of rise of VGS, and the faster
the turn−on time. Power dissipation in the switching
DVESR + DIOUT ESRMAX
MOSFET consists of: (1) conduction losses, (2) leakage
Similarly, the maximum allowable ESL is calculated from losses, (3) turn−on switching losses, (4) turn−off switching
the following formula: losses, and (5) gate−transitions losses. The latter three losses
DVESL Dt are all proportional to frequency. The most important aspect
ESLMAX +
DI of FET performance is the Static Drain−to−Source
On−Resistance (RDS(ON)), which affects regulator
Input Inductor Selection
efficiency and FET thermal management requirements. The
A common requirement is that the buck controller must
On−Resistance determines the amount of current a FET can
not disturb the input voltage. One method of achieving this
handle without excessive power dissipation that may cause
is by using an input inductor and a bypass capacitor. The
overheating and potentially catastrophic failure. As the
input inductor isolates the supply from the noise generated
drain current rises, especially above the continuous rating,
in the switching portion of the buck regulator and also limits
the On−Resistance also increases. Its positive temperature
the inrush current into the input capacitors during power up.
coefficient is between +0.6%/_C and +0.85%/_C. The
The inductor’s limiting effect on the input current slew rate
higher the On−Resistance, the larger the conduction loss is.
becomes increasingly beneficial during load transients. The
Additionally, the FET gate charge should be low in order to
worst case is when the load changes from no load to full load
minimize switching losses and reduce power dissipation.
(load step), a condition under which the highest voltage
Both logic level and standard FETs can be used. Voltage
change across the input capacitors is also seen by the input
applied to the FET gates depends on the application circuit
inductor. An input inductor successfully blocks the ripple
used. Both upper and lower gate driver outputs are specified
current while placing the transient current requirements on
to drive to within 1.5 V of ground when in the low state and
the input bypass capacitor bank, which has to initially
to within 2.0 V of their respective bias supplies when in the
support the sudden load change. The minimum value for the
high state. In practice, the FET gates will be driven
input inductor is:
rail−to−rail due to overshoot caused by the capacitive load
LIN + DV they present to the controller IC.
(dlńdt)MAX
where: Switching (Upper) FET Selection
The designer must ensure that the total power dissipation
LIN = input inductor value; in the FET switch does not cause the power component’s
DV = voltage seen by the input inductor during a full load junction temperature to exceed 150_C. The maximum RMS
swing; current through the switch can be determined by the
(dI/dt)MAX = maximum allowable input current slew rate. following formula:
The designer must select the LC filter pole frequency such
that a minimum of 40 dB attenuation is obtained at the IRMS(H) + Ǹ IL(PEAK)2 ) (IL(PEAK)
ƪ IL(VALLEY)) ) IL(VALLEY)2
3
Dƫ

regulator switching frequency. The LC filter is a

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 NCP5425

where: Synchronous (Lower) FET Selection

IRMS(H) = maximum switching MOSFET RMS current; The switch conduction losses for the lower FET are
IL(PEAK) = inductor peak current; calculated as follows:
IL(VALLEY) = inductor valley current; PRMS(L) + IRMS2 RDS(ON)
+ ƪIOUT Ǹ(1 * D)ƫ2
D = duty cycle.
RDS(ON)
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated by: where:
PRMS(H) + IRMS(H)2 RDS(ON) PRMS(L) = lower MOSFET conduction losses;
IOUT = load current;
where: D = Duty Cycle;
PRMS(H) = switching MOSFET conduction losses; RDS(ON) = lower FET drain−to−source on−resistance.
IRMS(H) = maximum switching MOSFET RMS current; The synchronous MOSFET has no switching losses,
RDS(ON) = FET drain−to−source on−resistance. except for losses in the internal body diode, because it turns
Upper MOSFET switching losses occur during MOSFET on into near zero voltage conditions. The MOSFET body
switch−on and switch−off, and can be calculated by: diode will conduct during the non−overlap time and the
PSWH + PSWH(ON) ) PSWH(OFF) resulting power dissipation (neglecting reverse recovery
VIN IOUT (tRISE ) tFALL)
losses) can be calculated as follows:
+ PSWL + VSD ILOAD non−overlap time fSW
6T
where: where:
PSWH(ON) = upper MOSFET switch−on losses; PSWL = lower FET switching losses;
PSWH(OFF) = upper MOSFET switch−off losses; VSD = lower FET source−to−drain voltage;
VIN = input voltage; ILOAD = load current;
IOUT = load current; Non−overlap time = GATE(L)−to−GATE(H) or
TRISE =MOSFET rise time (from FET manufacturer’s GATE(H)−to−GATE(L) delay
switching characteristics performance curve); (from NCP5425 data sheet
TFALL = MOSFET fall time (from FET manufacturer’s Electrical Characteristics section);
switching characteristics performance curve); fSW = switching frequency.
T = 1/fSW = period. The total power dissipation in the synchronous (lower)
The total power dissipation in the switching MOSFET can MOSFET can then be calculated as:
then be calculated as: PLFET(TOTAL) + PRMS(L) ) PSWL
PHFET(TOTAL) + PRMS(H) ) PSWH(ON) ) PSWH(OFF)
where:
where: PLFET(TOTAL) = Synchronous (lower) FET total losses;
PHFET(TOTAL) = total switching (upper) MOSFET losses; PRMS(L) = Switch Conduction Losses;
PRMS(H) = upper MOSFET switch conduction Losses; PSWL = Switching losses.
PSWH(ON) = upper MOSFET switch−on losses; Once the total power dissipation in the synchronous FET
PSWH(OFF) = upper MOSFET switch−off losses. is known the maximum FET switch junction temperature
Once the total power dissipation in the switching FET is can be calculated:
known, the maximum FET switch junction temperature can TJ + TA ) [PLFET(TOTAL) RqJA]
be calculated:
where:
TJ + TA ) [PHFET(TOTAL) RqJA]
TJ = MOSFET junction temperature;
where: TA = ambient temperature;
TJ = FET junction temperature; PLFET(TOTAL) = total synchronous (lower) FET losses;
TA = ambient temperature; RqJA = lower FET junction−to−ambient thermal
PHFET(TOTAL) = total switching (upper) FET losses; resistance.
RqJA = upper FET junction−to−ambient thermal
resistance.

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 NCP5425

Control IC Power Dissipation Sense Resistor

The power dissipation of the IC varies with the MOSFETs A sense resistor can be added in series with the inductor.
used, VCC, and the NCP5425 operating frequency. The When the voltage drop across the sense resistor exceeds the
average MOSFET gate charge current typically dominates internal voltage threshold of 70 mV, a limit condition is set.
the control IC power dissipation, and is given by: The sense resistor value is calculated by:
PCONTROL(IC) + ICC1VCC1 ) IBSTVBST
RSENSE + 0.070 V
) PGATE(H)1 ) PGATE(L)1 ILIMIT
) PGATE(H)2 ) PGATE(L)2 In a high current supply, the sense resistor will be a very
low value, typically less than 10 mW. Such a resistor can be
where: either a discrete component or a PCB trace. The resistance
PCONTROL(IC) = control IC power dissipation; of a discrete component can be more precise than a PCB
ICC1 = IC quiescent supply current; trace, but the cost is also greater. Setting the current limit
VCC1 = IC supply voltage; using an external sense resistor is very precise because all
PGATE(H) = upper MOSFET gate driver (IC) losses; the values can be designed to specific tolerances. However,
PGATE(L) = lower MOSFET gate driver (IC) losses. the disadvantage of using a sense resistor is its additional
The upper (switching) MOSFET gate driver (IC) losses constant power loss and heat generation. Trace resistance
are given by: can vary as much as "10% due to copper plating variations.
PGATE(H) + QGATE(H) fSW VBST Inductor ESR
where: Another means of sensing current is to use the intrinsic
resistance of the inductor. A model of an inductor reveals
PGATE(H) = upper MOSFET gate driver (IC) losses; that the windings have an effective series resistance (ESR).
QGATE(H) = total upper MOSFET gate charge at VCC; The voltage drop across the inductor ESR can be measured
fSW = switching frequency. with a simple parallel circuit: an RC integrator. If the value
The lower (synchronous) MOSFET gate driver (IC) of RS1 and C are chosen such that:
losses are: L +R C
S1
PGATE(L) + QGATE(L) fSW VCC ESR
where: then the voltage measured across the capacitor C will be:
PGATE(L) = lower MOSFET gate driver (IC) losses; VC + ESR ILIM
QGATE(L) = total lower MOSFET gate charge at VCC;
Inductor Sensing Component Selection
fSW = switching frequency.
Select the capacitor C first. A value of 0.1 mF is
The junction temperature of the control IC is primarily a recommended. The value of RS1 can be calculated by:
function of the PCB layout, since most of the heat is removed
RS1 + L
through the traces connected to the pins of the IC. ESR C
Typical values for inductor ESR range in the low
CURRENT SENSING AND CURRENT SHARING
milliohms; consult manufacturer’s data sheets for specific
Current Sharing Errors values. Selection of components at these values will result
The three main errors in current are from board layout in a current limit of:
imbalances, inductor mismatch, and input offsets in the error
amplifiers. The first two sources of error can be controlled ILIM + 0.070 V
ESR
through careful component selection and good layout
practice. With a 4.0 mW (parasitic winding resistance) VCC L ESR
inductor, for example, one mV of input offset error will
Co
represent 0.25 A of measurement error. One way to diminish
this effect is to use higher resistance inductors, but the GATE(H) RS1 C
penalty is higher power losses in the inductors.
GATE(L)
Current Limiting Options
IS+
The current supplied to the load can be sensed using the
IS+ and IS− pins. These pins sense a voltage, proportional IS−
to the output current, and compare it to a fixed internal
voltage threshold. When the differential voltage exceeds Figure 11. Inductor ESR Current Sensing
70 mV, the internal overcurrent protection system goes into
a cycle−by−cycle limiting mode. Two methods for sensing
the current are available.

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 NCP5425

Given an ESR value of 3.5 mW, the current limit becomes Master Slave
20 A. If an increased current limit is required, a resistor Switch Switch
Node Node
divider can be added (see Figure 8). Advantages of setting
Slave
the current limit by using the winding resistance of the Error
inductor (relative to a sense resistor) are higher efficiency Amp
and lower heat generation. The tolerance of the inductor Lx R1 R2 Lx
ESR must be factored into the design of the current limit.
Finally, one or two more components are required for this
approach than with resistor sensing.
Rx C1 C1 Rx
Selecting and Configuring Current Sharing for a 2 R3
Phase Single Output Application
When the two controllers are connected as a single output
two phase Buck Converter, they are in a Master−Slave DC
configuration. The Slave controller on the right side of Output
Figure 6 tries to follow information provided by the Master Figure 12. 40%/60% Current Sharing
controller, on the left. This circuit uses inductor current
sensing, in which the parasitic resistances (LSR) of the
controllers’ output chokes are used as current sensing Master Slave
elements. On the Slave side (Controller Two), both Error Switch Switch
Amplifier inputs are brought to external pins so the Node Node
reference is available. The RC network in parallel with the Slave
Error
output inductor on the Master side (Controller One)
Amp
generates the reference for the Slave. Current information
Lx R2 R1 Lx
from the Slave is fed back to the error amplifier’s inverting
input. In this configuration, the Slave tries to adjust its
current to match the current information fed to its reference
input from the Master Controller. If 50−50 current sharing Rx C1 C1 Rx
is needed, then Figure 8a is used for both sides to generate R3
the reference and the inverting signals. The values for both
sides should be calculated with the following equation:
DC
R1 + Lx , where,
Output
C1 · Rx
Lx = Inductor value, both controllers should use the same Figure 13. 66.7%/33.3% Current Sharing
inductor.
Rx = Internal resistance of L, from the inductor data sheet.
Example 1
C1 = Select a value such that R1 is less than 15 KW.
Assume we have elected to source 40% of the output
With the RC time constant selected to equal the Lx/Rx time
current from the master controller, and 60% from the Slave.
constant, the voltage across the capacitor will be equal to the
Figure 12 shows the configuration of the inductor sense
voltage drop across the internal resistance of the inductor.
networks and Slave error amplifier. The ratio of
For proper sharing, the inductors on both Master and Slave
Slave−to−Master load current is 60%/40%, or 1.5:1. R2 and
side should be the identical.
R3 must be chosen to satisfy two conditions:
If a current share ratio other than 50−50 is desired,
inductor sense resistor network selection is a three step A parallel equivalent resistance equal to R1, and,
process: A ratio such that the drop across the parasitic resistance of
1. Decide how the total load current will be budgeted the Slave inductor is 1.5 times the drop across the parasitic
between the two controllers. resistance of the Master inductor when the inputs to the
2. Calculate the value of R1 for the controller with Slave error amplifier are equal (assumes the inductors are
the lesser current share. identical). The optimum value of R1 is described by the
3. Calculate the current sense resistor network equation:
(2 resistors) for the controller with the greater R1 + Lxń(C1 * Rx)
current share.
In the two examples that follow, the inductor sense
resistors are designated R1, R2, and R3, as depicted in
Figures 12 and 13.

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 NCP5425

The values of R2 and R3 can be found by solving two The values of R2 and R3 can be found by solving two
simultaneous equations: simultaneous equations:
R2 + R3ń2 R2 + R3
R1 + (R2 * R3)ń(R2 ) R3) R1 + (R2 * R3)ń(R2 ) R3)
Solving for R2 and R3 yields: Solving for R2 and R3 yields:
R2 + 1.5R1 R2 + 2R1
R3 + 3R1 R3 + 2R1
Example 2 Note that the Mode pin must be floating for a two−phase,
Assume we have elected to source 66.7% output current single output design. This disables the internal Error
from the Master controller, and 33.3% from the Slave. Amplifier Reference clamp, and increases its common mode
Figure 13 shows the configuration of the inductor sense range.
networks and Slave error amplifier for this case. The ratio of
Master−to−Slave load current is equal to 66.7%/33.3%, or No Load Zero Balance
2:1. Therefore R2 and R3 must be chosen to satisfy two To improve current matching, a low pass filter can be
conditions: inserted between the Master controller inductor sensing RC
network and the Slave controller Vref2 input pin (see
A parallel equivalent resistance equal to R1, and, Figure 14). This will attenuate the amplitude of the
A ratio such that the drop across the parasitic resistance of out−of−phase ripple current signal superimposed on the DC
the Master inductor is 2 times the drop across the parasitic current signal, providing a smoother Slave Error Amplifier
resistance of the Slave inductor when the inputs to the reference input.
Slave error amplifier are equal (assumes the inductors are
identical). The optimum value of R1 is described by the
equation:
R1 + Lxń(C1 * Rx)

Vin

Vout
Q1 Q3

L1 L2
R1 C1 C2 R2 Q4
Q2
R3

C3
Vfb1 Vfb2
− −
Vref2
Master + R4 + Slave
RF
Error Amp Error Amp
Low Pass
Filter CF
Internal
0.8 V Ref.

Figure 14. Addition of a Low Pass Filter to the Current Sense Reference Input

With the value of RF set to approximately two times the Configuring a Dual Output Application
value of R1, Cf can be calculated as follows: To configure the NCP5425 for a dual output application:
Cf + 1ń(2p · f · RF), where : • The Mode pin must be grounded
• An external voltage reference must be provided for
f = operating frequency of the controller
Controller 2, via the Vref2 pin
When a filter is added, the response delay introduced by
the RC time constant must be considered.

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 NCP5425

Grounding the Mode pin enables an internal clamp to limit The simplest way to provide a Controller 2 reference is by
the Comp 2 voltage excursions during overcurrent faults. using the Controller 1 feedback voltage. This will provide a
Without this clamp, the output voltage (Vout1 and Vout2) 0.8 V reference for regulation, and also causes the
can overshoot the regulated output voltages when the fault Controller 2 output to track the Controller 1 output during
is removed. For a single output two−phase application the transients. With a voltage reference established and the
Mode pin must be floating, which disables the clamp and Mode pin floating, Controller 2 can function as an
permits a larger current−sharing reference voltage range. independent Buck regulator.
The Comp1 pin is always clamped, because it is regulated to
a fixed internal voltage (0.8 V).
Vin

Q1 Q3
Vout1 Vout2
L1 L2
Q2 C1 C2 Q4

R1 R3

Vfb1 Vfb2
− −
Vref1 Vref2
Master + R2 R4 + Slave
Error Amp Error Amp

Internal
0.8 V Ref.

Figure 15. Dual Output Configuration

Adding External Slope Compensation t = RC constant determined by C1 and the parallel

Today’s voltage regulators are expected to meet very combination of R1, R2 neglecting the low driver
stringent load transient requirements. One of the key factors output impedance.
in achieving tight dynamic voltage regulation is low ESR.
Low ESR at the regulator output results in low output
COMP
voltage ripple. The consequence is, however, that very little
voltage ramp exists at the control IC feedback pin (VFB),
resulting in increased regulator sensitivity to noise and the
potential for loop instability. In applications where the NCP5425
C1
internal slope compensation is insufficient, the performance R2 R1
of the NCP5425−based regulator can be improved through
the addition of a fixed amount of external slope
GATE(L)
compensation at the output of the PWM Error Amplifier (the
To Synchronous
COMP pin) during the regulator off−time. Referring to FET
Figure 8, the amount of voltage ramp at the COMP pin is
dependent on the gate voltage of the lower (synchronous) Figure 16. RC Filter Provides the Proper Voltage
FET and the value of resistor divider formed by R1and R2. Ramp at the Beginning of each On−Time Cycle

VSLOPECOMP + VGATE(L) ǒR1 R2

) R2
Ǔ (1−e −1
t) The artificial voltage ramp created by the slope
where: compensation scheme results in improved control loop
stability provided that the RC filter time constant is smaller
VSLOPECOMP = amount of slope added; than the off−time cycle duration (time during which the lower
VGATE(L) = lower MOSFET gate voltage; MOSFET is conducting). It is important that the series
R1, R2 = voltage divider resistors; combination of R1 and R2 is high enough in resistance to
t = tON or tOFF (switch off−time); avoid loading the GATE(L) pin. Also, C1 should be very
small (less than a few nF) to avoid heating the part.

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 NCP5425

EMI MANAGEMENT the optimum approach to reducing susceptibility to

As a consequence of large currents being turned on and off noise. Use the two internal layers as the power and
at high frequency, switching regulators generate noise GND planes, the top layer for power connections
during normal operation. When designing for compliance and component vias, and the bottom layers for the
with EMI/EMC regulations, additional components may be noise sensitive traces.
necessary to reduce noise emissions. These components are 6. Keep the inductor switching node small by placing
not required for regulator operation and experimental results the output inductor, switching and synchronous
may allow them to be eliminated. The input filter inductor FETs close together.
may not be required because bulk filter and bypass 7. The MOSFET gate traces to the IC must be short,
capacitors, as well as other loads located on the board will straight, and wide as possible.
tend to reduce regulator di/dt effects on the circuit board and 8. Use fewer, but larger output capacitors, keep the
input power supply. Placement of the power components to capacitors clustered, and use multiple layer traces
minimize routing distance will also help to reduce with wide, thick copper to keep the parasitic
emissions. resistance low.
9. Place the switching MOSFET as close to the input
LAYOUT GUIDELINES capacitors as possible.
When laying out a buck regulator on a printed circuit 10. Place the output capacitors as close to the load as
board, the following checklist should be used to ensure possible.
proper operation of the NCP5425. 11. Place the COMP capacitor as close as possible to
1. Rapid changes in voltage across parasitic capacitors the COMP pin.
and abrupt changes in current in parasitic inductors 12. Connect the filter components of pins ROSC, VFB,
are major concerns. VOUT, and COMP, to the GND pin with a single
2. Keep high currents out of sensitive ground trace, and connect this local GND trace to the
connections. output capacitor GND.
3. Avoid ground loops as they pick up noise. Use star 13. Place the VCC bypass capacitors as close as possible
or single point grounding. to the IC.
4. For high power buck regulators on double−sided 14. Place the ROSC resistor as close as possible to the
PCB’s a single ground plane (usually the bottom) ROSC pin.
is recommended. 15. Assign the output with lower duty cycle to
5. Even though double sided PCB’s are usually channel 2, which has inherently better noise
sufficient for a good layout, four−layer PCB’s are immunity.

V2 is a trademark of Switch Power, Inc.

[Link]
21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016

SCALE 2:1
NOTES:
20X K REF 1. DIMENSIONING AND TOLERANCING PER

ÍÍÍÍ
K
ANSI Y14.5M, 1982.
0.15 (0.006) T U S 0.10 (0.004) M T U S V S K1 2. CONTROLLING DIMENSION: MILLIMETER.

ÍÍÍÍ
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.

ÍÍÍÍ
MOLD FLASH OR GATE BURRS SHALL NOT
20 11 J J1 EXCEED 0.15 (0.006) PER SIDE.
2X L/2 4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
B SECTION N−N SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
L −U− 5. DIMENSION K DOES NOT INCLUDE
PIN 1 DAMBAR PROTRUSION. ALLOWABLE
IDENT DAMBAR PROTRUSION SHALL BE 0.08
N 0.25 (0.010)
(0.003) TOTAL IN EXCESS OF THE K
1 10 DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
M REFERENCE ONLY.
0.15 (0.006) T U S 7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
A N MILLIMETERS INCHES
−V− DIM MIN MAX MIN MAX
F A 6.40 6.60 0.252 0.260
B 4.30 4.50 0.169 0.177
DETAIL E C --- 1.20 --- 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
−W−
C H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
D G K 0.19 0.30 0.007 0.012
H K1 0.19 0.25 0.007 0.010
DETAIL E L 6.40 BSC 0.252 BSC
0.100 (0.004) M 0_ 8_ 0_ 8_
−T− SEATING
PLANE
GENERIC
SOLDERING FOOTPRINT MARKING DIAGRAM*
7.06
XXXX
1 XXXX
ALYWG
G

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
0.65 (Note: Microdot may be in either location)
PITCH
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
16X 16X may or may not be present.
0.36
1.26 DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASH70169A Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: TSSOP−20 WB PAGE 1 OF 1

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