Admas University

Department of computer science

Microprocessor Assembly Language Programming

Prepared By Girmay G.

1 1 1 Prepared By Girmay G. March 2024

Contents
🞂​ 1.1 Introduction to 🞂​ 2.1 Internal architecture of the 8086/8088
microprocessors microprocessors
🞂​ 1.2 General architecture of
🞂​ 2.2 Memory address space and data
microcomputer system
organization
🞂​ 1.3 Evolution of Intel
microprocessors 🞂​ 2.3 Segment registers and memory
🞂​ 1.4 Architectural compatibility segmentation
🞂​ 1.5 Hardware and software 🞂​ 2.4 Pointer and index register
🞂​ 1.6 Review of the basic number
systems and conversion between 🞂​ 2.5 Status and flag register
different number systems

2 Prepared By Girmay G. March 2024

Cont..
🞂​ 3.1 Data-Addressing Modes 🞂​ 4.1. Data Movement Instructions

🞂​ 3.1.1 Register Addressing 🞂​ 4.1.1 MOV Revisited

🞂​ 4.1.2 PUSH/POP
🞂​ 3.1.2 Immediate Addressing
🞂​ 4.1.3 Load-Effective Address
🞂​ 3.1.3 Direct Data Addressing
🞂​ 4.1.4 String Data Transfers
🞂​ 3.1.4 Register Indirect Addressing
🞂​ 4.2: Arithmetic and Logic instructions
🞂​ 3.2 Program Memory-Addressing Modes
🞂​ 4.2.1 Arithmetic Instructions
🞂​ 3.2.1 Direct Program Memory
🞂​ 4.2.2 Basic Logic Instructions
Addressing
🞂​ 4.2.3 Shift and Rotate
🞂​ 3.2.2 Relative Program Memory
🞂​ 4.2.4 String Comparisons
Addressing

🞂​ 3.2.3 Indirect Program Memory

3 Addressing Prepared By Girmay G. March 2024
INTRODUCTION TO MICROPROCESSORS
🞂​ Computer's Central Processing Unit (CPU) built on a single Integrated
Circuit (IC) is called a microprocessor.
🞂​ A digital computer with one microprocessor which acts as a CPU is
called microcomputer.
🞂​ It is a programmable, multipurpose, clock -driven, register-based
electronic device that reads binary instructions from a storage device
called memory, accepts binary data as input and processes data according
to those instructions and provides results as output.

4 Prepared By Girmay G. March 2024

Cont..
🞂​ The microprocessor contains millions of tiny components like transistors,
registers, and diodes that work together.
🞂​ A Microprocessor is an important part of a computer architecture without
which you will not be able to perform anything on your computer.
🞂​ It is a programmable device that takes in input performs some arithmetic
and logical operations over it and produces the desired output.
🞂​ In simple words, a Microprocessor is a digital device on a chip that can
fetch instructions from memory, decode and execute them and give
results.

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Basics of Microprocessor
🞂​ A Microprocessor takes a bunch of instructions in
machine language and executes them, telling the processor what
it has to do. Microprocessor performs three basic things while
executing the instruction:
🞂​ It performs some basic operations like addition, subtraction,
multiplication, division, and some logical operations using its
Arithmetic and Logical Unit (ALU).
🞂​ New Microprocessors also perform operations on floating-point numbers also.
🞂​ Data in microprocessors can move from one location to another.
🞂​ .
6 Prepared By Girmay G. March 2024
Cont..
🞂​ Program Counter (PC)
🞂 ​ Is a register that stores the address of the next instruction based on the
value of the PC, Microprocessor jumps from one location to another
and takes decisions

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Basic Terms used in Microprocessor
🞂​ Instruction Set -
🞂​ The group of commands that the microprocessor can understand is
called Instruction set.
🞂​ It is an interface between hardware and software.
🞂​ Bus -
🞂​ Set of conductors intended to transmit data, address or control
information to different elements in a microprocessor.
🞂​ A microprocessor will have three types of buses, i.e., data bus, address
bus, and control bus.
🞂​ IPC (Instructions Per Cycle) -
🞂​ It is a measure of how many instructions a CPU is capable of executing in
a single clock.

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Cont..
🞂​ Clock Speed -
🞂 ​ It is the number of operations per second the processor can
perform.
🞂 ​ It can be expressed in megahertz (MHz) or gigahertz (GHz).
🞂 ​ What Is the Difference between GHz AND MHz?
🞂​ One GHz equals one billion cycles per second whereas one MHz equals one million
cycles per second
🞂​ It is also called the Clock Rate.
🞂​ Bandwidth -
🞂 ​ The number of bits processed in a single instruction is called
Bandwidth.

9 Prepared By Girmay G. March 2024

Cont..
🞂​ Word Length -
🞂​ The number of bits the processor can process at a time is called
the word length of the processor.
🞂​ 8-bit Microprocessor may process 8 -bit data at a time.
🞂​ The range of word length is from 4 bits to 64 bits depending upon
the type of the microcomputer.
🞂​ Data Types - The microprocessor supports multiple data type
formats like binary, A SCII, signed and unsigned numbers.

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Features of Microprocessor
o Low Cost
o Due to integrated circuit technology microprocessors are available at very
low cost.
o It will reduce the cost of a computer system.
o High Speed
o Due to the technology involved in it, the microprocessor can work at very
high speed.
o It can execute millions of instructions per second.
o Small Size
o A microprocessor is fabricated in a very less footprint due to very large scale
and ultra large scale integration technology.
o Because of this, the size of the computer system is reduced.

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Cont..
 Versatile -
o The same chip can be used for several applications, therefore, microprocessors are
versatile.
 Low Power Consumption -
o Microprocessors are using metal oxide semiconductor technology, which consumes less
power.
 Less Heat Generation -
o Microprocessors uses semiconductor technology which will not emit much heat as
compared to vacuum tube devices.
 Reliable -
o Since microprocessors use semiconductor technology, therefore, the failure rate is very
less. Hence it is very reliable.
🞂​ Portable -
🞂 ​ Due to the small size and low power consumption microprocessors are portable.

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A µcomputer system?

13 Prepared By Girmay G. March 2024

 Cont…

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 Evolution of Intel

F airchild Semiconductors (founded in 1957)

invented the first IC in 1959.
I 1968, Robert Noyce, Gordan Moore, Andrew Grove
n
resigned from Fairchild Semiconductors.
They founded their own company Intel
(Integrated Electronics).

I tel grown from 3 man start-up in 1968 to

n
industrial giant by 1981.
I had 20,000 employees and $188
t
million revenue.
15 Prepared By Girmay G. March 2024
 4Bit Microprocessor :Intel 4004
IIintroduced in 1971.

I It was the first

t
microprocessor by Intel.

I It was a 4-bit µP.

t
I It’s clock speed was
t 740KHz.

I It had 2,300 transistors. It

t
could execute around
60,000 instructions per second.

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 Intel I ntroduced in 1974.

4040 I was also 4-bit µP.

t
8 KB of program memory
6 40 bytes of addressable memory
.000 The number of transistor
3
Clock speed is between 500
kHz
and 740 kHz. 4 uses
a crystal to 5185 MHz

17 Prepared By Girmay G. March 2024

 8 bit Microprocessors: Intel 8008

Introduced in 1972.

It was first 8-bit µP.

Its clock speed was 500
KHz.
Could execute
50,000 instructions per
second.

18 Prepared By Girmay G. March 2024

 Intel Itroduced in 1974. was
nalso 8-bit µP.
I
8080 t clock speed was 2
Its
MHz.

t had 6,000 transistors.

I
Was 10 times faster than 8008
Could execute

5,00,000 instructions per

second.

19 Prepared By Girmay G. March 2024

 ntroduced in 1976. was
I
also 8-bit µP.
I
t s clock speed was 3 MHz.
I
Intel t data bus is 8-bit and
Its
address bus is 16-bit.
8085 It had 6,500 transistors.

Could execute 7,69,230

instructions per second.
It could access 64 KB of
memory.
It had 246 instructions.

Over 100 million copies were s

Pro
eplad
re.
d

20 Prepared By Girmay G. March 2024

 Introduced in

Intel 1978.
It was first 16-
bit µP.
8086 Its clock speed is 4.77 MHz,
8 MHz and 10 MHz, depending
on the version.

I s data bus is 16-bit and

t address
bus is 20-bit.
It had 29,000
C
transistors. ould

I execute 2.5 million

instructions
t per second.
I
t could access 1 MB of
I
memory. had 22,000

instructions.
21 Prepared By Girmay G. March 2024
 Intel
8088 Introduced in 1979.
I was also 16-bit µP.
t
It was created as a cheaper
version of Intel’s 8086.

I was a 16-bit processor with

an
t 8-bit external bus.
Could execute 2.5 million
instructions per second.

T his chip became the most

popular in the computer
industry when IBM used it
for its first PC.
22 Prepared By Girmay G. March 2024
 Intel 80186 &
80188 Introduced in 1982.
They were 16-bit µPs.
Clock speed was 6 MHz.
80188 was a cheaper
version of 80186 with an 8-
bit external data bus.
They had additional
components like:
Interrupt Controller
Clock Generator
Local Bus
Controller
Counters
23 Prepared By Girmay G. March 2024
 Intel Introduced in 1989.
It was also 32-bit µP. It
80486 had It
h ad 1.2 million
I transistors.
t
1 Its clock speed varied
d from 6 MHz to 100 MHz
v depending upon the
various
I versions.
It
v t had five
different
versions:
 80486 DX
 80486 SX
 80486 DX2
8  80486 SL March 2024
24 Prepared By Girmay G.  80486 DX4
as
 32-bıt Mıcroprocessors

25 Prepared By Girmay G. March 2024

 Introduced in 1986.
t was first 32-bit
Intel I
I
µP.

80386 ts data bus is 32-bit and

address
I is 32-bit.
bus
t could address 4 GB of memory.
 It had 2,75,000 transistors.
 Its clock speed varied from 16
MHz to 33 MHz depending upon the
various versions.

Different versions:
80386 DX

80386 SX

80386 SL

 Intel 80386 became the best

selling microprocessor in
history.

26 Prepared By Girmay G. March 2024

 Intel Introduced in
Pentıum 1993.
I was also 32-bit
t µP.
I was originally named 80586.
t
s clock speed was 66 MHz.
iIt
t
is data bus is 32-bit and
It
a taddress bus is 32-bit.
I It could address 4 GB of memory.
t
m ould execute 110 million
c
instructions per second.
C
 i cache memory:
n
8 KB for
C instructions. 8 KB
for data.
27 Prepared By Girmay G. March 2024
 Intel Pentıum
Pro Introduced in 1995.

I It was also 32-bit µP.

I It had L2 cache of 25. 6 KB
 It had 21 million
I transistors
.  It
system
was primarily used in
servermemory:
 cache
I
8 KB for

C instructions. 8 KB
It for
had data.
L2 cache of 256
KB.
28 Prepared By Girmay G. March 2024
 Intel Pentıum
II Itroduced in
nI
1997. was also
tI
32-bit µP. s
t
clock speed was
233C MHz to 500 MHz.
ould execute 333
million
L
instructions per
second.
2 cache &
processor were on
29
Prepared By Girmay G. one circuit. March 2024
 Intel Pentıum II
Xeon Introduced in 1998.

I was also 32-bit µP.

t
I was designed for
t
I servers. s clock speed
t
was 400
MHz
L to 450 MHz.

1 cache of 32 KB & L2
cache of 512 KB, 1MB or
2I MB.
t
could work with 4
30 Prepared By Girmay G.
Xeons in same system.
March 2024
 Intel Pentıum
III Introduced in 1999.
It was also µP. 32
bit

Its clock speed

varied from 500 MHz
to 1.4 GHz.

It had 9.5
million
31 Prepared By Girmay G. transistors. March 2024
 Intel Pentıum
IV Introduced in 2000.

I It was also 32-


bit µP.

I Its clock speed was
from 3 GHz to 3.8
1 GHz.
1 cache was of 32 KB &
L 2 cache of 256 KB.
L
 It had 42
I million
transistors.
A ll internal connections
were made from aluminium
to copper.
32 Prepared By Girmay G. March 2024
 Introduced in 2006.
I is 32-bit or 64-bit µP.
t
I has two cores.
t
Bboth the cores have there wn
ointernal bus and L1 ache, but
cshare the external bus and L2
ecache
((Next Slide).
I  It supported SMT
t Technology.
t SMT: Simultaneously
S
Multi- threading E.g.: Adobe
T
Photoshop

33 Prepared By Girmay G. March 2024

 64-bıt Mıcroprocessors

34 Prepared By Girmay G. March 2024

 Intel Core 2
Introduced in 2006.
is a 64-bit µP.
II
t ts clock speed is from 1.2 Hz
I
I t to
t 3 GHz.
GI
t has 291 million
II
t t transistors. has 64 KB of
I I L1 cache per
tcore
t and 4 MB of L2 cache.
c
is launched in three
Idifferent ersions:
t Intel Core 2 Duo
v
 Intel Core 2 Quad
35 March 2024
Prepared By Girmay G.  Intel Core2 Extreme
 Intel Core i7
I troduced in 2008.
nI is a 64-bit µP.
t has 4 physical cores.
I
t
s clock speed is
I from
t
2.66 GHz to 3.33 GHz.

tIt has 781

million
ransistors.
I
t has 64 KB of L1 cache per core,
36 Prepared By Girmay G.
8 MB of L3
256 KB of L2 cache and
March 2024
 Intel Core i5
I troduced in
nI 2009. is a 64-
t bit µP.
I
t has 4 physical
I s cores.
clock speed from
2.40
t is GHz to 3.60
GHz.
I
t has 781
million
Itransistors.
has 64 KB of L1 cache per
tcore, 25KB of L2 cache6 L3 chache
37 Prepared By Girmay G. d March 2024
 Intel Core i3
I troduced in
nI 2010. is a 64-
t bit µP.
I
t has 2 physical cores.
I
t s clock speed is from 2.93 GHz
I to
3.33
t GHz.
has 781 million transistors.
It has 64 KB of 2 L1 cache
38 perBy Girmay
Prepared core,
G. 512024KB4 of L2
March
cache and MB of L3 cache.
39 Prepared By Girmay G. March 2024
 Chapter 2
BASIC ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSORS

40 40 Prepared By Girmay G. March 2024

Contents
🞂​ 2.1 Internal architecture of the 8086/8088 microprocessors
🞂​ 2.2 Memory address space and data organization
🞂​ 2.3 Segment registers and memory segmentation
🞂​ 2.4 Pointer and index register
🞂​ 2.5 Status and flag register

41 Prepared By Girmay G. March 2024

Intel 8086 M I C R O P R O C E S S O R ARCHITECTURE

42 Prepared By Girmay G. March 2024

Features

🞂​ It is a 16-bit μp.
🞂​ 8086 has a 20 bit address bus can access up to 220
memory locations (1 MB).
🞂​ It can support up to 64K I/O ports.
🞂​ It provides 14, 16 -bit registers.
🞂​ Word size is 16 bits and double word size is 4 bytes.
🞂​ It has multiplexed address and data bus AD0- AD15
and A16 – A19.

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🞂​ 8086 is designed to operate in two modes, Minimum and
Maximum.

🞂​ It can prefetches up to 6 instruction bytes from memory and

queues them in order to speed up instruction execution.

🞂​ It requires +5V power supply.

🞂​ A 40 pin dual in line package.

🞂​ Address ranges from 00000H to FFFFFH

44 Prepared By Girmay G. March 2024

Intel 8086 Internal Architecture

45 Prepared By Girmay G. March 2024

 Internal architecture of 8086

🞂​ 8086 has two blocks BIU and EU.

🞂​ The BIU handles all transactions of data and addresses on the
buses for EU.

🞂​ The BIU performs all bus operations such as instruction

fetching, reading and writing operands for memory and
calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue.
🞂​ E U executes instructions from the instruction system byte
queue.

46 Prepared By Girmay G. March 2024

 🞂​ BIU contains Instruction queue, Segment registers,
Instruction pointer, Address adder.
🞂​ EU contains Control circuitry, Instruction decoder,
ALU, Pointer and Index register, Flag register.

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Execution Unit
E x e c u t i o n U n i t c o n t a i n s :
 General Purposes Registers
 St a ck Pointer
 Base Pointer
 Index Registers
 ALU
 Flag Register
 Instruction Decoder
 Timing & Control Unit

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EX ECUTION UNIT

🞂​ Decodes instructions fetched by the BIU

🞂​ Generate control signals,
🞂​ Executes instructions.

The main parts are:

🞂​ Control Circuitry
🞂​ Instruction decoder
🞂​ A LU

49 Prepared By Girmay G. March 2024

EXECUTION UNIT – General Purpose Registers

8 8
bits bits
AH AL Accumulator
AX
16 bits
BH BL Base
BX

CX CH CL Count

DX DH DL Data

SP Stack Pointer
Pointer
BP Base Pointer

SI Source Index
Index
DI Destination Index
50 Prepared By Girmay G. March 2024
 EXEC U T IO N UNIT General Purpose Registers

• AX Register : AX register is also k n o w n as

a c c u m u l a t o r r e g i s t e r t h a t s t o r e s o p e r a n d s for
a ri t h m e t i c operation like divided, rotate.
• B X R e g i s t e r : This register is m a i n l y u s e d a s a b ase
r e g i s t e r . It h o l d s t h e s t a r t i n g b a s e l o c a t i o n of a
memory region within a data segment .
• C X R e g i s t e r : It i s d e f i n e d a s a c o u n t e r . It is
p r i m a r i l y u s e d i n l o o p i n s t r u c t i o n to s t o r e l o o p
counter.
• D X R e g i s t e r : D X r e g i s t e r i s u s e d to c o n t a i n I/ O
p o r t a d d r e s s for I / O i n s t r u c t i o n .
51 Prepared By Girmay G. March 2024
 E X E C U T IO N UNIT Pointer And Index Registers

🞂​ used to keep offset addresses.

🞂​ Used in various forms of memory addressing.
• Stack Pointer (SP):
The function of S P is same as the function of S P in Intel 8085.
It stores the address of top element in the stack.
• BP, SI & DI are used in memory address computation.
• BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments

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🞂​ SI: Source Index register

🞂​ is required for some string operations

🞂​ When string operations are performed, the SI register points to memory locations in the data
segment which is addressed by the DS register.

🞂​ Thus, SI is associated with the DS in string operations.

🞂​ DI: Destination Index register

🞂​ is also required for some string operations.

🞂​ When string operations are performed, the DI register points to memory locations in the data
segment which is addressed by the ES [Link], DI is associated with the ES in string operations.

🞂​ The SI and the DI registers may also be used to access data stored in arrays
53 Prepared By Girmay G. March 2024
EXECUTI O N UNIT – Flag Register
🞂​ A flag is a flip flop which indicates some conditions produced by the execution
of an instruction or controls certain operations of the EU .
🞂​ In 8086 The EU contains
a 16 bit flag register
9 of the 16 are active flags and remaining 7 are undefined.
6 flags indicates some conditions- status flags
3 flags –control Flags
U U U U OF DF IF TF SF ZF U AF U PF U CF

Sign Auxiliary Carry

Interrupt Trap Zero Parity
Over flow Direction

U - Unused
54 March 2024
Prepared By Girmay G.
Cont..

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EXEC U T IO N UNIT – Flag Register

Flag Purpose
Carry (CF) Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated
by some programs and procedures .
Parity (PF) PF=0;odd parity, PF=1;even parity.
Auxiliary (AF) Holds the carry (half – carry) after addition or
borrow after subtraction between bit positions 3
and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF) Shows the result of the arithmetic or logic
operation. Z=1; result is zero. Z=0; The
result is 0
Sign
56 (SF) Holds the sign of the resultPrepared
after an arithmetic/logic
By Girmay G. March 2024 instruction
 Flag Purpose
A control flag.
Trap (TF) Enables the trapping through an on-chip debugging
feature.
A control flag.
Interrupt (IF) Controls the operation of the INTR (interrupt
request) I=0; INTR pin disabled. I=1; INTR pin
enabled.
A control flag.
Direction (DF) It selects either the increment or decrement mode
for DI and /or SI registers during the string
instructions.
Overflow occurs when signed numbers are added or
Overflow
57 (OF) subtracted. An overflow indicates the resultMarch
Prepared By Girmay G.
has2024
exceeded the capacity of the Machine
Execution unit – Flag Register
🞂​ Six of the flags are status indicators reflecting properties of the last
arithmetic or logical instruction.
🞂​ For example, if register AL = 7Fh and the instruction A D D AL,1 is
executed then the following happen
A L = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed
58 Prepared By Girmay G. March 2024
Exercise 1

MOV A 2Bh (load 2BH in register

A) MOV B 19h (load 39H in
register B) ADD B
AL =
CF =
PF =
AF =
ZF =
SF =
OF =
59 Prepared By Girmay G. March 2024
 Exercise 2

MOV A 2Bh (load 2BH in register

A) MOV B 39h (load 39H in
register B) ADD B
AL =
CF =
PF =
AF =
ZF =
SF =
OF =

60 Prepared By Girmay G. March 2024

 BUS INTERFACE UNIT (BIU)
Contains
🞂 ​ 6-byte Instruction Queue (Q)
🞂 ​ The Segment Registers (CS, DS, ES, SS).
🞂 ​ The Instruction Pointer (IP).
🞂 ​ The Address Summing block (Σ)

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 F u n c t i o n of B u s I n t e r f a c e U n i t
It handles transfer of data and addresses
between the processor a n d memory / I O.
It r e a d s d a t a f r o m m e m o r y a n d I / O d e v i c e s .
It w r i t e s d a t a to m e m o r y a n d I / O d e v i c e s .
It c o m p u t e s a n d s e n d s o u t a d d r e s s e s .
It f e t c h e s i n s t r u c t i o n c o d e s .
It s t o r e s f e t c h e d i n s t r u c t i o n c o de s in a F I F O
register called Q U E U E .
62 Prepared By Girmay G. March 2024
 THE Q U EU E (Q)

🞂​ The BIU uses a mechanism known as an instruction stream

queue to implement a pipeline architecture.

🞂​ This queue permits pre-fetch of up to 6 bytes of instruction code.

🞂​ Whenever the queue of the BIU is not full,
🞂​ it has room for at least two more bytes and at the same time the EU is not
requesting it to read or write operands from memory, the BIU is free to look ahead
in the program by pre-fetching the next sequential instruction.

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 Physical Memory

Segmented Memory 00000

 The memory in an 8086/88 based

system is organized as
Code segment (64KB)
segmented memory.
Data segment (64KB)

1 MB
 The CPU 8086 is able to
address 1Mbyte of memory.
Extra segment (64KB)

 The Complete physically available Stack segment (64KB)

memory may be divided into a
number of logical segments.
FFFFF

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🞂​ The size of each segment is 64 KB
🞂​ A segment may be located any where in the memory
🞂​ Each of these segments can be used for a specific function.

🞂​ Code segment is used for storing the instructions.

🞂​ The stack segment is used as a stack and it is used to store the return
addresses.
🞂​ The data and extra segments are used for storing data byte.

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🞂​ The 4 segments are
🞂​ Code segment
🞂​ Data segment
🞂​ Extra segment
🞂​ Stack segment
🞂​ A Segment is a 64kbyte block of memory.
🞂 ​ The 16 bit contents of the segment registers in the BIU
actually point to the starting location of a particular segment.
🞂 ​ Segments may be overlapped or non-overlapped

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Segment registers
🞂​ In 8086/88 the processors have 4 segments registers

🞂​ Code Segment register (CS), Data Segment register (DS), Extra

Segment register (ES) and Stack Segment (SS) register.

🞂​ All are 16 bit registers.

🞂​ Each of the Segment registers store the upper 16 bit address of

the starting address of the corresponding segments.

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 Segment and Address register combination

🞂​ CS:IP

🞂​ SS:SP SS:BP

🞂​ DS:BX DS:SI

🞂​ DS:DI (for other than string operations)

🞂​ ES:DI (for string operations)

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 Summary of Registers & Pipeline of 8086 µP

EU BIU

AX AH AL
BX
IP
BH BL
D Fetch &
CX CH CL
store CS DS ES SS
DX DH DL E
C
code
C
O bytes in
O BX DI SP
D PIPELINE C IP
SP D E PIPELINE O DI BP
E O (or) D
BP SI
R U QUEUE E
SI T I
N
DI
Default Assignment
Timing
FLAGS ALU control

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 P i n D i a g r a m of 8 0 8 6

It h a s a 16 l i n e d a t a b u s .

And 20 line a d d r e s s bus.

It c o u l d a d d r e s s u p to 1 M B of m e m o r y .

It h a s m o r e t h a n 2 0 , 0 0 0 i n s t r u c t i o n s .

It s u p p o r t s m u l t i p l i c a t i o n a n d d i v i s i o n .

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 P i n D i a g r a m of 8 0 8 6

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 A D 0 – A D 1 5 P i n 1 6 - 2 , 3 9 (B i - d i r e c t i o n a l )

These lines are multiplexed

bidirectional address/data bus .
D u r i n g T1 , they carry lower order
16 - bit a d d r e s s .
In the r e m a i n i n g clock cycles,
they ca rry 16 - bit d a t a .
A D 0 - A D 7 c a r r y l o w e r o r d e r b y t e of
data.
A D 8 - A D 15 carry hi ghe r order byte
of d a t a .

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 A19/S6, A18/S5, A17/S4, A16/S3
P i n 3 5 - 3 8 (U n i d i r e c t i o n a l )

These lines are multiplexed

unidirecti onal address and status
bus.
D u r i n g T1 , they carry higher order 4 -
bit a d d r e s s .
In the remaining clock cycles, they
carry status signals.

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 B H E / S 7 P i n 3 4 (O u t p u t )

B H E s t a n d s for B u s H i g h E n a b l e .
BHE signal is used to indicate the
t r a n s f e r of d a t a o v e r h i g h e r o r d e r d a t a
b u s (D 8 – D 1 5 ) .

8 - bit I / O de vi ce s u s e t hi s s i g n a l .
It i s m u l t i p l e x e d w i t h s t a t u s p i n S 7 .

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 R D (R e a d ) P i n 3 2 (O u t p u t )

It is a read signal used for

read operation.

It i s a n o u t p u t s i g n a l .

It i s a n a c t i v e low s i g n a l .

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 R E A D Y P i n 2 2 (I n p u t )

T h i s is a n a c k n o w l e d g e m e n t s i g n a l from
s l o w e r I / O d e v i c e s or m e m o r y .
It i s a n a c t i v e h i g h s i g n a l .
W h e n h i g h , it i n d i c a t e s that the device
i s r e a d y to t r a n s f e r d a t a .
When low, then microprocessor is in
wait s t a t e .

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 R E S E T P i n 2 1 (I n p u t )

It i s a s y s t e m r e s e t .
It i s a n a c t i v e h i g h s i g n a l .
When high, microprocessor enters
into reset state and terminates the
current activity.

It m u s t be a c t i v e for a t l e a s t f o u r
clock cycles to reset the
microprocessor.

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 I N T R P i n 1 8 (I n p u t )

It i s a n i n t e r r u p t r e q u e s t s i g n a l .

It i s a c t i v e h i g h .

It i s l e v e l t r i g g e r e d .

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 N M I P i n 1 7 (I n p u t )

It i s a n o n - m a s k a b l e i n t e r r u p t s i g n a l .

It i s a n a c t i v e h i g h .

It i s a n e d g e t r i g g e r e d i n t e r r u p t .

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 T E S T P i n 2 3 (I n p u t )

It is used to test the status of math

coprocessor 8087 .

The B U S Y p i n of 8 0 8 7 is c o n n e c t e d to

t h i s p i n of 8 0 8 6 .

If low, execution continues else

m i c r o p r o c e s s o r is in wait s t a t e .

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 C L K P i n 1 9 (I n p u t )
This clock i n put provides the basic
t i m i n g for p r o c e s s o r o p e r a t i o n .

It is symmetric square wave with

33 % duty cycle.

T h e r a n g e of f r e q u e n c y of d i f f e r e n t
versions is 5 MHz, 8 MHz and 10
MHz.

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 V C C and V S S Pin 40 and Pin 20 (Input)

V C C is power s u p p l y s i g n a l .

+5V DC is s u p p l i e d through this

pin.

V S S is g r o u n d s i g n a l .

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 M N / M X P i n 33 (I n p u t )
8086 works in two modes:
• Minimum Mode
• Maximum Mode
If MN/MX is high, it works in minimum mode.
If MN/MX is low, it works in maximum mode.
Pins 24 to 31 issue two different sets of signals.
One set of signals is issued when C P U operates in
minimum mode.
Other set of signals is issued when C P U operates in
maximum mode.

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 P i n D e s c r i p t i o n for M i n i m u m M o d e
INTA P i n 2 4 (O u t p u t )

• This is an interrupt acknowledge

signal.

• When microprocessor receives INTR

signal, it acknowledges the
i n t e r r u p t by g e n e r a t i n g t h i s s i g n a l .
• It i s a n a c t i v e low s i g n a l .

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 A L E P i n 2 5 (O u t p u t )

• T hi s is a n A d d r e s s L a t c h E n a b l e s i g n a l .

• It i n d i c a t e s t h a t v a l i d a d d r e s s i s a v a i l a b l e

on b u s A D 0 – A D 15 .

• It is an active high signal and remains

high during T1 state.

• It is connected to enable pin of latch

8282 .
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 D E N P i n 2 6 (O u t p u t )

• T hi s is a D a t a E n a b l e s i g n a l .

• This signal is used to enable the

transceiver 8286 .

• Transceiver is used to separate the

data from the a d d r e s s / d a t a b u s .

• It i s a n a c t i v e low s i g n a l .

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 D T / R P i n 2 7 (O u t p u t )

• T hi s is a Data Transmit /Receive

signal.

• It d e c i d e s t h e d i r e c t i o n of d a t a flow
t h r o u g h the t ra nsceiver.

• When it i s h i g h , data is t r a n s m i t t e d
out.

• W h e n it i s l o w , d a t a i s r e c e i v e d i n .

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 M / I O P i n 2 8 (O u t p u t )

• This signal is issued by the

microprocessor to distinguish memory

a c c e s s from I /O a c c e s s .

• W h e n it i s h i g h , m e m o r y i s a c c e s s e d .

• W h e n it i s l o w , I / O d e v i c e s a r e a c c e s s e d .

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 W R P i n 2 9 (O u t p u t )

• It i s a W r i t e s i g n a l .

• It i s u s e d to w r i te d a t a i n m e m o r y
or o u t p u t device depending on the
s t a t u s of M / I O s i g n a l .

• It i s a n a c t i v e low s i g n a l .

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 H L D A P i n 3 0 (O u t p u t )

• It i s a H o l d A c k n o w l e d g e s i g n a l .

• It is issued after receiving the

HOLD signal.

• It i s a n a c t i v e h i g h s i g n a l .

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 H O L D P i n 3 1 (I n p u t )

• When DMA controller needs to use

address/data b u s , it s e n d s a r e q u e s t to
the C P U t h r o u g h this pin.

• It i s a n a c t i v e h i g h s i g n a l .

• When microprocessor receives HOLD

s i g n a l , it i s s u e s H L D A s i g n a l to t h e D M A
controller.

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 P i n D e s c r i p t i o n for M a x i m u m M o d e
QS1 and Q S 0 P i n 2 4 a n d 2 5 (O u t p u t )

• These pins provide the s t a t u s of

instruction Queue.

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 S 0 , S 1 , S 2 P i n 2 6 , 2 7 , 2 8 (O u t p u t )

• These status signals indicate the

operation being done by the
microprocessor.

• This information is r e q u i r e d by t h e B u s
Controller 8288 .

• B u s controller 8 2 8 8 g e n e r a t e s all m e m o r y
and I/O control signals.

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 S 0 , S 1 , S 2 P i n 2 6 , 2 7 , 2 8 (O u t p u t )

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 L O C K P i n 2 9 (O u t p u t )

• This signal indicates that other

processors should not ask CPU to
re li nquish the system b u s .
• When it goes low, all interrupts are
m a s k e d a n d H O L D r e q u e s t is not g r a n t e d .
• This pin is activated by using LOCK
prefix on any i n s t r u c t i o n .

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 RQ/ GT 1 and RQ/ GT 0 Pi n 3 0 a n d 3 1 ( B i - d i r e c t i o n a l )

• These are Request/Grant

pins.
• Other processors request the
CPU through these l ines to
release the system b u s .
• After receiving the request,
CPU sends acknowledge

s i g n a l on the s a m e l i n e s .
• RQ/GT 0 has higher priority
than RQ /GT 1.
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97 Prepared By Girmay G. March 2024
 Chapter Three
ADDRESSING MODES

98 98 Prepared By Girmay G.
Contents
🞂​ 3.1 Data-Addressing Modes

🞂​ 3.1.1 Register Addressing

🞂​ 3.1.2 Immediate Addressing

🞂​ 3.1.3 Direct Data Addressing

🞂​ 3.1.4 Register Indirect Addressing

🞂​ 3.2 Program Memory-Addressing Modes

🞂​ 3.2.1 Direct Program Memory Addressing

🞂​ 3.2.2 Relative Program Memory Addressing

🞂​ 3.2.3 Indirect Program Memory Addressing

🞂​ 3.3 Stack Memory-Addressing Modes

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 2. A D D R E S S I N G M O D E S

 To p e r f o r m a n y o p e r a t i o n , we h a v e to g i v e t h e
corresponding i n s t r u c t i o n s to the m i c r o p r o c e s s o r .
 I n e a c h i n s t r u c t i o n , p r o g r a m m e r h a s to s p e c i f y 3
things:

O p e r a t i o n to be p e r f o r m e d .
A d d r e s s of s o u r c e of d a t a .
A d d r e s s of d e s t i n a t i o n of r e s u l t .

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 ADDRESSING MODES

T h e m e t h o d b y w h i c h t h e a d d r e s s of s o u r c e of
d a t a or t h e a d d r e s s of d e s t i n a t i o n of r e s u l t i s
given in the i n s t r u c t i o n is c a lled A d d r e s s i n g
Modes.

T h e t e r m a d d r e s s i n g m o d e r e f e r s to t h e w a y in
w h i c h t h e o p e r a n d of t h e i n s t r u c t i o n i s s p e c i f i e d .

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Categories of addressing modes

102 1 02
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103 1 02
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 Ty pes of D at a Addressing Modes

Intel 8086 use s the following a ddre ssi n g modes:

1. Direct Addressing Mode

2. Register Addressing Mode

3. Register Indirect Addressing Mode

4. Immediate Addressing Mode

5. Implicit Addressing Mode

[Link]-plus-index addressing
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 1 . Direct Addressing Mode

 In this mode, the address of the operand i s directly

specified in the instruction Itself.

8085/8086 Offset address

E . g . LDA/( mov) C L, [ 2 5 0 0 H ]

L D A is the o p e r a t i o n .

2 5 0 0 H is the a d d r e s s of s o u r c e .

A c c u m u l a t o r is the d e s t i n a t i o n .

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 2 . Register Addressing Mode

 In this mode, the Both the operand i s in general

purpose register.

M O V is t h e o p e r a t i o n .
B is t h e s o u r c e of d a t a .
A is t h e d e s t i n a t i o n .

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 3 . Register Indirect Addressing Mode

 In thi s m o d e , the ad d ress o f operand i s specified by a

register pair.

MOV is the o p e r a t i o n .
M i s t h e m e m o r y l o c a t i o n s p e c i f i e d by H - L
register pair.
A is the d e s t i n a t i o n .

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108 Prepared By Girmay G. March 2024
 4. Immediate Addressing Mode
I n t h i s m o d e , t h e o p e r a n d i s s p e c i f i e d w i t h i n t h e
instruction itself.

 T h e S o u r c e o p e r a n d i s a 8 b i t or 1 6 b i t d a t a

MOV AX,1200H MOV AL,12H

MV I is the o p e r a t i o n .
1 2 0 0 H a n d 1 2 h is the i m m e d i a t e d ata
Destination
Source (s o u r c e ) .
A X O R AL is the d e s t i n a t i o n .

NOTE:
D estination Can Never B e im m ediate dat a
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110 Prepared By Girmay G. March 2024
5. Implicit Addressing Mode
 If a d d r e s s of s o u r c e of d a t a a s w e l l a s a d d r e s s of
d e s t i n a t i o n of r e s u l t i s f i x e d , t h e n t h e r e i s n o n e e d to
give a n y o p e r a n d a l o n g with the i n s t r u c t i o n .

C M A i s t h e o p e r a t i o n .
A i s t h e s o u r c e .
A i s t h e d e s t i n a t i o n .

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6. Base-plus-index addressing
🞂​ Base-plus-index addressing transfers a byte or word between a register
and the memory location addressed by a base register (BP or BX) plus an
index register (DI or SI).
🞂​ Example:The MOV [BX+DI], CL instruction copies the byte-sized contents of
register CL into the data segment memory location addressed by BX plus DI.

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 7. Register relative addressing:
🞂​ Register relative addressing moves a byte or word between a register and the
memory location addressed by an index or base register plus a displacement.
🞂​ Example: MOV AX,[BX+4] or MOV AX,ARRAY[BX].
🞂​ The first instruction loads A X from the data segment address formed by BX plus [Link]
second instruction loads A X from the data segment memory location in ARRAY plus
the contents of BX.

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[Link] relative-plus-index addressing
🞂​ Base relative-plus-index addressing transfers a byte or word between a register and
the memory location addressed by a base and an index register plus a displacement.
🞂​ Example: MOV AX, ARRAY[BX+DI] or MOV AX, [BX+DI+4].
🞂​ These instructions load A X from a data segment memory [Link] first instruction uses
an address formed by adding ARRAY, BX, and DI and the second by adding BX, DI, and 4.

114
Prepared By Girmay G. March 2024
3.2 Program Memory-Addressing Modes
🞂​ This type of addressing mode is required for the instructions that causes a
branch program.

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116 March 2024
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Program Memory Addressing Modes
🞂​ Program memory-addressing modes, used with the JMP (jump) and CALL
instructions, consist of three distinct forms:
🞂​ direct,
🞂​ relative,
🞂​ and indirect.
🞂​ This section introduces these three addressing forms, using the JMP
instruction to illustrate their operation.

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1. Direct program memory addressing
🞂​ Direct program memory addressing is what many early microprocessors
used for all jumps and calls.
🞂​ Direct program memory addressing is also used in high-level languages,
such as the GOTO instruction.
🞂​ The microprocessor uses this form of addressing, but not as often as
relative and indirect program memory addressing are used.

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🞂​ The instructions for direct program memory addressing store the address
with the opcode. For example, if a program jumps to memory location
10000H for the next instruction, the address (10000H) is stored following the
opcode in the memory.
🞂​ the direct intersegment JMP instruction and the 4 bytes required to store the address
10000H.
🞂​ This JMP instruction loads CS with 1000H and IP with 0000H to jump to memory
location 10000H for the next instruction.

🞂​ An intersegment jump is a jump to any memory location within the entire

memory system.)
🞂​ The direct jump is often called a far jump because it can jump to any memory
location for the next instruction.
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2. Relative Program Memory Addressing
🞂​ Relative program memory addressing is not available in all early
microprocessors, but it is available to this family of microprocessors.(8086)
🞂 ​ The term relative means “relative to the instruction pointer (IP)”.
🞂 ​ For example, if a JMP instruction skips the next 2 bytes of memory, the
address in relation to the instruction pointer is a 2 that adds to the
instruction pointer.
🞂 ​ This develops the address of the next program instruction.

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🞂​ An example of the relative JMP instruction is shown below.

🞂​ Note that the JMP instruction is a 1-byte instruction, with a 1-byte or a 2-

byte displacement that adds to the instruction pointer.
🞂​ A 1-byte displacement is used in short jumps, and a 2-byte displacement is
used with near jumps and calls.
🞂​ Both types are considered to be intrasegment jumps.
🞂​ An intrasegment jump is a jump anywhere within the current code
segment.
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3. Indirect Program Memory Addressing
🞂​ The microprocessor allows several forms of program indirect memory
addressing for the JMP and CALL instructions.

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 3. Stack Memory Addressing Modes

🞂​ The stack plays an important role in all microprocessors.

🞂​ It holds data temporarily and stores the return addresses used by procedures.
🞂​ The stack memory is an LIFO (last-in, first-out) memory, which describes the
way that data are stored and removed from the stack.
🞂​ Data are placed onto the stack with a P U S H instruction and removed with a
PO P instruction.
🞂​ The CALL instruction also uses the stack to hold the return address for
procedures and a RET (return) instruction to remove the return address from
the stack.

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🞂​ The stack memory is maintained by two registers:
🞂​ the stack pointer (SP)
🞂​ the stack segment register (SS).
🞂​ Whenever a word of data is pushed onto the stack, the high-order 8
bits are placed in the location addressed by SP – 1.
🞂​ The low-order 8 bits are placed in the location addressed by SP – 2.
🞂​ The SP is then decremented by 2 so that the next word of data is stored in the
next available stack memory location.
🞂​ The SP register always points to an area of memory located within the stack
[Link] SP register adds to SS x 10h to form the stack memory address in
the real mode.
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🞂​ Whenever data are popped from the stack, the low-order 8 bits are
removed from the location addressed by [Link] high-order 8 bits are
removed from the location addressed by SP+[Link] SP register is then
incremented by 2.

🞂​ Note that P U S H and PO P store or retrieve words of data—never

bytes—in the 8086 microprocessors.
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 Thanks

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 Chapter 4
INSTRUCTIONS

127 127 Prepared By Girmay G. March 2024

Contents
🞂​ 4.1. Data Movement Instructions

🞂​ 4.1.1 MOV Revisited

🞂​ 4.1.2 PUSH/POP

🞂​ 4.1.3 Load-Effective Address

🞂​ 4.1.4 String Data Transfers

🞂​ 4.2: Arithmetic and Logic instructions

🞂​ 4.2.1 Arithmetic Instructions

🞂​ 4.2.2 Basic Logic Instructions

🞂​ 4.2.3 Shift and Rotate

🞂​ 4.2.4 String Comparisons

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4.1. Data Movement Instructions
🞂 ​ These instructions are used to transfer data from source to
destination.
🞂 ​ Also called as Data Transfer Instructions
🞂 ​ The operand can be a constant, memory Location, register or
I/O port address.
 If the oprand is constant vakue we have to assign radex.
 Common radix characters:
 h – hexadecimal
 d – decimal
 b – binary
 O/q octal

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Cont..
🞂​ x86 assembly language uses different types of instruction
operands.
Syntax
mnemonic [destination], [ source]
🞂 ​ The Source and destination can be one of the
following
🞂 ​ Immediate—uses a numeric literal expression
🞂 ​ Register—uses a named register in the CPU
🞂 ​ M emory—references a memory location

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1. M O V Instruction
🞂​ The M O V instruction copies data from a source operand
to a destination operand.
🞂​ Known as a data transfer instruction, it is used in
virtually every program.
🞂​ Its basic format shows that the first operand is the
destination and the second operand is the source:

Syntax
: MOV destination, source

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Cont..
🞂​ MOV is very flexible in its use of operands, as long as the following rules are
observed:
 Both operands must be the same size.
 Both operands cannot be memory operands.
 CS, EIP, and IP cannot be destination operands.
 An immediate value cannot be moved to a segment register
🞂​ The ff are correct
🞂 ​ MOV reg,reg
🞂 ​ MOV mem,reg
🞂 ​ MOV reg,mem
🞂 ​ MOV mem,imm
🞂 ​ MOV reg,imm

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Example

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2. X C H G Instruction
The XCHG (exchange data) instruction exchanges the contents of two
operands.
🞂 ​ It exchange the contents of the sourse and Destination.
There are three variants:
🞂​ XCHG reg,reg Example:
🞂​ XCHG reg,mem
xchg ax,bx ; exchange 16-bit regs
🞂​ XCHG mem,reg
xchg ah,al ; exchange 8-bit regs
xchg var1,bx ; exchange 16-bit mem op with B X
xchg eax,ebx ; exchange 32-bit regs
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3. POP/Push instructions
🞂​ PUSH D
🞂​ pushes D to the stack example : PUSH D X
🞂​ POP D
🞂​ pops the stack to D example: POP AS

Examples

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4. Load Effective Address(LEA)
🞂​ Computes the Effective address of the second operand( the source operand )
and stores it in the 1st operand (Destination Operand).
🞂​ The main deference b/n move and LDA is
🞂​ LEA means Load Effective Address
🞂​ MOV means Load Value

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4.1.4 String data Transfer
🞂​ String is s series of data byte or word available in
memory at consecutive locations.
🞂​ It is either referred as byte string or word string.
🞂​ Their memory is always allocated in a sequential order.
🞂​ Instructions used to manipulate strings are called string
manipulation instructions.

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Some instructions

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4.2 Arithmetic and Logic instructions
🞂​ 4.2.1 Arithmetic Instructions
🞂​ 4.2.2 Basic Logic Instructions
🞂​ 4.2.3 Shift and Rotate

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 4.2.1 Arithmetic Instructions
🞂 ​ There are different instruction set. Let’s begin with
1. INC (increment),
2. DEC (decrement),
The syntax is
🞂​ INC reg/mem
🞂 ​ DEC reg/mem

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Cont.…
3 . A D D (add),
🞂 ​ The A D D instruction adds a source operand to a destination operand of the same size.
🞂 ​ The syntax is
A D D dest , source
Example:
.CODE
MOV AL, 10H ;Sets AL to 10H
MOV BH, 75H ;Sets BX to 23H
ADD AL, BH ;Store the sum of AL and BX in AL
MOV CX, 0F21Ah ;Set CX to 0F21Ah
ADD [0154H], CX ;Store sum of CX data and data at memory address DS:0154 into the same
memory address
MOV AH, 9FH ;Sets AH to 9FH
ADD AH,BH ;Store sum of AH and BH into BH
RET ;stops the program
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Cont..
[Link] (subtract)
🞂 ​ The SUB instruction subtracts a source operand from a destination
[Link] set of possible operands is the same as for the A D D
and MOV instructions.
🞂​ Flags The Carry, Zero, Sign, Overflow,Auxiliary Carry, and Parity flags are
changed according to the value that is placed in the destination operand
🞂​ The syntax is
SUB dest ,source

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5. Mul and DIV Instruction
🞂 ​ MUL
🞂 ​ Its operand is8-bit reg
🞂 ​ Used to multiply and divide unsigned byte by byte/word by
word.
🞂 ​ Example :

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6. N E G
🞂​ NEG D
🞂​ This operation performs 2’s compliment of D
🞂​ What is the output (value) stored in Ax? In the following example

🞂​ 250h in binary is 0000001001010000 so,

🞂​ it 2’s compliment will be 1111110110101111 +1
🞂​ 1111110110110000 = FDBDh
🞂​ therefore Ax will store FDBD

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7. CMP : Compare
🞂​ This instruction compares the source operand, which may be a register or
an
immediate data or a memory location, with a destination operand that may
be a register or a memory location
Eg.
🞂​ CMP BX, 0100H
CMP AX, 0100H
CMP [5000H], 0100H
CMP BX, [SI]
CMP BX, CX

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Cont..
🞂​ NOTE: In Addition and Multiplication if they produce results > 16 bits it will
be stored in D X register

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 4.2.2 Basic Logic Instructions
🞂​ The processor instruction set provides the instructions
🞂 ​ AND,
🞂 ​ OR,
🞂 ​ XOR,
🞂 ​ NOT Boolean logic,
🞂​ which tests, sets, and clears the bits according to the need of the
program.

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I. The AND instruction
🞂​ performs a Boolean (bitwise) A N D operation between each pair of matching
bits in two operands and places the result in the destination operand:

A N D destination, source
🞂​ The following operand combinations are permitted:
AND reg,reg
AND reg,mem
AND reg,imm
AND mem,reg
AND mem,imm

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Cont..
🞂​ For example, suppose AL is initially set to 10101110 binary. After
ANDing it with 11110110, AL equals 10100110:

mov al,10101110b
and al,11110110b ; result in AL = 10100110

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Application of AND Instruction
 Converting Characters to Upper Case
o The AND instruction provides an easy way to translate a
letter from lowercase to uppercase.
o If we compare the ASCII codes of capital A and lowercase a,
it becomes clear that only bit 5 is different:
o If we AND any character with 11011111 binary, all bits are
unchanged except for bit 5, which is cleared.
o 0 1 1 0 0 0 0 1 = 61h ('a')
0 1 0 0 0 0 0 1 = 41h ('A')

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II. OR Instruction
🞂​ The OR instruction performs a Boolean OR operation between each pair of
matching bits in two operands and places the result in the destination
operand:
OR destination ,source
🞂​ The OR instruction uses the same operand combinations as the A N D
instruction:
OR reg,reg For example, if AL is initially equal to 11100011
OR reg,mem binary and then we OR it with 00000100, the
OR reg,imm result equals 11100111:
OR mem,reg
mov al,11100011b
OR mem,imm
and al,00000100b; result in AL = 11100111
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EXMPLES

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III. The X O R Instruction
🞂​ The X OR instruction implements the bitwise X OR operation.
🞂​ The X O R operation sets the resultant bit to 1, if and only if the bits from the
operands are different.
🞂​ If the bits from the operands are same (both 0 or both 1), the resultant bit is
cleared to 0.

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IV. NOT Instruction
🞂​ The complement of a set can be generated using the
NOT instruction, which reverses all bits.
🞂 ​ Example :

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4.3 Shift and rotate instructions
 There are two ways to shift an operand’s bits.
 The first,
 Logical shift, fills the newly created bit
position with zero.

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Cont..
 In the following illustration, a byte is logically shifted one
position to the right.
 In other words, each bit is moved to the next lowest bit position.
 Note that bit 7 is assigned 0:
 Example
o The following illustration shows a single logical right
shift on the binary value 11001111,
o producing 01100111.
o The lowest bit is shifted into the Carry flag:

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Cont..
 Second an arithmetic shift.
 The newly created bit position is filled with a
copy of the original number’s sign bit:
 Example
o Binary 11001111, for example, h a s a 1 in the
sign bit.
o When shifted arithmetically 1 bit to the right,
it becomes 11100111:
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1 . S H L Instruction
o The S H L (shift left) instruction performs a
logical left shift on the destination operand,
filling the lowest bit with 0 .
o The highest bit is moved to the Carry flag, and the
bit that w a s in the Carry flag is discarded:
🞂​ Example
mov bl,8Fh ; BL = 10001111b
shl bl,1 ; CF = 1, BL = 00011110b

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Application of S H L
 Bitwise Multiplication: S H L can perform multiplication by powers
of 2.
o Shifting any operand left by n bits multiplies the operand by 2 n .
o For example, shifting the integer 5 left by 1 bit yields the product
of 5 x 2 1 = 10:
mov dl,5 dl= 00000101
shl dl,1 dl=00001010
o Exercise what will be the value of the Dl in decimal after SHl by 3
is performed
o mov dl,5 dl= 00000101
shl dl,3 dl=

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Cont..
 SHRInstruction
o The SHR(shift right) instruction performs a logical right shift on the destination
operand, replacing the highest bit with a 0.
o The lowest bit is copied into the Carry flag, and the bit that was previously
in the Carry flag is lost:

o Example In the following example, the 0 from the lowest bit

in ALis copied into the Carry flag, and the highest bit in ALis filled with a zero:

mov al,0D0h ; AL=11010000b

shr al,1 ; AL=01101000b, CF= 0
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Application of S H R
o Bitwise Division: Logically shifting an unsigned integer right by n bits
divides the operand by 2n.
🞂
 In the following statements, we divide 32 by 21, producing 16:
mov dl,32 ; dl=100000
shr dl,1 ; dl=010000 cf=0
 Exercise , write an assembly program that divide 32 by 23 using SHR:
mov dl,32 ; dl=100000
shr dl,3 ; dl=0000100 cf=0
 Write an assembly program that divide 32 by 24 using SHR

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R OL Instruction
🞂​ The ROL (rotate left) instruction shifts each bit to the left.
🞂​ The highest bit is copied into the Carry flag and the lowest bit position.
🞂

mov al,40h ;AL = 01000000b

rol al,1 ;AL = 10000000b, CF = 0
rol al,1 ;AL = 00000001b, CF = 1
rol al,1 ;AL = 00000010b, CF = 0
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Cont..
🞂​ Multiple Rotations:
🞂​ When using a rotation count greater than 1, the Carry flag contains the last bit
rotated out of the MSB position:
🞂​ mov al,00100000b
🞂​ rol al,3 ; CF = 1,AL = 00000001b
🞂​ Exchanging Groups of Bits:
🞂​ You can use ROL to exchange the upper (bits 4–7) and lower (bits 0–3) halves of a
byte.
🞂​ For example, 26h rotated four bits in either direction becomes 62h:
 mov al,26h
 rol al,4 ;AL = 62h

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R O R Instruction
🞂​ The ROR (rotate right) instruction shifts each bit to the right and copies the
lowest bit into the Carry flag and the highest bit position.
🞂

mov al,01h ;AL = 00000001b

ror al,1 ;AL = 10000000b, CF = 1
ror al,1 ;AL = 01000000b, CF = 0

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Cont..
🞂​ Multiple Rotations:
🞂​ When using a rotation count greater than 1, the Carry flag contains the last bit
rotated out of the LSB position:
🞂​ mov al,00000100b
🞂​ ror al,3 ;AL = 10000000b, CF = 1
🞂​ RCL and RCR Instructions
🞂​ The RCL (rotate carry left) instruction shifts each bit to the left, copies the Carry flag
to the LSB, and copies the MSB into the Carry flag

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Cont..
🞂​ RCR Instruction:
🞂​ The RCR (rotate carry right) instruction shifts each bit to the right, copies the
Carry flag into the MSB, and copies the LSB into the Carry flag:

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