14 November 2024 22:38

UNIT–I NOTES
1. Boolean Algebra and Logic
1.1 Boolean Algebra
Boolean algebra deals with variables that take binary values: 0 or 1.
It is used to analyze and simplify digital circuits.
1.2 Basic Boolean Operations
Operation Symbol Meaning
AND • or no symbol (AB) Output is 1 only if all inputs are 1
OR + Output is 1 if any input is 1
NOT ̅ Inverts the input (0→1, 1→0)

1.3 Basic Laws of Boolean Algebra

I. Commutative Laws
• A+B=B+A
• AB = BA
II. Associative Laws
• (A + B) + C = A + (B + C)
• (AB)C = A(BC)
III. Distributive Laws
• A(B + C) = AB + AC
• A + BC = (A + B)(A + C)
IV. Identity Laws
• A+0=A
• A•1=A
V. Null (Dominance) Laws
• A+1=1
• A•0=0
VI. Idempotent Laws
• A+A=A
• A•A=A
VII. Involution Law
• (A)̅ = A
VIII. Complement Laws
• A+A=1
• A • A̅ = 0
IX. Absorption Laws
• A + AB = A
• A(A + B) = A

1.4 Logic Gates

Basic Gates
• AND
• OR

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 • OR
• NOT
Universal Gates
• NAND
• NOR
○ Any digital circuit can be built using only NAND or only NOR.
Derived Gates
• XOR (Exclusive OR): A ⊕ B = AB + AB
• XNOR: (A ⊕ B)̅

2. Simplification Using K-Maps

2.1 Karnaugh Maps (K-map)
A graphical method to simplify Boolean expressions.
• 2 variables → 4 cells
• 3 variables → 8 cells
• 4 variables → 16 cells
Used to get minimal SOP (Sum of Products) or POS (Product of Sums) forms.
2.2 Grouping Rules
• Groups must be 1, 2, 4, 8… (powers of 2)
• Make largest possible groups
• Groups can wrap around the edges
• Overlapping is allowed
2.3 Don’t Care Conditions (X)
• Used when output is not important for certain input combinations
• Can be taken as 1 or 0 to help minimization

3. Arithmetic Circuits
3.1 Half Adder
• Adds 2 single bits
• Outputs: Sum (S) and Carry (C)
Input Output
S = A ⊕ B C = AB

3.2 Full Adder

• Adds 3 bits (A, B, Cin)
• Outputs Sum and Carry
Equations:
• S = A ⊕ B ⊕ Cin
• Cout = AB + BCin + ACin
3.3 Half Subtractor
• Inputs: A (minuend), B (subtrahend)
• Outputs: Difference (D), Borrow (Bo)
• D=A⊕B
• Bo = AB
3.4 Full Subtractor
• Inputs: A, B, Bin
• D = A ⊕ B ⊕ Bin
• Bout = AB + B Bin + A Bin
3.5 Parallel Binary Adder/Subtractor
• Uses multiple full adders
• For subtraction, add 2’s complement of subtrahend:
○ B’ = B + 1
• Achieved using:

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 • Achieved using:
○ XOR gates for conditional inversion
○ Cin = 1 for subtraction mode

4. Combinational Circuits
4.1 Multiplexer (MUX)
• Selects one input from many inputs
• Controlled by selection lines
• Example:
○ 4-to-1 MUX → 4 inputs, 2 select lines
Equation (4:1 MUX):
Y = S1̅S0̅ I0 + S1̅S0 I1 + S1S0̅ I2 + S1S0 I3

4.2 Demultiplexer (DEMUX)

• Opposite of MUX
• Sends single input to one of many outputs
Example: 1-to-4 DEMUX
Outputs depend on select lines.

4.3 Decoder
• Converts binary input into 2ⁿ unique outputs
• 2-to-4 decoder
• 3-to-8 decoder
Example (2-to-4):
Y0 = AB
Y1 = AB
Y2 = A B
Y3 = A B
Used in memory address decoding.

4.4 Encoder
• Opposite of decoder
• Converts 2ⁿ inputs into n-bit code
• Example: 8-to-3 encoder
Prioritized encoders handle multiple active inputs.

SHORT EXAM POINTS / 2–3 Marks

• NAND and NOR are universal gates
• XOR used in adders
• Decoder: n → 2ⁿ
• MUX: data selector
• K-Map groups must be power of 2
• Don’t care ↑ → helps minimiza on

LONG ANSWER POINTS / 8–10 Marks

• Explain Boolean laws with proofs
• Draw truth tables & logic diagrams of adders/subtractors
• Explain K-Map simplification with examples
• Design MUX/DEMUX/Decoder circuits
• Compare SOP vs POS
• Derive expressions of parallel adder/subtractor

Absolutely — here is a more advanced, detailed, college-level version of UNIT-II notes with

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Absolutely — here is a more advanced, detailed, college-level version of UNIT-II notes with
deeper explanations, equations, timing diagrams (described textually), and design principles.

UNIT–II: Sequential Logic, Flip-Flops, Shift Registers

& Counters
1. Sequential Circuits Overview
Sequential circuits differ from combinational circuits because they include a memory element.
They depend on:
[
\text{Output} = f(\text{Present Inputs}, \text{Past State})
]
Classification:
Type Clock Example
Asynchronous No common clock Latches
Synchronous Controlled by common clock Flip-Flops, Registers, Counters

2. Latches (Asynchronous Building Blocks)

S-R (NOR) Latch
Equations:
[
Q(t+1) = \overline{R + \overline{Q(t)} \cdot S}
]
Issues: Invalid when S = R = 1 → both outputs = 0 (violates complementarity).

Gated S-R Latch

Clock/Enable input controls whether latch accepts data.

D Latch (Transparent Latch)

[
Q(t+1) = D \quad \text{(when Enable = 1)}
]
Used for data synchronization and pipeline registers.

3. Flip-Flops (Edge Triggered)

Flip-flops eliminate transparency and glitch problems in latches.
Edge Triggering
• Positive edge (↑) — data stored only at rising edge.
• Negative edge (↓) — falling edge.

Important Timing Parameters

Parameter Description
Setup Time (Ts) Minimum time input must be stable before clock edge
Hold Time (Th) Minimum time input must remain stable after clock edge
Propagation Delay (tpd) Time taken for output to stabilize
Clock-to-Q Delay Measured from active clock edge to output change
Timing diagram must show D signal stable before/after clock, otherwise data corruption occurs.

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Flip-Flop Types
1. S-R Flip-Flop
Same as latch but clocked.
Equation:
[
Q(t+1) = S + \overline{R}Q(t)
]

2. D Flip-Flop
[
Q(t+1) = D
]
Applications: Registers, Data Buffering, Memory, CPU pipelines.

3. J-K Flip-Flop
Removes invalid state of SR FF.
[
Q(t+1) = J\overline{Q(t)} + \overline{K} Q(t)
]
Case J = K = 1 → toggle opera on.

4. T Flip-Flop
Special case of JK with J = K = 1.
[
Q(t+1) = \overline{Q(t)}
]
Used for frequency division.

4. Race Around Condition

Occurs in JK Flip-Flop when:
• J=K=1
• Level clock is HIGH for longer than propagation delay
Output toggles multiple times → unpredictable state.
Remedies:
✔ Edge-triggered Flip-Flop
✔ Master-Slave Flip-Flop
✔ Reduce clock pulse width

Master-Slave Flip-Flop Working

• Master captures data on clock high
• Slave updates output on clock low
This ensures single toggle per pulse.

5. Flip-Flop Conversion (Realization)

Used when designing sequential circuits from available FF type.
Target Source Relationship
D from JK J = D, K = D’
T from JK J = T, K = T
JK from SR S = JQ', R = KQ
Conversion table technique steps:

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Conversion table technique steps:
1. Write excitation table of required FF
2. Compare with available FF excitation
3. Derive conversion table + logic expression

6. Shift Registers
Shift register = collection of D Flip-Flops connected serially.
General register delay:
[
t_{delay(total)} = n \cdot (Clock \rightarrow Q \ delay)
]
Modes
Type Input Output Example Use
SISO Serial Serial Time delay element
SIPO Serial Parallel ADC interface
PISO Parallel Serial UART transmission
PIPO Parallel Parallel Data storage

Applications:
• Serial communication (UART, SPI)
• Counters
• Sequence generator
• Convolution operations

7. Counters
Counters = sequential circuits that progress through predefined states.
Types:
A. Asynchronous (Ripple) Counter
• Flip-Flops triggered sequentially
• Delay accumulates:
[
t_{pd(total)} = n \cdot t_{pd}
]
Example: 4-bit ripple counter → counts 0–15 (mod-16).

B. Synchronous Counter
All flip-flops triggered by same clock → no ripple delay.
Logic determines when each FF toggles:
[
T_0 = 1,\quad T_1 = Q_0,\quad T_2 = Q_0Q_1 \cdots
]

C. Modulo-N Counters
If:
[
2^n > N
]
then clear/reset FFs when count = N.
Example: MOD-10 (Decade counter) resets after binary 1001.

D. Ring and Johnson Counters

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Type Operation States
Ring Counter Circular shift n states
Johnson Counter Inverted feedback shift 2n states
Applications: Digital clocks, sequence generation, timing circuits.

Exam-Important Diagrams & Tables (Describe if

drawing not allowed)
✔ State Table
✔ State Transition Diagram
✔ Timing Diagram
✔ Excitation Table
✔ Karnaugh Map Minimization for FF Logic

Common 5 & 10 Mark Questions

1. Difference between asynchronous and synchronous counters.
2. Explain race around condition with solution using master-slave J-K flip-flop.
3. Design MOD-6 synchronous counter using T Flip-Flops.
4. Compare registers and counters.
5. Flip-Flop conversion problems.
6. Timing hazard analysis in ripple counters.

If you'd like, I can also give:

📌 Fully solved design problems
📌 Previous exam expected long question answers
📌 One-page rapid revision cheat sheet
Would you like those too?

📌 UNIT–II RAPID REVISION SHEET

Sequen al Circuits Basics
✔ Output depends on: Present Input + Previous State
Q(t+1)=f(Q(t),inputs)Q(t+1) = f(Q(t),\text{inputs})Q(t+1)=f(Q(t),inputs)
✔ Two types:
• Asynchronous: No clock (Latches)
• Synchronous: Clock dependent (FFs, Registers, Counters)

Latches
SR Latch (NOR)
S R Q(next)
0 0 NC
0 1 0
1 0 1
1 1 Invalid

D Latch
Q=D (when Enable = 1)Q = D \text{ (when Enable = 1)}Q=D (when Enable = 1)

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Q=D (when Enable = 1)Q = D \text{ (when Enable = 1)}Q=D (when Enable = 1)

Flip-Flops (Edge Triggered)

Important Timing:
• Setup Time (Ts) – Input stable before clock edge
• Hold Time (Th) – Input stable after clock edge

Flip-Flop Truth Tables

FF Type Inputs Q(next)
SR 00 No Change
01 0
10 1
11 Invalid
D D D
JK 00 NC
01 0
10 1
11 Toggle
T 0 NC
1 Toggle

Race Around Condition

Occurs in JK FF when J=K=1 and clock pulse width > propagation delay.
✔ Solution: Edge Triggering / Master-Slave

Flip-Flop Conversion Shortcuts

Convert Formula
D → JK J = D, K = D′
D→T T=D⊕Q
T → JK J = T, K = T
SR → JK J = S, K = R

Shi Registers
Type Input Output
SISO Serial Serial
SIPO Serial Parallel
PISO Parallel Serial
PIPO Parallel Parallel
✔ Used in: Serial communication, temporary storage, sequence generation.

Counters
Asynchronous (Ripple) Counter
• Triggered one after another
• Slow (cumulative delay)

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 • Slow (cumulative delay)
Max count:
=2n=2^n=2n

Synchronous Counter
• All FFs clocked together
• Faster; no ripple delay

MOD-N Counter Rule

If:
2n>N2^n > N2n>N
→ Reset output when count = N.
Example: MOD-10 counter reset at 1010₂

Ring vs Johnson Counter

Type States Notes
Ring n 1 shifts around
Johnson 2n Feedback of complement

Applica ons (Ready to write list)

✔ Registers → Data storage, Serial-Parallel conversion
✔ Counters → Digital clock, Frequency division, Timers
✔ Flip-Flops → Synchroniza on, Frequency division, FSMs
✔ Shift Registers → UART/SPI, Pa ern genera on

Key Differences
Feature Latch Flip-Flop
Triggering Level-sensitive Edge-triggered
Speed Fast Slower
Use Basic storage Synchronous systems

Here are clean, well-organized, exam-ready notes for UNIT–III (BCA 3rd Sem – Computer
Organization & Architecture). You can directly write these in your exam.

📌 UNIT–III Notes (11 Hours)

Data Transfer Operations & Basic Computer Organization

✅ 1. Data Transfer Operations

1.1 Register Transfer
A register transfer means the movement of binary data from one register to another.
Notation:
R1 ← R2

Meaning: Contents of R2 are transferred to R1.

📌 Control Function Example:
P: R1 ← R2

(Transfer happens only if control signal P = 1)

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(Transfer happens only if control signal P = 1)

1.2 Bus and Memory Transfer

Bus
A bus is a common communication path used to transfer data between registers or memory.
Types of Buses:
Type Description
Data Bus Transfers actual data
Address Bus Carries address of memory location
Control Bus Carries control signals (Read/Write)
📌 Three-state Buffer or Multiplexer is used for bus control.

Memory Transfer
Operations involving memory:
Operation Meaning
Read Memory → Register
Write Register → Memory
Examples:
Read: R1 ← M[Address]
Write: M[Address] ← R1

1.3 Registers and Micro-operations

A micro-operation is the smallest operation performed on data stored in registers.
Types of Micro-operations:
Type Examples
Transfer R1 ← R2
Arithmetic R1 ← R1 + R2
Logic R1 ← R1 AND R2
Shift R1 ← SHR R1 (shi right)

✅ 2. Basic Computer Organization and Design

2.1 Instruction Codes
An instruction code is a binary code that specifies an operation.
General Format:
[Opcode][Address]
Example formats:
• Direct Addressing: Opcode + Memory Address
• Implied Addressing: Only Opcode

2.2 Computer Registers

Common registers in a basic computer:
Register Meaning
AC (Accumulator) Stores intermediate arithmetic results
PC (Program Counter) Holds address of next instruction
IR (Instruction Register) Holds current instruction

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IR (Instruction Register) Holds current instruction
MAR (Memory Address Register) Holds address for memory access
MDR (Memory Data Register) Holds data read/written from memory
TR (Temporary Register) Used internally

2.3 Instruction Cycle

Steps followed by CPU to execute an instruction:
1. Fetch
IR ← M[PC]
PC ← PC + 1

2. Decode
○ CPU decodes opcode.
3. Execute
○ Required operation performed.
📌 If a program branch occurs, PC is updated with new address.

2.4 General Register Organization

• Uses multiple general-purpose registers (R0, R1, R2...)
• Operation performed using an ALU, controlled by control signals.

2.5 Stack Organization

A stack is a Last-In-First-Out (LIFO) memory structure.
• Used in subroutines, expression evaluation.
• Maintained with stack pointer (SP).
Stack Operations:
Operation Meaning
PUSH Insert item into stack
POP Remove item
Example:
SP ← SP – 1
M[SP] ← DR // push opera on

2.6 Instruction Formats

Structure in which an instruction is written.
Types:
Format Type Example
Zero Address Used in stack-based (ex: ADD uses stack)
One Address ADD A
Two Address MOV R1, R2
Three Address ADD R1, R2, R3

2.7 Addressing Modes

Specifies the method to access operands.
Addressing Mode Example Meaning
Immediate MOV R1, 5 Operand is constant value
Direct MOV R1, (2000) Operand stored at memory address
Indirect MOV R1, @(2000) Address stored in another location

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Indirect MOV R1, @(2000) Address stored in another location
Register MOV R1, R2 Operand stored in register
Register Indirect MOV R1, (R2) Register contains address
Indexed MOV R1, (Base + Index) Used in arrays
Relative PC + address Used in branching

⭐ Quick Revision Summary (Exam-Ready)

• Register transfer uses notation: R1 ← R2
• Bus is common data path for multiple registers.
• Memory transfer: Read (Memory → Register), Write (Register → Memory).
• Micro-operations are smallest executable operations.
• Instruction cycle: Fetch → Decode → Execute
• Registers: AC, PC, IR, MAR, MDR, SP, etc.
• Stack uses LIFO, controlled by SP.
• Instruction formats vary by number of addresses.
• Addressing modes decide HOW operand is accessed.
Here you go — well-structured, exam-oriented notes for BCA 3rd Semester, UNIT-IV
(Computer Organization).
You can revise directly from this.

UNIT – IV: Input-Output & Memory Organization

1. Input-Output Organization
1.1 Peripheral Devices
Peripheral devices are external devices connected to the computer for input, output, or
storage.
Type Examples Function
Input devices Keyboard, Mouse, Scanner Provide data to system
Output devices Monitor, Printer, Speaker Display processed data
Storage devices HDD, CD, Pendrive Store data
Peripheral devices usually operate slower than CPU, so I/O modules are required.

1.2 Input-Output Interfaces

The I/O Interface connects the CPU and peripheral devices.
Functions:
• Device communication
• Data buffering
• Error detection
• Control and timing
I/O Interface consists of:
• Data register
• Status register
• Control register

1.3 Asynchronous Data Transfer

Used when CPU and I/O device have different speeds.
Techniques:
1. Strobe Control – One device sends a signal indicating data ready.
2. Handshaking – Both sender and receiver exchange control signals.

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 2. Handshaking – Both sender and receiver exchange control signals.
Example handshake signals:
✔ Data Valid
✔ Data Accepted

1.4 Modes of Data Transfer

1. Programmed I/O
○ CPU continuously checks device status (polling).
○ Slow & CPU dependent.
2. Interrupt-Driven I/O
○ Device sends interrupt when ready.
○ CPU is free until interrupt occurs.
3. Direct Memory Access (DMA)
○ Data transfers directly between memory and device without CPU.
○ Fastest method.

1.5 Priority Interrupt

Used when multiple devices request interrupt.
Priority Methods:
Type Meaning
Daisy Chaining Serial priority arrangement
Polling CPU checks device priority list
Hardware priority encoder Generates priority signal automatically

1.6 Direct Memory Access (DMA)

DMA controller handles high-speed data transfer.
DMA Steps:
1. CPU sends DMA request.
2. DMA takes control of bus.
3. Data transferred directly between memory & device.
4. DMA sends interrupt after completion.
Advantages:
• Fast data transfer
• CPU remains free

2. Memory Organization
2.1 Types of Memory
Memory hierarchy:
Registers → Cache → Main Memory (RAM) → Secondary Memory → Backup Storage
(Fastest → Slowest)
(Most Expensive → Cheapest)

2.2 Main Memory

• Directly accessed by CPU
• Implemented using RAM and ROM
Type Description
RAM Read/Write, volatile memory
ROM Permanent data, non-volatile

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2.3 Auxiliary (Secondary) Memory
Used for long-term storage.
Examples:
✔ Hard Disk
✔ CD/DVD
✔ Pendrive
✔ Magnetic Tape
Characteristics:
• Non-volatile
• Large storage
• Slower than RAM

2.4 Associative Memory

Also called Content Addressable Memory (CAM).
• Data is accessed based on content not address.
• Used in cache lookup and translation tables.

2.5 Cache Memory

Small, high-speed memory between CPU & RAM.
Cache operates on the principle of:
• Temporal locality → recently used data is reused
• Spatial locality → nearby memory addresses are likely accessed
Cache Mapping Techniques:
Mapping Type Description
Direct Mapping One memory block maps to one fixed cache line
Associative Mapping Any block can go to any cache location
Set Associative Mapping Combination of both

2.6 Virtual Memory

Technique that uses secondary storage (HDD/SSD) as an extension of RAM.
• Allows running programs larger than physical memory.
• Based on paging and segmentation.
Advantages:
• Improves multitasking
• Cost effective

Page Table
Maps virtual addresses to physical memory.
Example:
Virtual Address → Page Number → Frame Number → Physical Address

Exam Short Questions (2–5 Marks)

✔ Define DMA.
✔ Difference between Interrupt-driven I/O and Programmed I/O.
✔ What is cache memory?
✔ Explain concept of virtual memory.
✔ What is associative memory?

Important 10-Mark Questions

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Important 10-Mark Questions
1. Explain DMA with neat block diagram.
2. Describe cache memory and explain different mapping techniques.
3. Describe modes of data transfer.
4. Explain virtual memory, paging, and segmentation.

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