library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- for unsigned and arithmetic
-------------------------------------------------------------------------------
-- 1) 16-bit Adder (adder16)
-------------------------------------------------------------------------------
entity adder16 is
port (
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0);
Cin : in std_logic;
Sum : out std_logic_vector(15 downto 0);
Cout : out std_logic
);
end entity adder16;
architecture rtl of adder16 is
signal a_u : unsigned(15 downto 0);
signal b_u : unsigned(15 downto 0);
signal result : unsigned(16 downto 0);
begin
-- Type conversions (concurrent)
a_u <= unsigned(A);
b_u <= unsigned(B);
-- Combinational addition. Use "all" in sensitivity to be safe in simulators
process (all)
begin
-- extend to 17 bits to capture carry-out
result := ('0' & a_u) + ('0' & b_u);
if Cin = '1' then
result := result + 1;
end if;
Sum <= std_logic_vector(result(15 downto 0));
Cout <= result(16);
end process;
end architecture rtl;
-------------------------------------------------------------------------------
-- 2) 8x1 16-bit Multiplexer (mux8x1_16)
-------------------------------------------------------------------------------
entity mux8x1_16 is
port (
in0 : in std_logic_vector(15 downto 0);
in1 : in std_logic_vector(15 downto 0);
in2 : in std_logic_vector(15 downto 0);
in3 : in std_logic_vector(15 downto 0);
in4 : in std_logic_vector(15 downto 0);
in5 : in std_logic_vector(15 downto 0);
in6 : in std_logic_vector(15 downto 0);
in7 : in std_logic_vector(15 downto 0);
sel : in std_logic_vector(2 downto 0);
outp: out std_logic_vector(15 downto 0)
);
end entity mux8x1_16;
architecture rtl of mux8x1_16 is
begin
process (all)
begin
case sel is
when "000" => outp <= in0;
when "001" => outp <= in1;
when "010" => outp <= in2;
when "011" => outp <= in3;
when "100" => outp <= in4;
when "101" => outp <= in5;
when "110" => outp <= in6;
when "111" => outp <= in7;
when others => outp <= (others => '0'); -- safe default for X/U sel
end case;
end process;
end architecture rtl;
-------------------------------------------------------------------------------
-- 3) Top-level structural module (muxed_adder16)
-- B input of adder is driven by the mux output.
-------------------------------------------------------------------------------
entity muxed_adder16 is
port (
A : in std_logic_vector(15 downto 0);
M0 : in std_logic_vector(15 downto 0);
M1 : in std_logic_vector(15 downto 0);
M2 : in std_logic_vector(15 downto 0);
M3 : in std_logic_vector(15 downto 0);
M4 : in std_logic_vector(15 downto 0);
M5 : in std_logic_vector(15 downto 0);
M6 : in std_logic_vector(15 downto 0);
M7 : in std_logic_vector(15 downto 0);
sel : in std_logic_vector(2 downto 0);
Cin : in std_logic;
Sum : out std_logic_vector(15 downto 0);
Cout: out std_logic
);
end entity muxed_adder16;
architecture structural of muxed_adder16 is
-- Component declarations must match above entities
component mux8x1_16
port (
in0 : in std_logic_vector(15 downto 0);
in1 : in std_logic_vector(15 downto 0);
in2 : in std_logic_vector(15 downto 0);
in3 : in std_logic_vector(15 downto 0);
in4 : in std_logic_vector(15 downto 0);
in5 : in std_logic_vector(15 downto 0);
in6 : in std_logic_vector(15 downto 0);
in7 : in std_logic_vector(15 downto 0);
sel : in std_logic_vector(2 downto 0);
outp: out std_logic_vector(15 downto 0)
);
end component;
component adder16
port (
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0);
Cin : in std_logic;
Sum : out std_logic_vector(15 downto 0);
Cout : out std_logic
);
end component;
signal B_mux : std_logic_vector(15 downto 0);
begin
u_mux : mux8x1_16
port map (
in0 => M0,
in1 => M1,
in2 => M2,
in3 => M3,
in4 => M4,
in5 => M5,
in6 => M6,
in7 => M7,
sel => sel,
outp=> B_mux
);
u_adder : adder16
port map (
A => A,
B => B_mux,
Cin => Cin,
Sum => Sum,
Cout => Cout
);
end architecture structural;